ADS7049-Q1 小型低功耗 12 位、2MSPS SAR ADC

The ADS7049-Q1 is an ultra-low-power, miniature analog-to-digital converter (ADC) that supports a wide analog input range. The analog input range for the device is defined by the AVDD supply voltage. The device samples the input voltage across the AINP and AINM pins on the CS falling edge and starts the conversion. The clock provided on the SCLK pin is used for conversion and data transfer. During conversions, both the AINP and AINM pins are disconnected from the sampling circuit. After the conversion completes, the sampling capacitors are reconnected across the AINP and AINM pins and the ADS7049-Q1 enters acquisition phase.

The device has an internal offset calibration. The offset calibration can be initiated by the user either on power-up or during normal operation; see the Offset Calibration section for more details.

The device also provides a simple serial interface to the host controller and operates over a wide range of digital power supplies. The ADS7049-Q1 requires only a 32-MHz SCLK for supporting a throughput of 2 MSPS. The digital interface also complies with the JESD8-7A (normal range) standard. The Functional Block Diagram section provides a block diagram of the device.

8.3.1 Reference

The device uses the analog supply voltage (AVDD) as a reference, as shown in Figure 33. The AVDD pin is recommended to be decoupled with a 3.3-µF, low equivalent series resistance (ESR) ceramic capacitor.. The AVDD pin functions as a switched capacitor load to the source powering AVDD. The decoupling capacitor provides the instantaneous charge required by the internal circuit and helps in maintaining a stable dc voltage on the AVDD pin. The AVDD pin is recommended to be powered with a low output impedance and low-noise regulator (such as the TPS73230).

Figure 33. Reference for the Device

8.3.2 Analog Input

The device supports single-ended analog inputs. The ADC samples the difference between AINP and AINM and converts for this voltage. The device is capable of accepting a signal from –100 mV to 100 mV on the AINM input and is useful in systems where the sensor or signal-conditioning block is far from the ADC. In such a scenario, there can be a difference between the ground potential of the sensor or signal conditioner and the ADC ground. In such cases, use separate wires to connect the ground of the sensor or signal conditioner to the AINM pin. The AINP input is capable of accepting signals from 0 V to AVDD. Figure 34 represents the equivalent analog input circuits for the sampling stage. The device has a low-pass filter followed by the sampling switch and sampling capacitor. The sampling switch is represented by an R_S (typically 50 Ω) resistor in series with an ideal switch and C_S (typically 15 pF) is the sampling capacitor. The ESD diodes are connected from both analog inputs to AVDD and ground.

Figure 34. Equivalent Input Circuit for the Sampling Stage

The analog input full-scale range (FSR) is equal to the reference voltage of the ADC. The reference voltage for the device is equal to the analog supply voltage (AVDD). Thus, the device FSR can be determined by Equation 1:

8.3.3 ADC Transfer Function

The device output is in straight binary format. The device resolution for a single-ended input can be computed by Equation 2:

Figure 35 and Table 1 show the ideal transfer characteristics for the device.

Figure 35. Ideal Transfer Characteristics

8.3.4 Serial Interface

The device supports a simple, SPI-compatible interface to the external host. The CS signal defines one conversion and serial transfer frame. A frame starts with a CS falling edge and ends with a CS rising edge. The SDO pin outputs the ADC conversion results. Figure 36 shows a detailed timing diagram for the serial interface. A minimum delay of t_{SU_CSCK} must elapse between the CS falling edge and the first SCLK falling edge. The device uses the clock provided on the SCLK pin for conversion and data transfer. The conversion result is available on the SDO pin with the first two bits set to 0, followed by 12 bits of the conversion result. The first zero is launched on the SDO pin on the CS falling edge. Subsequent bits (starting with another 0 followed by the conversion result) are launched on the SDO pin on subsequent SCLK falling edges. The SDO output remains low after 14 SCLKs. A CS rising edge ends the frame and brings the serial data bus to tri-state. For acquisition of the next sample, a minimum time of t_ACQ must be provided after the conversion of the current sample is completed. For details on timing specifications, see the Timing Requirements table.

The device initiates an offset calibration on the first CS falling edge after power-up and the SDO output remains low during the first serial transfer frame after power-up. For further details, see the Offset Calibration section.

Figure 36. Serial Interface Timing Diagram

8.4.1 Offset Calibration

The ADS7049-Q1 includes a feature to calibrate the device internal offset. During offset calibration, the analog input pins (AINP and AINM) are disconnected from the sampling stage. The device includes an internal offset calibration register (OCR) that stores the offset calibration result. The OCR is an internal register and cannot be accessed by the user through the serial interface. The OCR is reset to zero on power-up. Therefore, it is recommended to calibrate the offset on power-up in order to bring the offset error within the specified limits. If the operating temperature or analog supply voltage reflect a significant change, the offset can be recalibrated during normal operation. Figure 37 shows the offset calibration process.

1. See the Timing Requirements section for timing specifications.

2. See the Offset Calibration During Normal Operation section for details.

3. See the Offset Calibration on Power-Up section for details.

4. The power recycle on the AVDD supply is required to reset the offset calibration and to bring the device to a power-up state.

Figure 37. Offset Calibration

8.4.1.1 Offset Calibration on Power-Up

The device initiates offset calibration on the first CS falling edge after power-up and calibration completes if the CS pin remains low for at least 16 SCLK falling edges after the first CS falling edge. The SDO output remains low during calibration. The minimum acquisition time must be provided after calibration for acquiring the first sample. If the device is not provided with at least 16 SCLKs during the first serial transfer frame after power-up, the OCR is not updated. Table 2 provides the timing parameters for offset calibration on power-up.

For subsequent samples, the device adjusts the conversion results with the value stored in the OCR. The conversion result adjusted with the value stored in OCR is provided by the device on the SDO output. Figure 38 shows the timing diagram for offset calibration on power-up.

Table 2. Offset Calibration on Power-Up

		MIN	TYP	MAX	UNIT
fCLK-CAL	SCLK frequency for calibration			16	MHz
tPOWERUP-CAL	Calibration time at power-up	15 × tSCLK			ns
tACQ	Acquisition time	90			ns
tPH_CS	CS high time	tACQ			ns
tSU_CSCK	Setup time: CS falling to SCLK falling	12			ns
tD_CKCS	Delay time: last SCLK falling to CS rising	10			ns

Figure 38. Offset Calibration on Power-Up Timing Diagram

8.4.1.2 Offset Calibration During Normal Operation

Offset calibration can be done during normal device operation if at least 32 SCLK falling edges are provided in one serial transfer frame. During the first 14 SCLKs, the device converts the sample acquired on the CS falling edge and provides data on the SDO output. The device initiates the offset calibration on the 17th SCLK falling edge and calibration completes on the 32nd SCLK falling edge. The SDO output remains low after the 14th SCLK falling edge and SDO goes to tri-state after CS goes high. If the device is provided with less than 32 SCLKs during a serial transfer frame, the OCR is not updated. Table 3 provides the timing parameters for offset calibration during normal operation.

For subsequent samples, the device adjusts the conversion results with the value stored in the OCR. The conversion result adjusted with the value stored in the OCR is provided by the device on the SDO output. Figure 39 shows the timing diagram for offset calibration during normal operation.

Table 3. Offset Calibration During Normal Operation

		MIN	TYP	MAX	UNIT
fCLK-CAL	SCLK frequency for calibration			16	MHz
tCAL	Calibration time during normal operation	15 × tSCLK			ns
tACQ	Acquisition time	90			ns
tPH_CS	CS high time	tACQ			ns
tSU_CSCK	Setup time: CS falling to SCLK falling	12			ns
tD_CKCS	Delay time: last SCLK falling to CS rising	10			ns

Figure 39. Offset Calibration During Normal Operation Timing Diagram

9.2.1 Design Requirements

The goal of this application is to design a single-supply digital acquisition (DAQ) circuit based on the ADS7049-Q1 with SNR greater than 70 dB and THD less than –80 dB for input frequencies of 2 kHz at a throughput of 2 MSPS.

9.2.2 Detailed Design Procedure

The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and a charge kickback filter. Careful design of the front-end circuit is critical to meet the linearity and noise performance of a high-precision ADC.

9.2.2.1 Low Distortion Charge Kickback Filter Design

Figure 41 shows the input circuit of a typical SAR ADC. During the acquisition phase, the SW switch closes and connects the sampling capacitor (C_SH) to the input driver circuit. This action introduces a transient on the input pins of the SAR ADC. An ideal amplifier with 0 Ω of output impedance and infinite current drive can settle this transient in zero time. For a real amplifier with non-zero output impedance and finite drive strength, this switched capacitor load can create stability issues.

Figure 41. Charge Kickback Filter

For ac signals, the filter bandwidth must be kept low to band limit the noise fed into the ADC input, thereby increasing the SNR of the system. Besides filtering the noise from the front-end drive circuitry, the RC filter also helps attenuate the sampling charge injection from the switched-capacitor input stage of the ADC. A filter capacitor, C_FLT, is connected across the ADC inputs. This capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold capacitors during the acquisition process. As a rule of thumb, the value of this capacitor is at least 20 times the specified value of the ADC sampling capacitance. For this device, the input sampling capacitance is equal to 15 pF. Thus, the value of C_FLT is greater than 300 pF. Select a COG- or NPO-type capacitor because these capacitor types have a high-Q, low-temperature coefficient, and stable electrical characteristics under varying voltages, frequency, and time.

Note that driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier marginally unstable. To avoid amplifier stability issues, series isolation resistors (R_FLT) are used at the output of the amplifiers. A higher value of R_FLT is helpful from the amplifier stability perspective, but adds distortion as a result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance, input signal frequency, and input signal amplitude. Therefore, the selection of R_FLT requires balancing the stability and distortion of the design.

The input amplifier bandwidth is typically much higher than the cutoff frequency of the antialiasing filter. Thus, a SPICE simulation is strongly recommended to be performed to confirm that the amplifier has more than 40° phase margin with the selected filter. Simulation is critical because even with high-bandwidth amplifiers, some amplifiers can require more bandwidth than others to drive similar filters.

9.2.3 Application Curve

Figure 42 shows the FFT plot for the ADS7049-Q1 with a 2-kHz input frequency used for the circuit in Figure 40.

SNR = 70.6 dB, THD = –86 dB, SINAD = 70.2 dB, number of samples = 32768

Figure 42. Test Results for the ADS7049-Q1 and OPA365-Q1 for a 2-kHz Input

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