• Menu
  • Product
  • Email
  • PDF
  • Order now
  • TPS53313 集成开关的高效 6A 降压稳压器

    • ZHCSFM8A December   2011  – October 2016 TPS53313

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • TPS53313 集成开关的高效 6A 降压稳压器
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Soft-Start Operation
      2. 7.3.2 Power Good
      3. 7.3.3 UVLO Function
      4. 7.3.4 Overcurrent (OC) Protection
      5. 7.3.5 Overvoltage and Undervoltage Protection
      6. 7.3.6 Overtemperature Protection
      7. 7.3.7 Output Discharge
      8. 7.3.8 Switching Frequency Setting and Synchronization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Mode
      2. 7.4.2 Light Load Operation
      3. 7.4.3 Forced Continuous Conduction Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Inductor Selection
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Output Voltage Setting Resistors Selection
        5. 8.2.2.5 Compensation Design
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息
  13. 重要声明
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

TPS53313 集成开关的高效 6A 降压稳压器

本资源的原文使用英文撰写。 为方便起见,TI 提供了译文;由于翻译过程中可能使用了自动化工具,TI 不保证译文的准确性。 为确认准确性,请务必访问 ti.com 参考最新的英文版本(控制文档)。

1 特性

  • 4.5V 至 16V 转换电压范围
  • 可调节输出电压范围:0.6V 至 0.7 × VIN
  • 6A 持续输出电流
  • 支持所有多层陶瓷电容 (MLCC) 输出电容
  • 可选跳跃模式或强制连续导通模式 (CCM)
  • 可选软启动时间(1ms、3ms 或 6ms)
  • 可选 4A-5A、6A 或 9A 峰值电流限值
  • 优化了轻负载与重负载条件下的效率
  • 电压模式控制
  • 可编程开关频率范围:250kHz 至 1.5MHz
  • 同步至外部时钟
  • 针对过零检测和过流保护提供 RDS(on) 感测
  • 软停止输出在禁用期间放电
  • 在断续模式下提供过流、过压和欠压保护
  • 过热保护
  • 开漏电源正常指示
  • 内部自举开关
  • 4mm × 4mm 24 引脚超薄四方扁平无引线 (VQFN) 封装

2 应用

  • 电压为 5V 的 负载点 (POL) 应用
  • 12V 降压电压轨

3 说明

TPS53313 提供集成两个 N 沟道金属氧化物半导体场效应晶体管 (MOSFET) 的 5V 或 12V 同步降压转换器。由于低RDS(接通)和TI私有的 SmoothPWM™跳跃模式操作可优化轻载条件下的效率,同时不影响输出电压纹波。

TPS53313 具有 可编程开关频率(250kHz 至 1.5MHz),可选择跳跃模式或强制 CCM 模式操作。该器件提供预偏置启动、软停止、集成自举开关、电源正常功能和 EN/输入电压锁定 (UVLO) 保护。该器件支持 4.5V 至 16V 范围内的输入电压,无需额外使用偏置电压。可调节输出电压范围:0.6V 至 0.7 × VIN。

TPS53313 采用 4mm × 4mm 24 VQFN 封装(绿色环保,符合 RoHS 标准并且无铅),额定运行温度范围为 -40°C 至 85°C。

器件信息(1)

器件型号 封装 封装尺寸(标称值)
TPS53313 VQFN (24) 4.00mm x 4.00mm
  1. 要了解所有可用封装,请见数据表末尾的可订购产品附录。

典型应用电路

TPS53313 v11254_lusas8.gif

4 修订历史记录

Changes from * Revision (December 2011) to A Revision

  • Added ESD 额定值表,特性 描述部分,器件功能模式,应用和实施部分,电源相关建议部分,布局部分,器件和文档支持部分以及机械、封装和可订购信息部分Go
  • Deleted 订购信息表;请参见数据表末尾的 POAGo

5 Pin Configuration and Functions

RGE Package
24-Pin VQFN
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NO. NAME
1 EN I Enable pin
2 PG O Power good output flag. Open drain output. Pull up to an external rail through a resistor.
3 VIN P Gate driver supply and power conversion voltage
4 VIN P Gate driver supply and power conversion voltage
5 VIN P Gate driver supply and power conversion voltage
6 VIN P Gate driver supply and power conversion voltage
7 PGND P Device power ground terminal
8 PGND P Device power ground terminal
9 PGND P Device power ground terminal
10 PGND P Device power ground terminal
11 PGND P Device power ground terminal
12 PGND P Device power ground terminal
13 SW O Output inductor connection to integrated power devices
14 SW O Output inductor connection to integrated power devices
15 SW O Output inductor connection to integrated power devices
16 SW O Output inductor connection to integrated power devices
17 VBST P Supply input for high-side MOSFET (bootstrap terminal). Connect capacitor from this pin to SW terminal.
18 BP7 P Bias for internal circuitry and driver
19 BP3 P Input bias supply for analog functions
20 AGND G Device analog ground terminal
21 RT/SYNC I/O Synchronized to external clock. Program the switching frequency by connecting with a resistor to GND.
22 MODE/SS I Mode configuration pin. Connect with a resistor to GND sets different modes and soft-start time, parallel a capacitor (or no capacitor) with the resistor changes the current limit threshold. Shorting MODE/SS pin to supply inhibits the device; shorting MODE/SS pin to AGND is equivalent to 10-kΩ resistor setting is not recommended (see Table 1 and Table 2 for resistor and capacitor settings).
23 COMP O Error amplifier compensation terminal. Type III compensation method is generally recommended for stability.
24 FB I Voltage feedback pin. Use for OVP, UVP, and power good determination
(1) B = Bidirectional, G = Ground, I = Input, O = Output, P = Supply

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN MAX UNIT
Input voltage VIN –0.3 20 V
VBST –0.3 27
VBST to SW –0.3 7
SW (bidirectional) DC –2 20
transient < 20 ns –3 20
EN VVIN ≥ 17 –0.3 17
VVIN < 17 –0.3 VVIN + 0.1
FB, MODE/SS –0.3 3.6
Output voltage COMP, RT/SYNC, BP3 –0.3 3.6 V
BP7 –0.3 7
PGD –0.3 17
Ground pin (GND) –0.3 0.3 V
Output current 6 A
Operating temperature, TJ –40 150 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
(3) Voltage values are with respect to the corresponding LL terminal.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Input voltage VIN (main supply) 4.5 16 V
VBST –0.1 22
VBST to SW –0.1 6.5
SW (bidirectional) dc –1 18
transient < 20 ns –2 18
EN –0.1 VVIN + 0.1
FB, MODE/SS –0.1 3.5
Output voltage COMP, RT/SYNC, BP3 –0.1 3.5 V
BP7 –0.1 6.5
PGD –0.1 14
Ground pin (GND) –0.1 0.1 V
TA Ambient temperature –40 85 °C
TJ Junction temperature –40 125 °C
(1) Voltage values are with respect to the corresponding LL terminal.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.

6.4 Thermal Information

THERMAL METRIC(1) TPS53313 UNIT
RGE (VQFN)
24 PINS
RθJA Junction-to-ambient thermal resistance 44.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 35 °C/W
RθJB Junction-to-board thermal resistance 19 °C/W
ψJT Junction-to-top characterization parameter 0.5 °C/W
ψJB Junction-to-board characterization parameter 18.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 8.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over operating free-air temperature range, VVIN = 12 V, PGND = GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY
VVIN VIN supply voltage Nominal input voltage range 4.5 16 V
VPOR VIN POR threshold Ramp up, EN = HIGH 4 4.23 4.4 V
VPOR(hys) VIN POR hysteresis 200 mV
ISTBY Standby current EN = LOW, VIN = 12 V 58 µA
RBOOT Bootstrap on-resistance 10 Ω
REFERENCE
VVREF Internal precision reference voltage 0.6 V
TOLVREF VREF tolerance –1% 1%
ERROR AMPLIFIER
UGBW(1) Unity gain bandwidth 14 MHz
AOL(1) Open loop gain 80 dB
IFBINT FB input leakage current Sourced from FB pin 50 nA
IEA(max) Output sinking and sourcing current 5 mA
SR(1) Slew rate 5 V/µs
ENABLE
RENPD(1) Enable pulldown resistor 800 kΩ
VENH EN logic high VVIN = 4.5 V 1.8 V
VENHYS EN hysteresis VVIN = 4.5 V 0.6 V
IEN EN pin current VEN = 0 V 1 µA
VEN = 3.3 V 3.3 5
VEN = 14 V 17.8 27.5
SOFT-START
tSS_1 Delay after EN asserts EN = High 0.65 ms
tSS_2 Soft start ramp_up time 0 V ≤ VSS ≤ 0.6 V, 39-kΩ or no resistor to MODE/SS pin 1 ms
0 V ≤ VSS ≤ 0.6 V, 20-kΩ or 160-kΩ resistor to MODE/SS pin 3
0 V ≤ VSS ≤ 0.6 V, 10-kΩ or 82-kΩ resistor to MODE/SS pin 6
tPGDENDLY PGD startup delay time VSS = 0.6 V to PGD (SSOK) going high,
tSS = 1 ms
0.2 ms
RAMP
Ramp amplitude 4.5 V ≤ VVIN ≤ 14.4 V VVIN/9 V
14.4 V ≤ VVIN ≤ 16 V 1.6
PWM
tMIN(off) Minimum OFF time fSW = 1 MHz 150 ns
tMIN(on) Minimum ON time No load 90 ns
DMAX Maximum duty cycle fSW = 1 MHz 80%
SWITCHING FREQUENCY
fSW Switching frequency tolerance fSW = 1 MHz, RT = 45.3 kΩ –10% 10%
SOFT DISCHARGE
RSFTDIS Soft-discharge transistor resistance EN = Low, VIN = 4.5 V, VOUT = 0.6 V 120 Ω
OVERCURRENT AND ZERO CROSSING
IOCPL Overcurrent limit on high-side FET (peak) When IOUT exceeds this threshold for 4 consecutive cycles, 2.2-nF capacitor to MODE/SS pin 4.5 A
When IOUT exceeds this threshold for 4 consecutive cycles, no capacitor to MODE/SS pin 6 A
When IOUT exceeds this threshold for 4 consecutive cycles, 10-nF capacitor to MODE/SS pin 9
IOCPH One time overcurrent shut-off on the low-side FET (peak) Immediately shut down when sensed current reach this value, 2.2-nF capacitor to MODE/SS pin 4.5 A
Immediately shut down when sensed current reach this value, no capacitor to MODE/SS pin 6 A
Immediately shut down when sensed current reach this value, 10-nF capacitor to MODE/SS pin 9
VZXOFF Zero crossing comparator internal offset SW – PGND, SKIP mode –3 mV
POWER GOOD
VPGDL Power good low threshold Measured at the FB pin w/r/t VREF 80% 83% 86%
VPGDH Power good high threshold Measured at the FB pin w/r/t VREF 114% 117% 120%
VPG(hys) Power good hysteresis 2
VIN(min_pg) Minimum Vin voltage for valid PG at startup. Measured at VIN with 1-mA (or 2-mA) sink current on PG pin at startup 1 V
VPG(pd) Power good pull-down voltage Pull down voltage with 4-mA sink current 0.2 0.4 V
IPG(leak) Power good leakage current Hi-Z leakage current, apply 3.3-V in off state 12 16.2 µA
OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTION
TOVPDLY Overvoltage protection delay time Time from FB out of +17% of VREF to OVP fault 2 µs
TUVPDLY Undervoltage protection delay time Time from FB out of –17% of VREF to UVP fault 10 µs
THERMAL SHUTDOWN
THSD(1) Thermal shutdown Shutdown controller, attempt soft-stop 130 140 150 °C
THSDHYST(1) Thermal shutdown hysteresis Controller restarts after temperature drops 40 °C
(1) Ensured by design. Not production tested.

6.6 Typical Characteristics

TPS53313 g001_dutyratio.png Figure 1. Ensured Minimum Duty Ratio
TPS53313 g003_efficiency_lusas8.png Figure 3. Efficiency, VIN = 5 V
TPS53313 g005_fsw_v_rrt_lusas8.png Figure 5. Switching Frequency
vs Timing Resistance (RT)
TPS53313 g007_pgood_lusas8.png Figure 7. PGOOD Upper Threshold
vs Junction Temperature
TPS53313 g009_pghystlo_lusas8.png Figure 9. PGOOD Lower Hysteresis
vs Junction Temperature
TPS53313 g011_fsw_lusas8.png Figure 11. Switching Frequency vs Junction Temperature
TPS53313 g002_efficiency_lusas8.png Figure 2. Efficiency, VIN = 12 V
TPS53313 g004_efficiency_lusas8,png.png Figure 4. Efficiency, VIN = 14 V
TPS53313 g006_pgood_lusas8.png Figure 6. PGOOD Lower Threshold
vs Junction Temperature
TPS53313 g008_modess_lusas8.png Figure 8. MODE/SS Leakage Current
vs Junction Temperature
TPS53313 g010_pghysthi_lusas8.png Figure 10. PGOOD Upper Hysteresis
vs Junction Temperature

 

Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale