ISO5451-Q1 具有有源安全特性的高 CMTI 2.5A/5A 隔离式 IGBT、MOSFET 栅极 驱动器

Table 2. Design Parameters

10.2.2.1 Recommended ISO5451-Q1 Application Circuit

The ISO5451-Q1 has both, inverting and non-inverting gate control inputs, an active low reset input, and an open drain fault output suitable for wired-OR applications. The recommended application circuit in Figure 43 illustrates a typical gate driver implementation with Unipolar Output Supply and Figure 44 illustrates a typical gate driver implementation with Bipolar Output Supply using the ISO5451-Q1.

A 0.1-μF bypass capacitor, recommended at input supply pin V_CC1 and 1-μF bypass capacitor, recommended at output supply pin V_CC2, provide the large transient currents necessary during a switching transition to ensure reliable operation. The 220 pF blanking capacitor disables DESAT detection during the off-to-on transition of the power device. The DESAT diode (D_DST) and its 1-kΩ series resistor are external protection components. The R_G gate resistor limits the gate charge current and indirectly controls the IGBT collector voltage rise and fall times. The open-drain FLT output and RDY output has a passive 10-kΩ pull-up resistor. In this application, the IGBT gate driver is disabled when a fault is detected and will not resume switching until the micro-controller applies a reset signal.

Figure 43. Unipolar Output Supply

Figure 44. Bipolar Output Supply

10.2.2.2 FLT and RDY Pin Circuitry

There is 50k pull-up resistor internally on FLT and RDY pins. The FLT and RDY pin is an open-drain output. A 10-kΩ pull-up resistor can be used to make it faster rise and to provide logic high when FLT and RDY is inactive, as shown in Figure 45.

Fast common mode transients can inject noise and glitches on FLT and RDY pins due to parasitic coupling. This is dependent on board layout. If required, additional capacitance (100 pF to 300 pF) can be included on the FLT and RDY pins.

Figure 45. FLT and RDY Pin Circuitry for High CMTI

10.2.2.3 Driving the Control Inputs

The amount of common-mode transient immunity (CMTI) can be curtailed by the capacitive coupling from the high-voltage output circuit to the low-voltage input side of the ISO5451-Q1. For maximum CMTI performance, the digital control inputs, IN+ and IN-, must be actively driven by standard CMOS, push-pull drive circuits. This type of low-impedance signal source provides active drive signals that prevent unwanted switching of the ISO5451-Q1 output under extreme common-mode transient conditions. Passive drive circuits, such as open-drain configurations using pull-up resistors, must be avoided. There is a 20 ns glitch filter which can filter a glitch up to 20 ns on IN+ or IN-.

10.2.2.4 Local Shutdown and Reset

In applications with local shutdown and reset, the FLT output of each gate driver is polled separately, and the individual reset lines are asserted low independently to reset the motor controller after a fault condition.

Figure 46. Local Shutdown and Reset for Noninverting (left) and Inverting Input Configuration (right)

10.2.2.5 Global-Shutdown and Reset

When configured for inverting operation, the ISO5451-Q1 can be configured to shutdown automatically in the event of a fault condition by tying the FLT output to IN+. For high reliability drives, the open drain FLT outputs of multiple ISO5451-Q1 devices can be wired together forming a single, common fault bus for interfacing directly to the micro-controller. When any of the six gate drivers of a three-phase inverter detects a fault, the active low FLT output disables all six gate drivers simultaneously.

Figure 47. Global Shutdown with Inverting Input Configuration

10.2.2.6 Auto-Reset

In this case, the gate control signal at IN+ is also applied to the RST input to reset the fault latch every switching cycle. Incorrect RST makes output go low. A fault condition, however, the gate driver remains in the latched fault state until the gate control signal changes to the 'gate low' state and resets the fault latch.

If the gate control signal is a continuous PWM signal, the fault latch will always be reset before IN+ goes high again. This configuration protects the IGBT on a cycle by cycle basis and automatically resets before the next 'on' cycle.

Figure 48. Auto Reset for Non-inverting and Inverting Input Configuration

10.2.2.7 DESAT Pin Protection

Switching inductive loads causes large instantaneous forward voltage transients across the freewheeling diodes of IGBTs. These transients result in large negative voltage spikes on the DESAT pin which draw substantial current out of the device. To limit this current below damaging levels, a 100-Ω to 1-kΩ resistor is connected in series with the DESAT diode.

Further protection is possible through an optional Schottky diode, whose low forward voltage assures clamping of the DESAT input to GND2 potential at low voltage levels.

Figure 49. DESAT Pin Protection with Series Resistor and Schottky Diode

10.2.2.8 DESAT Diode and DESAT Threshold

The DESAT diode’s function is to conduct forward current, allowing sensing of the IGBT’s saturated collector-to-emitter voltage, V_(CESAT), (when the IGBT is "on") and to block high voltages (when the IGBT is "off"). During the short transition time when the IGBT is switching, there is commonly a high dV_CE/dt voltage ramp rate across the IGBT. This results in a charging current I_(CHARGE) = C_(D-DESAT) x d_VCE/dt, charging the blanking capacitor. C_(D-DESAT) is the diode capacitance at DESAT.

To minimize this current and avoid false DESAT triggering, fast switching diodes with low capacitance are recommended. As the diode capacitance builds a voltage divider with the blanking capacitor, large collector voltage transients appear at DESAT attenuated by the ratio of 1+ C_(BLANK) / C_(D-DESAT).

Because the sum of the DESAT diode forward-voltage and the IGBT collector-emitter voltage make up the voltage at the DESAT-pin, V_F + V_CE = V_(DESAT), the V_CE level, which triggers a fault condition, can be modified by adding multiple DESAT diodes in series: V_CE-FAULT(TH) = 9 V – n x VF (where n is the number of DESAT diodes).

When using two diodes instead of one, diodes with half the required maximum reverse-voltage rating may be chosen.

10.2.2.9 Determining the Maximum Available, Dynamic Output Power, P_OD-max

The ISO5451-Q1 maximum allowed total power consumption of P_D = 251 mW consists of the total input power, P_ID, the total output power, P_OD, and the output power under load, P_OL:

With:

and:

then:

In comparison to P_OL, the actual dynamic output power under worst case condition, P_OL-WC, depends on a variety of parameters:

Equation 5.

where

• f_INP = signal frequency at the control input IN+
• Q_G = power device gate charge
• V_CC2 = positive output supply with respect to GND2
• V_EE2 = negative output supply with respect to GND2
• r_on-max = worst case output resistance in the on-state: 4Ω
• r_off-max = worst case output resistance in the off-state: 2.5Ω
• R_G = gate resistor

Once R_G is determined, Equation 5 is to be used to verify whether P_OL-WC < P_OL. Figure 50 shows a simplified output stage model for calculating P_OL-WC.

Figure 50. Simplified Output Model for Calculating P_OL-WC

10.2.2.10 Example

This examples considers an IGBT drive with the following parameters:

Apply the value of the gate resistor R_G = 10 Ω.

Then, calculating the worst-case output power consumption as a function of R_G, using Equation 5 r_on-max = worst case output resistance in the on-state: 4Ω, r_off-max = worst case output resistance in the off-state: 2.5Ω, R_G = gate resistor yields

Equation 7.

Because P_OL-WC = 72.61 mW is below the calculated maximum of P_OL = 88.25 mW, the resistor value of R_G = 10 Ω is suitable for this application.

10.2.2.11 Higher Output Current Using an External Current Buffer

To increase the IGBT gate drive current, a non-inverting current buffer (such as the npn/pnp buffer shown in Figure 51) may be used. Inverting types are not compatible with the desaturation fault protection circuitry and must be avoided. The MJD44H11/MJD45H11 pair is appropriate for currents up to 8 A, the D44VH10/ D45VH10 pair for up to 15 A maximum.

Figure 51. Current Buffer for Increased Drive Current