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  • ISO5851-Q1 具有有源安全特性的高 CMTI 2.5A/5A 隔离式 IGBT、MOSFET 栅极 驱动器

    • ZHCSFJ4 September   2016 ISO5851-Q1

      PRODUCTION DATA.  

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  • ISO5851-Q1 具有有源安全特性的高 CMTI 2.5A/5A 隔离式 IGBT、MOSFET 栅极 驱动器
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史
  5. 5 说明 (续)
  6. 6 Pin Configuration and Function
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Rating
    6. 7.6  Insulation Characteristics
    7. 7.7  Safety Limiting Values
    8. 7.8  Safety-Related Certifications
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Safety and Insulation Characteristics Curves
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Supply and active Miller clamp
      2. 9.3.2 Active Output Pull-down
      3. 9.3.3 Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication Output
      4. 9.3.4 Fault (FLT) and Reset (RST)
      5. 9.3.5 Short Circuit Clamp
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Recommended ISO5851-Q1 Application Circuit
        2. 10.2.2.2  FLT and RDY Pin Circuitry
        3. 10.2.2.3  Driving the Control Inputs
        4. 10.2.2.4  Local Shutdown and Reset
        5. 10.2.2.5  Global-Shutdown and Reset
        6. 10.2.2.6  Auto-Reset
        7. 10.2.2.7  DESAT Pin Protection
        8. 10.2.2.8  DESAT Diode and DESAT Threshold
        9. 10.2.2.9  Determining the Maximum Available, Dynamic Output Power, POD-max
        10. 10.2.2.10 Example
        11. 10.2.2.11 Higher Output Current Using an External Current Buffer
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 PCB Material
    3. 12.3 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档 
    2. 13.2 接收文档更新通知
    3. 13.3 社区资源
    4. 13.4 商标
    5. 13.5 静电放电警告
    6. 13.6 Glossary
  14. 14机械、封装和可订购信息
  15. 重要声明
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DATA SHEET

ISO5851-Q1 具有有源安全特性的高 CMTI 2.5A/5A 隔离式 IGBT、MOSFET 栅极 驱动器

本资源的原文使用英文撰写。 为方便起见,TI 提供了译文;由于翻译过程中可能使用了自动化工具,TI 不保证译文的准确性。 为确认准确性,请务必访问 ti.com 参考最新的英文版本(控制文档)。

1 特性

  • 适用于汽车电子 标准
  • 具有符合 AEC-Q100 标准的下列结果:
    • 器件温度 1 级:-40°C 至 125°C 的环境运行温度范围
    • 器件人体模型 (HBM) 分类等级 3A
    • 器件充电器件模型 (CDM) 分类等级 C6
  • 在 VCM = 1500V 时,共模瞬态抗扰度 (CMTI) 的最小值为 100kV/μs
  • 2.5A 峰值拉电流和 5A 峰值灌电流
  • 短暂传播延迟:76ns(典型值),
    110ns(最大值)
  • 2A 有源米勒钳位
  • 输出短路钳位
  • 在检测到去饱和故障时通过 FLT 发出故障报警,并通过 RST 复位
  • 具有就绪 (RDY) 引脚指示的输入和输出欠压锁定 (UVLO)
  • 有源输出下拉特性,在低电源或输入悬空的情况下默认输出低电平
  • 3V 至 5.5V 输入电源电压
  • 15V 至 30V 输出驱动器电源电压
  • 互补金属氧化物半导体 (CMOS) 兼容输入
  • 抑制短于 20ns 的输入脉冲和瞬态噪声
  • 可承受的浪涌隔离电压达 12800VPK”
  • 安全及管理认证:
    • 符合 DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 标准的 8000 VPK VIOTM 和 2121 VPK VIORM 增强型隔离
    • 符合 UL 1577 标准且长达 1 分钟的 5700 VRMS 隔离
    • CSA 组件验收通知 5A、IEC 60950-1 和 IEC 60601-1 终端设备标准
    • 符合 EN 61010-1 和 EN 60950-1 标准的 TUV 认证
    • GB4943.1-2011 CQC 认证
    • 已通过 UL、VDE、CQC、TUV 认证并规划进行 CSA 认证

2 应用

  • 隔离式绝缘栅双极型晶体管 (IGBT) 和金属氧化物半导体场效应晶体管 (MOSFET) 驱动器:
    • 混合动力汽车 (HEV) 和电动车 (EV) 电源模块
    • 工业电机控制驱动
    • 工业电源
    • 太阳能逆变器
    • 感应加热

3 说明

ISO5851-Q1 是一款用于 IGBT 和 MOSFET 的 5.7 kVRMS 增强型隔离栅极驱动器,具有 2.5A 的拉电流能力和 5A 的灌电流能力。输入端由 3V 至 5.5V 的单电源供电运行。输出端允许的电源范围为 15V 至 30V。两个互补 CMOS 输入控制栅极驱动器的输出状态。76ns 的短暂传播时间保证了对于输出级的精确控制。

内置的去饱和 (DESAT) 故障检测功能可识别 IGBT 何时处于过载状态。当检测到 DESAT 时,栅极驱动器输出会被拉低为 VEE2 电势,从而将 IGBT 立即关断。

当发生去饱和故障时,器件会通过隔离隔栅发送故障信号,以将输入端的 FLT 输出拉为低电平并阻断隔离器的输入。FLT 的输出状态将被锁存,可通过 RST 输入上的低电平有效脉冲复位。

器件信息(1)

器件型号 封装 封装尺寸(标称值)
ISO5851-Q1 SOIC (16) 10.30mm x 7.50mm
  1. 如需了解所有可用封装,请见数据表末尾的可订购产品附录。

功能方框图

ISO5851-Q1 fbd_SLLSEQ1.gif

4 修订历史

日期 修订版本 注释
2015 年 9 月 * 最初发布版本

5 说明 (续)

如果在由双极输出电源供电的正常运行期间关断 IGBT,输出电压会被硬钳位为 VEE2。如果输出电源为单极,那么可采用有源米勒钳位,这种钳位会在一条低阻抗路径上灌入米勒电流,从而防止 IGBT 在高电压瞬态条件下发生动态导通。

当发生去饱和故障时,器件会通过隔离隔栅发送故障信号,以将输入端的 FLT 输出拉为低电平并阻断隔离器的输入。FLT 的输出状态将被锁存,可通过 RST 输入上的低电平有效脉冲复位。

如果在由双极输出电源供电的正常运行期间关断 IGBT,输出电压会被硬钳位为 VEE2。如果输出电源为单极,那么可采用有源米勒钳位,这种钳位会在一条低阻抗路径上灌入米勒电流,从而防止 IGBT 在高电压瞬态条件下发生动态导通。

栅极驱动器是否准备就绪待运行由两个欠压锁定电路控制,这两个电路会监视输入端和输出端的电源。如果任意一端电源不足,RDY 输出会变为低电平;否则,该输出为高电平。

ISO5851-Q1 采用 16 引脚小外形尺寸集成电路 (SOIC) 封装。此器件的额定工作环境温度范围为 -40°C 至 125°C。

6 Pin Configuration and Function

DW Package
16-Pin SOIC
Top View
ISO5851-Q1 po_sllsen5.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
VEE2 1, 8 - Output negative supply. Connect to GND2 for Unipolar supply application.
DESAT 2 I Desaturation voltage input
GND2 3 - Gate drive common. Connect to IGBT emitter.
NC 4 - Not connected
VCC2 5 - Most positive output supply potential.
OUT 6 O Gate drive voltage output
CLAMP 7 O Miller clamp output
GND1 9, 16 - Input ground
IN+ 10 I Non-inverting gate drive voltage control input
IN- 11 I Inverting gate drive voltage control input
RDY 12 O Power-good output, active high when both supplies are good.
FLT 13 O Fault output, low-active during DESAT condition
RST 14 I Reset input, apply a low pulse to reset fault latch.
VCC1 15 - Positive input supply (3 V to 5.5 V)

7 Specifications

7.1 Absolute Maximum Ratings(1)

Over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC1 Supply voltage input side GND1 - 0.3 6 V
VCC2 Positive supply voltage output side (VCC2 – GND2) –0.3 35 V
VEE2 Negative supply voltage output side (VEE2 – GND2) –17.5 0.3 V
V(SUP2) Total supply output voltage (VCC2 - VEE2) –0.3 35 V
VOUT Gate driver output voltage VEE2 - 0.3 VCC2 + 0.3 V
I(OUTH) Gate driver high output current Gate driver high output current
(max pulse width = 10 μs, max duty cycle = 0.2%)
2.7 A
I(OUTL) Gate driver low output current 5.5 A
V(LIP) Voltage at IN+, IN-,FLT, RDY, RST GND1 - 0.3 VCC1 + 0.3 V
I(LOP) Output current of FLT, RDY 10 mA
V(DESAT) Voltage at DESAT GND2 - 0.3 VCC2 + 0.3 V
V(CLAMP) Clamp voltage VEE2 - 0.3 VCC2 + 0.3 V
TJ Junction temperature –40 150 °C
TSTG Storage temperature –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±4000 V
Charged-device model (CDM), per AEC Q100-011 ±1500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC1 Supply voltage input side 3 5.5 V
VCC2 Positive supply voltage output side (VCC2 – GND2) 15 30 V
VEE2 Negative supply voltage output side (VEE2 – GND2) –15 0 V
V(SUP2) Total supply voltage output side (VCC2 – VEE2) 15 30 V
VIH High-level input voltage (IN+, IN-, RST) 0.7 x VCC1 VCC1 V
VIL Low-level input voltage (IN+, IN-, RST) 0 0.3 x VCC1 V
tUI Pulse width at IN+, IN- for full output (CLOAD = 1nF) 40 ns
tRST Pulse width at RST for resetting fault latch 800 ns
TA Ambient temperature -40 25 125 °C

7.4 Thermal Information

THERMAL METRIC(1) DW (SOIC) UNIT
16 PINS
θJA Junction-to-ambient thermal resistance 99.6 °C/W
θJCtop Junction-to-case (top) thermal resistance 48.5
θJB Junction-to-board thermal resistance 56.5
ψJT Junction-to-top characterization parameter 29.2
ψJB Junction-to-board characterization parameter 56.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Power Rating

VALUE UNIT
PD Maximum power dissipation(1) 1255 mW
PID Maximum input power dissipation 175
POD Maximum output power dissipation 1080
(1) Full chip power dissipation is de-rated 10.04 mW/°C beyond 25°C ambient temperature. At 125°C ambient temperature, a maximum of 251 mW total power dissipation is allowed. Power dissipation can be optimized depending on ambient temperature and board design, while ensuring that Junction temperature does not exceed 150°C.

7.6 Insulation Characteristics

PARAMETER TEST CONDITIONS SPECIFICATION UNIT
CLR External clearance(1) Shortest terminal-to-terminal distance through air 8 mm
CPG External creepage(1) Shortest terminal-to-terminal distance across the package surface 8 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) 21 μm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 >600 V
Material group According to IEC 60664-1 I
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 600 VRMS I-IV
Rated mains voltage ≤ 1000 VRMS I-III
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 2121 VPK
VIOWM Maximum isolation working voltage AC voltage. Time dependent dielectric breakdown (TDDB) Test, see Figure 1 1500 VRMS
DC voltage 2121 VDC
VIOTM Maximum Transient isolation voltage VTEST = VIOTM, t = 60 sec (qualification), t = 1 sec (100% production) 8000 VPK
VIOSM Maximum surge isolation voltage(3) Test method per IEC 60065, 1.2/50 μs waveform,
VTEST = 1.6 x VIOSM = 12800 VPK (qualification)
8000
qpd Apparent charge(4) Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM = 2545 VPK,
tm = 10 s
≤5 pC
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM = 3394 VPK,
tm = 10 s
≤5
Method b1: At routine test (100% production) and preconditioning (type test)
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.875× VIORM = 3977 VPK,
tm = 10 s
≤5
RIO Isolation resistance, input to output(5) VIO = 500 V at TS > 109 Ω
VIO = 500 V, TA = 25°C >1012 Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C >1011 Ω
CIO Barrier capacitance, input to output(5) VIO = 0.4 x sin (2πft), f = 1 MHz 1 pF
Pollution degree 2
UL 1577
VISO Withstanding Isolation voltage VTEST = VISO, t = 60 sec (qualification),
VTEST = 1.2 × VISO = 6840 VRMS, t = 1 sec (100% production)
5700 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device.

7.7 Safety Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IS Safety input, output or supply current θJA = 99.6°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C 349 mA
θJA = 99.6°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C 228
θJA = 99.6°C/W, VI = 15 V, TJ = 150°C, TA = 25°C 84
θJA = 99.6°C/W, VI = 30 V, TJ = 150°C, TA = 25°C 42
PS Safety input, output, or total power θJA = 99.6°C/W, TJ = 150°C, TA = 25°C 1255(1)
TS Maximum ambient safety temperature 150 °C
(1) Input, output, or the sum of input and output power should not exceed this value

7.8 Safety-Related Certifications

VDE CSA UL CQC TUV
Certified according to
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 60950-1 (VDE 0805 Teil 1):2011-01
Plan to certify under CSA Component Acceptance Notice 5A, IEC 60950-1, and IEC 60601-1 Certified according to UL 1577 Component Recognition Program Certified according to GB 4943.1-2011 Certified according to
EN 61010-1:2010 (3rd Ed) and
EN 60950-1:2006/A11:2009/A1:2010/
A12:2011/A2:2013
Reinforced Insulation Maximum Transient isolation voltage, 8000 VPK;
Maximum surge isolation voltage, 8000 VPK,
Maximum repetitive peak isolation voltage, 2121 VPK
Isolation Rating of 5700 VRMS;
Reinforced insulation per CSA 60950-1- 07+A1+A2 and IEC 60950-1 (2nd Ed.), 800 VRMS max working voltage (pollution degree 2, material group I) ;

2 MOPP (Means of Patient Protection) per CSA 60601-1:14 and IEC 60601-1 Ed. 3.1, 250 VRMS (354 VPK) max working voltage
Single Protection, 5700 VRMS (1) Reinforced Insulation, Altitude ≤ 5000m, Tropical climate, 400 VRMS maximum working voltage 5700 VRMS Reinforced insulation per
EN 61010-1:2010 (3rd Ed) up to working voltage of 600 VRMS

5700 VRMS Reinforced insulation per
EN 60950-1:2006/A11:2009/A1:2010/
A12:2011/A2:2013 up to working voltage of 800 VRMS
Certification completed
Certificate number: 40040142
Certification planned Certification completed
File number: E181974
Certification completed
Certificate number: CQC16001141761
Certification completed
Client ID number: 77311
(1) Production tested ≥6840 VRMS for 1 second in accordance with UL 1577.

The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed in the High-K Test Board for Leaded Surface-Mount Packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

7.9 Electrical Characteristics

Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOLTAGE SUPPLY
VIT+(UVLO1) Positive-going UVLO1 threshold voltage input side (VCC1 – GND1) 2.25 V
VIT-(UVLO1) Negative-going UVLO1 threshold voltage input side (VCC1 – GND1) 1.7 V
VHYS(UVLO1) UVLO1 Hysteresis voltage (VIT+ – VIT–) input side 0.24 V
VIT+(UVLO2) Positive-going UVLO2 threshold voltage output side (VCC2 – GND2) 12 13 V
VIT-(UVLO2) Negative-going UVLO2 threshold voltage output side (VCC2 – GND2) 9.5 11 V
VHYS(UVLO2) UVLO2 Hysteresis voltage (VIT+ – VIT–) output side 1 V
IQ1 Input supply quiescent current 2.8 4.5 mA
IQ2 Output supply quiescent current 3.6 6 mA
LOGIC I/O
VIT+(IN,RST) Positive-going input threshold voltage (IN+, IN-, RST) 0.7 x VCC1 V
VIT-(IN,RST) Negative-going input threshold voltage (IN+, IN-, RST) 0.3 x VCC1 V
VHYS(IN,RST) Input hysteresis voltage (IN+, IN-, RST) 0.15 x VCC1 V
IIH High-level input leakage at (IN+) IN+ = VCC1 100 µA
IIL Low-level input leakage at (IN-, RST) IN- = GND1, RST = GND1 -100 µA
IPU Pull-up current of FLT, RDY V(RDY) = GND1, V(FLT) = GND1 100 µA
VOL Low-level output voltage at FLT, RDY I(FLT) = 5 mA 0.2 V
GATE DRIVER STAGE
V(OUTPD) Active output pull-down voltage IOUT = 200 mA, VCC2 = open 2 V
V(OUTH) High-level output voltage IOUT = –20 mA VCC2 - 0.5 VCC2 - 0.24 V
V(OUTL) Low-level output voltage IOUT = 20 mA VEE2 + 13 VEE2 + 50 mV
I(OUTH) High-level output peak current IN+ = high, IN- = low,
VOUT = VCC2 - 15 V
1.5 2.5 A
I(OUTL) Low-level output peak current IN+ = low, IN- = high,
VOUT = VEE2 + 15 V
3.4 5 A
ACTIVE MILLER CLAMP
V(CLP) Low-level clamp voltage I(CLP) = 20 mA VEE2 + 0.015 VEE2 + 0.08 V
I(CLP) Low-level clamp current V(CLAMP) = VEE2 + 2.5 V 1.6 2.5 A
V(CLTH) Clamp threshold voltage 1.6 2.1 2.5 V
SHORT CIRCUIT CLAMPING
V(CLP_OUT) Clamping voltage
(VOUT - VCC2)
IN+ = high, IN- = low, tCLP = 10 µs, I(OUTH) = 500 mA 0.8 1.3 V
V(CLP_CLAMP) Clamping voltage
(VCLP - VCC2)
IN+ = high, IN- = low, tCLP = 10 µs, I(CLP) = 500 mA 1.3 V
V(CLP_CLAMP) Clamping voltage at CLAMP IN+ = High, IN- = Low, I(CLP) = 20 mA 0.7 1.1 V
DESAT PROTECTION
I(CHG) Blanking capacitor charge current V(DESAT) - GND2 = 2 V 0.42 0.5 0.58 mA
I(DCHG) Blanking capacitor discharge current V(DESAT) - GND2 = 6 V 9 14 mA
V(DSTH) DESAT threshold voltage with respect to GND2 8.3 9 9.5 V
V(DSL) DESAT voltage with respect to GND2, when OUT is driven low 0.4 1 V

7.10 Switching Characteristics

Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tr Output signal rise time CLOAD = 1 nF, see Figure 38, Figure 39, and Figure 40 12 20 35 ns
tf Output signal fall time 12 20 37 ns
tPLH, tPHL Propagation Delay 76 110 ns
tsk-p Pulse Skew |tPHL – tPLH| 20 ns
tsk-pp Part-to-part skew 30(1) ns
tGF Glitch filter on IN+, IN-, RST 20 30 40 ns
tDESAT (10%) DESAT sense to 10% OUT delay 300 415 500 ns
tDESAT (GF) DESAT glitch filter delay 330 ns
tDESAT (FLT) DESAT sense to FLT-low delay see Figure 40 2000 2420 ns
tLEB Leading edge blanking time see Figure 38 and Figure 39 330 400 500 ns
tGF(RSTFLT) Glitch filter on RST for resetting FLT 300 800 ns
CI Input capacitance(2) VI = VCC1 /2 + 0.4 x sin (2πft), f = 1 MHz, VCC1 = 5 V 2 pF
CMTI Common-mode transient immunity VCM = 1500 V, see Figure 41 100 120 kV/μs
(1) Measured at same supply voltage and temperature condition
(2) Measured from input pin to ground.

7.11 Safety and Insulation Characteristics Curves

ISO5851-Q1 tddb_curve_reinforced_dw.gif
TA upto 150°C Stress-voltage frequency = 60 Hz
Figure 1. Reinforced High-Voltage Capacitor Life Time Projection
ISO5851-Q1 D100_SLLSEN5.gif Figure 2. Thermal Derating Curve for Safety Limiting Current per VDE
ISO5851-Q1 D101_SLLSEN5.gif Figure 3. Thermal Derating Curve for Safety Limiting Power per VDE

7.12 Typical Characteristics

ISO5851-Q1 D001_SLLSEO1.gif
VCC2 = 30 V
Figure 4. Output High Drive Current vs Temperature
ISO5851-Q1 D003_SLLSEO1.gif
Figure 6. Output High Drive Current vs Output Voltage
ISO5851-Q1 D005_SLLSEO1.gif
Unipolar: VCC2 - VEE2 = VCC2 - GND2
Figure 8. DESAT Threshold Voltage vs Temperature
ISO5851-Q1 D002_SLLSEO1.gif
VCC2 = 30 V
Figure 5. Output Low Drive Current vs Temperature
ISO5851-Q1 D004_SLLSEO1.gif
Figure 7. Output Low Drive Current vs Output Voltage
ISO5851-Q1 G001_SLLSEN5.gif
CL = 1 nF RG = 0 Ω
VCC2 - VEE2 = VCC2 - GND2 = 20 V
Figure 9. OUT Transient Waveform
ISO5851-Q1 G003_SLLSEN5.gif
CL = 10 nF RG = 0 Ω
VCC2 - VEE2 = VCC2 - GND2 = 20 V
Figure 11. OUT Transient Waveform
ISO5851-Q1 G005_SLLSEN5.gif
CL = 100 nF RG = 0 Ω
VCC2 - VEE2 = VCC2 - GND2 = 20 V
Figure 13. OUT Transient Waveform
ISO5851-Q1 G007_SLLSEN5.gif
CL = 100 nF RG = 10 Ω
VCC2 - VEE2 = VCC2 - GND2 = 20 V
Figure 15. OUT Transient Waveform DESAT and FLT
ISO5851-Q1 D007_SLLSEO1.gif
IN+ = Low IN- = Low
Figure 17. ICC1 Supply Current vs Temperature
ISO5851-Q1 D009_SLLSEO1.gif
Figure 19. ICC1 Supply Current vs. Input Frequency
ISO5851-Q1 D025_SLLSEO1.gif
RG = 10 Ω, 20kHz
Figure 21. ICC2 Supply Current vs Load Capacitance
ISO5851-Q1 D013_SLLSEO1.gif
CL = 1nF RG = 0 Ω VCC2 = 15 V
Figure 23. VCC2 Propagation Delay vs Temperature
ISO5851-Q1 D022_SLLSEO1.gif
RG = 0 Ω VCC1 = 5 V
Figure 25. tr Rise Time vs Load Capacitance
ISO5851-Q1 D023_SLLSEO1.gif
RG = 10 Ω VCC1 = 5 V
Figure 27. tr Rise Time vs Load Capacitance
ISO5851-Q1 D014_SLLSEO1.gif
Figure 29. Leading Edge Blanking Time With Temperature
ISO5851-Q1 D016_SLLSEO1.gif
CL = 1 nF
Figure 31. DESAT Sense to FLT Low Delay vs Temperature
ISO5851-Q1 D018_SLLSEO1.gif
Figure 33. Miller Clamp Current vs Temperature
ISO5851-Q1 D021_SLLSEQ3.gif
Figure 35. VCLP_CLAMP - Short Circuit Clamp Voltage on Clamp Across Temperature
ISO5851-Q1 D011_SLLSEO1.gif
VCC2 = 15 V DESAT = 6 V
Figure 37. Blanking Capacitor Charging Current vs Temperature
ISO5851-Q1 G002_SLLSEN5.gif
CL = 1 nF RG = 10 Ω
VCC2 - VEE2 = VCC2 - GND2 = 20 V
Figure 10. OUT Transient Waveform
ISO5851-Q1 G004_SLLSEN5.gif
CL = 10 nF RG = 10 Ω
VCC2 - VEE2 = VCC2 - GND2 = 20 V
Figure 12. OUT Transient Waveform
ISO5851-Q1 G006_SLLSEN5.gif
CL = 100 nF RG = 10 Ω
VCC2 - VEE2 = VCC2 - GND2 = 20 V
Figure 14. OUT Transient Waveform
ISO5851-Q1 D006_SLLSEO1.gif
IN+ = High IN- = Low
Figure 16. ICC1 Supply Current vs Temperature
ISO5851-Q1 D008_SLLSEO1.gif
Input Frequency = 1 kHz
Figure 18. ICC2 Supply Current vs Temperature
ISO5851-Q1 D010_SLLSEO1.gif
no CL
Figure 20. ICC2 Supply Current vs Input Frequency
ISO5851-Q1 D012_SLLSEO1.gif
CL = 1nF RG = 0 Ω VCC1 = 5 V
Figure 22. VCC1 Propagation Delay vs Temperature
ISO5851-Q1 D024_SLLSEO1.gif
RG = 10 Ω VCC1 = 5 V
Figure 24. Propagation Delay vs Load Capacitance
ISO5851-Q1 D026_SLLSEO1.gif
RG = 0 Ω VCC1 = 5 V
Figure 26. tf Fall Time v. Load Capacitance
ISO5851-Q1 D027_SLLSEO1.gif
RG = 10 Ω VCC1 = 5 V
Figure 28. tf Fall Time vs Load Capacitance
ISO5851-Q1 D015_SLLSEO1.gif
CL = 10 nF
Figure 30. DESAT Sense to VOUT 10% Delay vs Temperature
ISO5851-Q1 D017_SLLSEO1.gif
Figure 32. Reset to Fault Delay Across Temperature
ISO5851-Q1 D019_SLLSEO1.gif
Figure 34. Active Pull Down Voltage vs Temperature
ISO5851-Q1 D020_SLLSEQ3.gif
Figure 36. VCLP_CLAMP - Short Circuit Clamp Voltage on OUT Across Temperature

8 Parameter Measurement Information

ISO5851-Q1 prop_delay_noninvert_SLLSEO1.gif Figure 38. OUT Propagation Delay, Non-Inverting Configuration
ISO5851-Q1 prop_delay_invert_SLLSEO1.gif Figure 39. OUT Propagation Delay, Inverting Configuration
ISO5851-Q1 DESAT_delay_SLLSEO1.gif Figure 40. DESAT, OUT, FLT, RST Delay
ISO5851-Q1 CMTI_test_circuit_sllseq1.gif Figure 41. Common-Mode Transient Immunity Test Circuit

 

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