ZHCSFJ0B August   2016  – February 2017 LM27762

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout
      2. 7.3.2 Input Current Limit
      3. 7.3.3 PFM Operation
      4. 7.3.4 Output Discharge
      5. 7.3.5 Power Good Output (PGOOD)
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Enable Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Positive Low-Dropout Linear Regulator and OUT+ Voltage Setting
        3. 8.2.2.3 Charge-Pump Voltage Inverter
        4. 8.2.2.4 Negative Low-Dropout Linear Regulator and OUT- Voltage Setting
        5. 8.2.2.5 External Capacitor Selection
          1. 8.2.2.5.1 Charge-Pump Output Capacitor
          2. 8.2.2.5.2 Input Capacitor
          3. 8.2.2.5.3 Flying Capacitor
          4. 8.2.2.5.4 LDO Output Capacitor
        6. 8.2.2.6 Power Dissipation
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
        1. 11.1.1.1 使用 WEBENCH® 工具创建定制设计
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

Layout

Layout Guidelines

The high switching frequency and large switching currents of the LM27762 make the choice of layout important. Use the following steps as a reference to ensure the device is stable and maintains proper LED current regulation across its intended operating voltage and current range:

  • Place CIN on the top layer (same layer as the LM27762) and as close as possible to the device. Connecting the input capacitor through short, wide traces to both the VIN and GND pins reduces the inductive voltage spikes that occur during switching, which can corrupt the VIN line.
  • Place CCPOUT on the top layer (same layer as the LM27762) and as close as possible to the VOUT and GND pins. The returns for both CIN and CCPOUT must come together at one point, as close as possible to the GND pin. Connecting CCPOUT through short, wide traces reduces the series inductance on the VCPOUT and GND pins that can corrupt the VCPOUT and GND lines and cause excessive noise in the device and surrounding circuitry.
  • Place C1 on top layer (same layer as the LM27762) and as close as possible to the device. Connect the flying capacitor through short, wide traces to both the C1+ and C1– pins.
  • Place COUT+, COUT– on the top layer (same layer as the LM27762) and as close to the respective OUT pin as possible. For best performance the ground connection for COUT must connect back to the GND connection at the thermal pad of the device.
  • Place R1 to R4 on the top layer (same layer as LM27762) and as close as possible to the respective FB pin. For best performance the ground connection of R2, R4 must connect back to the GND connection at the thermal pad of the device.

Connections using long trace lengths, narrow trace widths, or connections through vias must be avoided. These add parasitic inductance and resistance that results in inferior performance, especially during transient conditions.

Layout Example

LM27762 layout_SNVSAF7.gif Figure 16. LM27762 Layout Example
(Note: Pullup resistor for PGOOD not shown in example.)