DATA SHEET
CC1350 SimpleLink™ 超低功耗 双频带无线 MCU
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1 器件概述
1.1 特性
- 世界上第一款双频带（低于 1GHz 和 2.4GHz）无线微控制器
- 微控制器
- 性能强大的 Arm®Cortex®-M3 处理器
- EEMBC CoreMark®评分：142
- EEMBC ULPBench™评分：158
- 时钟速率最高可达 48MHz
- 128KB 系统内可编程闪存
- 8KB 缓存静态随机存取存储器 (SRAM)
（或用作通用 RAM） - 20KB 超低泄漏 SRAM
- 2 引脚 cJTAG 和 JTAG 调试
- 支持无线 (OTA) 升级
- 超低功耗传感器控制器
- 可独立于系统其余部分自主运行
- 16 位架构
- 2KB 超低泄漏代码和数据 SRAM
- 有效的代码尺寸架构，在 ROM 中放置
TI-RTOS、驱动程序、Bluetooth® 低功耗控制器以及引导加载程序的部件 - 与 RoHS 兼容的封装
- 7mm × 7mm RGZ VQFN48 封装（30 个通用输入/输出 (GPIO)）
- 5mm × 5mm RHB VQFN32 封装（15 个 GPIO）
- 4mm × 4mm RSM VQFN32 封装（10 个 GPIO）
- 外设
- 所有数字外设引脚均可连接任意 GPIO
- 四个通用定时器模块
（8 × 16 位或 4 × 32 位，均采用脉宽调制 (PWM)） - 12 位模数转换器 (ADC)、200MSPS、8 通道模拟多路复用器
- 持续时间比较器
- 超低功耗时钟比较器
- 可编程电流源
- UART
- 2 个同步串行接口 (SSI)（SPI、MICROWIRE 和 TI）
- I2C、I2S
- 实时时钟 (RTC)
- AES-128 安全模块
- 真随机数发生器 (TRNG)
- 支持八个电容感测按钮
- 集成温度传感器
- 外部系统
- 片上内部直流/直流转换器
- 无缝集成 SimpleLink™CC1190 和 CC2592 范围扩展器
- 低功耗
- 宽电源电压范围：1.8 至 3.8V
- RX：5.4mA（低于 1GHz），6.4mA（低功耗蓝牙，2.4GHz）
- TX（+10dBm 时）：13.4mA（低于 1GHz）
- TX（+9dBm 时）：22.3mA（低功耗蓝牙，2.4GHz）
- TX（+0dBm 时）：10.5mA（低功耗蓝牙，2.4GHz）
- Coremark 运行时的 48MHz 有源模式微控制器 (MCU)：2.5mA (51µA/MHz)
- 有源模式 MCU：48.5 CoreMark/mA
- 有源模式传感器控制器（24 MHz）：
0.4mA + 8.2μA/MHz - 传感器控制器，每秒唤醒一次来执行一次 12 位 ADC 采样：0.95µA
- 待机电流：0.7μA（实时时钟 (RTC) 运行，RAM 和 CPU 保持）
- 关断电流：185nA（发生外部事件时唤醒）
- 射频 (RF) 部分
- 2.4GHz RF 收发器，符合低功耗蓝牙 4.2 规范
- 出色的接收器灵敏度：远距离模式下为 –124dBm；50kbps 时为 –110dBm
（低于 1GHz），
低功耗蓝牙模式下为 –87dBm - 出色的可选择性 (±100kHz)：56dB
- 出色的阻断性能 (±10MHz)：
90dB - 可编程输出功率：低于 1GHz 时最高可达 +15dBm；2.4GHz（低功耗蓝牙）时最高可达 +9dBm
- 单端或差分 RF 接口
- 适用于符合全球射频规范的系统
- ETSI EN 300 220 和 EN 303 204（欧洲）
- EN 300 440 2 类（欧洲）
- EN 300 328（欧洲）
- FCC CFR47 第 15 部分（美国）
- ARIB STD-T66（日本）
- ARIB STD-T108（日本）
- 无线 M-Bus (EN 13757-4) 和 IEEE®802.15.4g PHY
- 工具和开发环境
- 功能全面的低成本开发套件
- 针对不同 RF 配置的多种参考设计
- 数据包监听器 PC 软件
- Sensor Controller Studio
- SmartRF™Studio
- SmartRF Flash Programmer 2
- IAR Embedded Workbench®（适用于 Arm）
- Code Composer Studio™(CCS) IDE
- CCS UniFlash
空白
空白
空白
空白
1.2 应用
- 315、433、470、500、779、868、915、
920MHz 和 2.4GHz 工业、科学和医疗 (ISM) 及短程设备 (SRD) 系统 - 信道间隔为 50kHz 至 5MHz 的
低功耗无线系统 - 家庭和楼宇自动化
- 无线警报和安全系统
- 工业用监控和控制
- 低功耗蓝牙信标管理
- 低功耗蓝牙调试
- 智能电网和自动抄表
- 无线医疗保健 应用
- 无线传感器网络
- 有源射频识别 (RFID)
- IEEE 802.15.4g、支持 IP 的智能对象 (6LoWPAN)、无线仪表总线、KNX 系统、
Wi-SUN™及专有系统 - 能量收集 应用
- 电子货架标签 (ESL)
- 远距离传感器 应用
- 热量分配表
1.3 说明
CC1350 器件是一款经济高效型超低功耗双频带射频器件，由 德州仪器 (TI)™倾力打造，属于 SimpleLink™ 微控制器 (MCU) 平台的组成部分。该平台包含 Wi-Fi®、低功耗 Bluetooth®、低于 1GHz、以太网、 Zigbee®、Thread 和主机 MCU。所有这些器件均共用一个简单易用的通用开发环境，其中包含单个核心软件开发套件 (SDK) 和丰富的工具集。借助一次性集成的 SimpleLink 平台，用户可以将产品组合中的任何器件组合添加到自己的设计中，从而在设计要求变更时实现 100% 代码重用。有关更多信息，请访问 www.ti.com.cn/simplelink。
凭借极低的有源射频和 MCU 电流消耗以及灵活的低功耗模式， 器件可确保卓越的电池寿命，并能够在小型纽扣电池供电的情况下以及在能量采集应用中实现远距离 工作。
CC1350 器件是 CC13xx 和 CC26xx 系列经济高效型超低功耗无线 MCU 中的一员，能够同时支持低于 1GHz 和 2.4GHz 射频。CC1350 器件在一个支持多个物理层和射频标准的平台上将灵活的超低功耗射频收发器与强大的 48MHz Arm® Cortex®-M3 微控制器结合在一起。专用无线电控制器 (Cortex®-M0) 可处理存储在 ROM 或 RAM 中的低级射频协议命令，因而可确保超低功耗和灵活性以同时支持低于 1GHz 协议和 2.4GHz 协议（例如低功耗蓝牙）。因此，可以将低于 1GHz 通信解决方案（提供绝佳的射频范围）与低功耗蓝牙智能手机通信连接（通过手机应用程序提供出色的用户体验）完美结合。该系列中唯一一款低于 1GHz 的器件是 CC1310。
CC1350 器件是高度集成的真正的单芯片解决方案，整合了完整的射频系统和片上直流/直流转换器。
传感器可由专用的超低功耗自主 MCU 以超低功耗方式进行处理（该 MCU 可配置为处理模拟和数字传感器），因此主 MCU (Arm® Cortex®-M3) 能够最大限度延长睡眠时间。
CC1350 器件的电源和时钟管理系统以及无线电系统需要采用特定配置并由软件处理才能正确运行，这已在 TI-RTOS 中实现。TI 建议将此软件框架用于该器件的全部应用开发过程。完整的 TI-RTOS 和设备驱动程序均有免费的源代码可供使用。
2 修订历史记录
Changes from November 20, 2016 to July 13, 2018 (from A Revision () to B Revision)
- Changed 描述 部分 Go
- Changed Table 3-1Go
- Changed test conditions for Receiver sensitivity, 50 kbps in Section 5.6Go
- Added parameters to Section 5.6Go
- Added Receiver sensitivity parameters to Section 5.7Go
- Changed Go
- Changed footnote in Go
- Added “软件”部分Go
Changes from June 20, 2016 to November 20, 2016 (from * Revision () to A Revision)
- Added 4mm × 4mm 和 5mm × 5mm 封装Go
- Added Figure 4-1Go
- Added Figure 4-2Go
- Added support for split supply rail to Section 5.3Go
- Added OOK modulation support to Section 5.4Go
- Added receive parameters for 431-MHz to 527-MHz band in Section 5.7Go
- Added transmit parameters for 431-MHz to 527-MHz band in Section 5.9Go
- Changed ADC reference voltage to correct value in Section 5.13Go
- Added thermal characteristics for RHB and RSM packages in Section 5.20Go
- Added Figure 5-10Go
- Added Section 6.10Go
- Changed Figure 8-1Go
3 Device Comparison
Table 3-1 lists the device family overview.
Table 3-1 Device Family Overview
| DEVICE | RADIO SUPPORT | FLASH
(KB) |
RAM
(KB) |
GPIOs | PACKAGE SIZE |
|---|---|---|---|---|---|
| CC1350F128RGZ | Proprietary, Wireless M-Bus,
IEEE 802.15.4g, Bluetooth low energy |
128 | 20 | 30 | RGZ (7 mm × 7 mm VQFN48)
|
| CC1350F128RHB | Proprietary, Wireless M-Bus,
IEEE 802.15.4g, Bluetooth low energy |
128 | 20 | 15 | RHB (5 mm × 5 mm VQFN32) |
| CC1350F128RSM | Proprietary, Wireless M-Bus,
IEEE 802.15.4g, Bluetooth low energy |
128 | 20 | 10 | RSM (4 mm × 4 mm VQFN32) |
| CC1310 | Sub-1 GHz
Proprietary, Wireless M-Bus, IEEE 802.15.4g |
128
64/32 |
20
16 |
10-30 | RGZ (7 mm × 7 mm VQFN48)
RHB (5 mm × 5 mm VQFN32) RSM (4 mm × 4 mm VQFN32) |
| CC2640R2 | Bluetooth 5 low energy
2.4-GHz proprietary FSK-based formats |
128 | 20 | 10-31 | RGZ (7 mm × 7 mm VQFN48)
RHB (5 mm × 5 mm VQFN32) RSM (4 mm × 4 mm VQFN32) YFV (2.7 mm × 2.7 mm DSBGA34) |
| CC1312R | Sub-1 GHz
Proprietary, Wireless M-Bus, IEEE 802.15.4g |
352 | 80 | 30 | RGZ (7 mm × 7 mm VQFN48) |
| CC1352R | Dual-band (2.4-GHz and Sub-1 GHz) Multiprotocol | 352 | 80 | 28 | RGZ (7 mm × 7 mm VQFN48) |
| CC2642R | Bluetooth 5 low energy
2.4-GHz proprietary FSK-based formats |
352 | 80 | 31 | RGZ (7 mm × 7 mm VQFN48) |
| CC2652R | Multiprotocol
Bluetooth 5 low energy Zigbee Thread 2.4-GHz proprietary FSK-based formats |
352 | 80 | 31 | RGZ (7 mm × 7 mm VQFN48) |
3.1 Related Products
- Wireless Connectivity
The wireless connectivity portfolio offers a wide selection of low-power RF solutions suitable for a broad range of application. The offerings range from fully customized solutions to turnkey offerings with precertified hardware and software (protocol).
- Sub-1 GHz
Long-range, low power wireless connectivity solutions are offered in a wide range of
Sub-1 GHz ISM bands.
- Companion Products
Review products that are frequently purchased or used with this product.
4 Terminal Configuration and Functions
4.1 Pin Diagram – RSM Package
Figure 4-1 shows the RSM pinout diagram.
I/O pins marked in Figure 4-1 in bold have high-drive capabilities; they are as follows:
- Pin 8, DIO_0
- Pin 9, DIO_1
- Pin 10, DIO_2
- Pin 13, JTAG_TMSC
- Pin 15, DIO_3
- Pin 16, DIO_4
I/O pins marked in Figure 4-1 in italics have analog capabilities; they are as follows:
- Pin 22, DIO_5
- Pin 23, DIO_6
- Pin 24, DIO_7
- Pin 25, DIO_8
- Pin 26, DIO_9
4.2 Signal Descriptions – RSM Package
Table 4-1 Signal Descriptions – RSM Package
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| DCDC_SW | 18 | Power | Output from internal DC/DC(1) |
| DCOUPL | 12 | Power | 1.27-V regulated digital-supply decoupling capacitor(2) |
| DIO_0 | 8 | Digital I/O | GPIO, Sensor Controller, high-drive capability |
| DIO_1 | 9 | Digital I/O | GPIO, Sensor Controller, high-drive capability |
| DIO_2 | 10 | Digital I/O | GPIO, Sensor Controller, high-drive capability |
| DIO_3 | 15 | Digital I/O | GPIO, high-drive capability, JTAG_TDO |
| DIO_4 | 16 | Digital I/O | GPIO, high-drive capability, JTAG_TDI |
| DIO_5 | 22 | Digital or analog I/O | GPIO, Sensor Controller, analog |
| DIO_6 | 23 | Digital or analog I/O | GPIO, Sensor Controller, analog |
| DIO_7 | 24 | Digital or analog I/O | GPIO, Sensor Controller, analog |
| DIO_8 | 25 | Digital or analog I/O | GPIO, Sensor Controller, analog |
| DIO_9 | 26 | Digital or analog I/O | GPIO, Sensor Controller, analog |
| EGP | – | Power | Ground; exposed ground pad |
| JTAG_TMSC | 13 | Digital I/O | JTAG TMSC |
| JTAG_TCKC | 14 | Digital I/O | JTAG TCKC(3) |
| RESET_N | 21 | Digital input | Reset, active low. No internal pullup. |
| RF_N | 2 | RF I/O | Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX |
| RF_P | 1 | RF I/O | Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX |
| RX_TX | 4 | RF I/O | Optional bias pin for the RF LNA |
| VDDS | 27 | Power | 1.8-V to 3.8-V main chip supply(1) |
| VDDS2 | 11 | Power | 1.8-V to 3.8-V GPIO supply(1) |
| VDDS_DCDC | 19 | Power | 1.8-V to 3.8-V DC/DC supply |
| VDDR | 28 | Power | 1.7-V to 1.95-V supply, connect to output of internal DC/DC(2)(4) |
| VDDR_RF | 32 | Power | 1.7-V to 1.95-V supply, connect to output of internal DC/DC(2)(5) |
| VSS | 3, 7, 17,
20, 29 |
Power | Ground |
| X32K_Q1 | 5 | Analog I/O | 32-kHz crystal oscillator pin 1 |
| X32K_Q2 | 6 | Analog I/O | 32-kHz crystal oscillator pin 2 |
| X24M_N | 30 | Analog I/O | 24-MHz crystal oscillator pin 1 |
| X24M_P | 31 | Analog I/O | 24-MHz crystal oscillator pin 2 |
(1) See the technical reference manual listed in Section 8.3 for more details.
(2) Do not supply external circuitry from this pin.
(3) For design consideration regrading noise immunity for this pin, see the JTAG Interface chapter in the CC13x0, CC26x0 SimpleLink™ Wireless MCU Technical Reference Manual.
(4) If internal DC/DC is not used, this pin is supplied internally from the main LDO.
(5) If internal DC/DC is not used, this pin must be connected to VDDR for supply from the main LDO.
4.3 Pin Diagram – RHB Package
Figure 4-2 shows the RHB pinout diagram.
I/O pins marked in Figure 4-2 in bold have high-drive capabilities; they are as follows:
- Pin 8, DIO_2
- Pin 9, DIO_3
- Pin 10, DIO_4
- Pin 15, DIO_5
- Pin 16, DIO_6
I/O pins marked in Figure 4-2 in italics have analog capabilities; they are as follows:
- Pin 20, DIO_7
- Pin 21, DIO_8
- Pin 22, DIO_9
- Pin 23, DIO_10
- Pin 24, DIO_11
- Pin 25, DIO_12
- Pin 26, DIO_13
- Pin 27, DIO_14
4.4 Signal Descriptions – RHB Package
Table 4-2 Signal Descriptions – RHB Package
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| DCDC_SW | 17 | Power | Output from internal DC/DC(1) |
| DCOUPL | 12 | Power | 1.27-V regulated digital-supply decoupling(2) |
| DIO_0 | 6 | Digital I/O | GPIO, Sensor Controller |
| DIO_1 | 7 | Digital I/O | GPIO, Sensor Controller |
| DIO_2 | 8 | Digital I/O | GPIO, Sensor Controller, high-drive capability |
| DIO_3 | 9 | Digital I/O | GPIO, Sensor Controller, high-drive capability |
| DIO_4 | 10 | Digital I/O | GPIO, Sensor Controller, high-drive capability |
| DIO_5 | 15 | Digital I/O | GPIO, high-drive capability, JTAG_TDO |
| DIO_6 | 16 | Digital I/O | GPIO, high-drive capability, JTAG_TDI |
| DIO_7 | 20 | Digital or analog I/O | GPIO, Sensor Controller, analog |
| DIO_8 | 21 | Digital or analog I/O | GPIO, Sensor Controller, analog |
| DIO_9 | 22 | Digital or analog I/O | GPIO, Sensor Controller, analog |
| DIO_10 | 23 | Digital or analog I/O | GPIO, Sensor Controller, Analog |
| DIO_11 | 24 | Digital or analog I/O | GPIO, Sensor Controller, analog |
| DIO_12 | 25 | Digital or analog I/O | GPIO, Sensor Controller, analog |
| DIO_13 | 26 | Digital or analog I/O | GPIO, Sensor Controller, analog |
| DIO_14 | 27 | Digital or analog I/O | GPIO, Sensor Controller, analog |
| EGP | – | Power | Ground; exposed ground pad |
| JTAG_TMSC | 13 | Digital I/O | JTAG TMSC, high-drive capability |
| JTAG_TCKC | 14 | Digital I/O | JTAG TCKC(3) |
| RESET_N | 19 | Digital input | Reset, active low. No internal pullup. |
| RF_N | 2 | RF I/O | Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX |
| RF_P | 1 | RF I/O | Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX |
| RX_TX | 3 | RF I/O | Optional bias pin for the RF LNA |
| VDDR | 29 | Power | 1.7-V to 1.95-V supply, connect to output of internal DC/DC(2)(4) |
| VDDR_RF | 32 | Power | 1.7-V to 1.95-V supply, connect to output of internal DC/DC(2)(5) |
| VDDS | 28 | Power | 1.8-V to 3.8-V main chip supply(1) |
| VDDS2 | 11 | Power | 1.8-V to 3.8-V GPIO supply(1) |
| VDDS_DCDC | 18 | Power | 1.8-V to 3.8-V DC/DC supply |
| X24M_N | 30 | Analog I/O | 24-MHz crystal oscillator pin 1 |
| X24M_P | 31 | Analog I/O | 24-MHz crystal oscillator pin 2 |
| X32K_Q1 | 4 | Analog I/O | 32-kHz crystal oscillator pin 1 |
| X32K_Q2 | 5 | Analog I/O | 32-kHz crystal oscillator pin 2 |
(1) For more details, see the technical reference manual listed in Section 8.3.
(2) Do not supply external circuitry from this pin.
(3) For design consideration regrading noise immunity for this pin, see the JTAG Interface chapter in the CC13x0, CC26x0 SimpleLink™ Wireless MCU Technical Reference Manual.
(4) If internal DC/DC is not used, this pin is supplied internally from the main LDO.
(5) If internal DC/DC is not used, this pin must be connected to VDDR for supply from the main LDO.
4.5 Pin Diagram – RGZ Package
Figure 4-3 shows the RGZ pinout diagram.
Figure 4-3 RGZ (7-mm × 7-mm) Pinout, 0.5-mm Pitch
Top View
I/O pins marked in Figure 4-3 in bold have high-drive capabilities; they are as follows:
- Pin 10, DIO_5
- Pin 11, DIO_6
- Pin 12, DIO_7
- Pin 24, JTAG_TMSC
- Pin 26, DIO_16
- Pin 27, DIO_17
I/O pins marked in Figure 4-3 in italics have analog capabilities; they are as follows:
- Pin 36, DIO_23
- Pin 37, DIO_24
- Pin 38, DIO_25
- Pin 39, DIO_26
- Pin 40, DIO_27
- Pin 41, DIO_28
- Pin 42, DIO_29
- Pin 43, DIO_30
4.6 Signal Descriptions – RGZ Package
Table 4-3 Signal Descriptions – RGZ Package
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| DCDC_SW | 33 | Power | Output from internal DC/DC(1)(2) |
| DCOUPL | 23 | Power | 1.27-V regulated digital-supply (decoupling capacitor)(2) |
| DIO_1 | 6 | Digital I/O | GPIO, Sensor Controller |
| DIO_2 | 7 | Digital I/O | GPIO, Sensor Controller |
| DIO_3 | 8 | Digital I/O | GPIO, Sensor Controller |
| DIO_4 | 9 | Digital I/O | GPIO, Sensor Controller |
| DIO_5 | 10 | Digital I/O | GPIO, Sensor Controller, high-drive capability |
| DIO_6 | 11 | Digital I/O | GPIO, Sensor Controller, high-drive capability |
| DIO_7 | 12 | Digital I/O | GPIO, Sensor Controller, high-drive capability |
| DIO_8 | 14 | Digital I/O | GPIO |
| DIO_9 | 15 | Digital I/O | GPIO |
| DIO_10 | 16 | Digital I/O | GPIO |
| DIO_11 | 17 | Digital I/O | GPIO |
| DIO_12 | 18 | Digital I/O | GPIO |
| DIO_13 | 19 | Digital I/O | GPIO |
| DIO_14 | 20 | Digital I/O | GPIO |
| DIO_15 | 21 | Digital I/O | GPIO |
| DIO_16 | 26 | Digital I/O | GPIO, JTAG_TDO, high-drive capability |
| DIO_17 | 27 | Digital I/O | GPIO, JTAG_TDI, high-drive capability |
| DIO_18 | 28 | Digital I/O | GPIO |
| DIO_19 | 29 | Digital I/O | GPIO |
| DIO_20 | 30 | Digital I/O | GPIO |
| DIO_21 | 31 | Digital I/O | GPIO |
| DIO_22 | 32 | Digital I/O | GPIO |
| DIO_23 | 36 | Digital or analog I/O | GPIO, Sensor Controller, analog |
| DIO_24 | 37 | Digital or analog I/O | GPIO, Sensor Controller, analog |
| DIO_25 | 38 | Digital or analog I/O | GPIO, Sensor Controller, analog |
| DIO_26 | 39 | Digital or analog I/O | GPIO, Sensor Controller, analog |
| DIO_27 | 40 | Digital or analog I/O | GPIO, Sensor Controller, analog |
| DIO_28 | 41 | Digital or analog I/O | GPIO, Sensor Controller, analog |
| DIO_29 | 42 | Digital or analog I/O | GPIO, Sensor Controller, analog |
| DIO_30 | 43 | Digital or analog I/O | GPIO, Sensor Controller, analog |
| EGP | – | Power | Ground; exposed ground pad |
| JTAG_TMSC | 24 | Digital I/O | JTAG TMSC, high-drive capability |
| JTAG_TCKC | 25 | Digital I/O | JTAG TCKC(3) |
| RESET_N | 35 | Digital input | Reset, active-low. No internal pullup. |
| RF_N | 2 | RF I/O | Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX |
| RF_P | 1 | RF I/O | Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX |
| VDDR | 45 | Power | 1.7-V to 1.95-V supply, connect to output of internal DC/DC(2)(4) |
| VDDR_RF | 48 | Power | 1.7-V to 1.95-V supply, connect to output of internal DC/DC(2)(5) |
| VDDS | 44 | Power | 1.8-V to 3.8-V main chip supply(1) |
| VDDS2 | 13 | Power | 1.8-V to 3.8-V DIO supply(1) |
| VDDS3 | 22 | Power | 1.8-V to 3.8-V DIO supply(1) |
| VDDS_DCDC | 34 | Power | 1.8-V to 3.8-V DC/DC supply |
| X24M_N | 46 | Analog I/O | 24-MHz crystal oscillator pin 1 |
| X24M_P | 47 | Analog I/O | 24-MHz crystal oscillator pin 2 |
| RX_TX | 3 | RF I/O | Optional bias pin for the RF LNA |
| X32K_Q1 | 4 | Analog I/O | 32-kHz crystal oscillator pin 1 |
| X32K_Q2 | 5 | Analog I/O | 32-kHz crystal oscillator pin 2 |
(1) See technical reference manual listed in Section 8.3 for more details.
(2) Do not supply external circuitry from this pin.
(3) For design consideration regrading noise immunity for this pin, see the JTAG Interface chapter in the CC13x0, CC26x0 SimpleLink™ Wireless MCU Technical Reference Manual.
(4) If internal DC/DC is not used, this pin is supplied internally from the main LDO.
(5) If internal DC/DC is not used, this pin must be connected to VDDR for supply from the main LDO.
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Supply voltage (VDDS, VDDS2, and VDDS3) | –0.3 | 4.1 | V | |
| Voltage on any digital pin(4)(3) | –0.3 | VDDSn + 0.3, max 4.1 | V | |
| Voltage on crystal oscillator pins X32K_Q1, X32K_Q2, X24M_N, and X24M_P | –0.3 | VDDR + 0.3, max 2.25 | V | |
| Voltage on ADC input (Vin) | Voltage scaling enabled | –0.3 | VDDS | V |
| Voltage scaling disabled, internal reference | –0.3 | 1.49 | ||
| Voltage scaling disabled, VDDS as reference | –0.3 | VDDS / 2.9 | ||
| Input RF level | 10 | dBm | ||
| Storage temperature (Tstg) | –40 | 150 | °C | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to ground, unless otherwise noted.
(3) Each pin is referenced to a specific VDDSn (VDDS, VDDS2 or VDDS3). For a pin-to-VDDS mapping table, see Table 6-3.
(4) Including analog-capable DIO.
5.2 ESD Ratings
| VALUE | UNIT | ||||
|---|---|---|---|---|---|
| VESD | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS001(1) | All pins | ±3000 | V |
| Charged device model (CDM), per JESD22-C101(2) | All pins | ±500 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| Ambient temperature | –40 | 85 | °C | ||
| Operating supply voltage (VDDS) | For operation in battery-powered and
3.3-V systems (internal DC/DC can be used to minimize power consumption) |
1.8 | 3.8 | V | |
| Operating supply voltages (VDDS2 and VDDS3) | VDDS < 2.7 V | 1.8 | 3.8 | V | |
| Operating supply voltages (VDDS2 and VDDS3) | VDDS ≥ 2.7 V | 1.9 | 3.8 | V | |
| Rising supply voltage slew rate | 0 | 100 | mV/µs | ||
| Falling supply voltage slew rate | 0 | 20 | mV/µs | ||
| Falling supply voltage slew rate, with low-power flash setting(1) | 3 | mV/µs | |||
| Positive temperature gradient in standby(2) | No limitation for negative temperature gradient, or outside standby mode | 5 | °C/s | ||
(1) For small coin-cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-µF VDDS input capacitor must be used to ensure compliance with this slew rate.
(2) Applications using RCOSC_LF as sleep timer must also consider the drift in frequency caused by a change in temperature (see ).
