VNDRID_BY1 |
0 |
0x10 |
VNDRID[15:8] |
VNDRID_BY0 |
1 |
0x0B |
VNDRID[7:0] |
PRODID |
2 |
0x33 |
PRODID[7:0]
|
REVID |
3 |
0x02 |
REVID[7:0]
|
PARTID |
4 |
0x01 |
PRTID[7:0] |
PINMODE_SW |
8 |
0x00 |
HW_SW_CTRL_MODE |
GPIO32_SW_MODE[2:0] |
RSRVD |
PINMODE_HW |
9 |
0x00 |
GPIO_HW_MODE[5:0] |
RSRVD |
SLAVEADR |
10 |
0x50 |
SLAVEADR_GPIO1_SW[7:1] |
RSRVD |
EEREV |
11 |
0x00 |
EEREV[7:0] |
DEV_CTL |
12 |
0xD9 |
RESETN_SW |
SYNCN_SW |
RSRVD |
SYNC_AUTO |
SYNC_MUTE |
AONAFTER
LOCK |
PLLSTRTMODE |
AUTOSTRT |
INT_LIVE |
13 |
0x00 |
LOL |
LOS |
CAL |
RSRVD |
SECTOPRI |
RSRVD |
INT_MASK |
14 |
0x00 |
LOL_MASK |
LOS_MASK |
CAL_MASK |
RSRVD |
SECTOPRI_ MASK |
RSRVD |
INT_FLAG_POL |
15 |
0x00 |
LOL_POL |
LOS_POL |
CAL_POL |
RSRVD |
SECTOPRI_ POL |
RSRVD |
INT_FLAG |
16 |
0x00 |
LOL_INTR |
LOS_INTR |
CAL_INTR |
RSRVD |
SECTOPRI_ INTR |
RSRVD |
INTCTL |
17 |
0x00 |
RSRVD |
INT_AND_OR |
INT_EN |
OSCCTL2 |
18 |
0x00 |
RISE_VALID_
SEC |
FALL_VALID_
SEC |
RISE_VALID_
PRI |
FALL_VALID_
PRI |
RSRVD |
STATCTL |
19 |
0x00 |
RSRVD |
STAT1_SHOOT_THRU_LIMIT |
STAT0_SHOOT_THRU_LIMIT |
RSRVD |
STAT1_OPEND |
STAT0_OPEND |
MUTELVL1 |
20 |
0x55 |
CH3_MUTE_LVL[1:0] |
CH2_MUTE_LVL[1:0] |
CH1_MUTE_LVL[1:0] |
CH0_MUTE_LVL[1:0] |
MUTELVL2 |
21 |
0x55 |
CH7_MUTE_LVL[1:0] |
CH6_MUTE_LVL[1:0] |
CH5_MUTE_LVL[1:0] |
CH4_MUTE_LVL[1:0] |
OUT_MUTE |
22 |
0xFF |
CH_7_MUTE |
CH_6_MUTE |
CH_5_MUTE |
CH_4_MUTE |
CH_3_MUTE |
CH_2_MUTE |
CH_1_MUTE |
CH_0_MUTE |
STATUS_MUTE |
23 |
0x02 |
RSRVD |
STATUS1_
MUTE |
STATUS0_
MUTE |
DYN_DLY |
24 |
0x00 |
RSRVD |
DIV_7_DYN_
DLY |
DIV_6_DYN_
DLY |
DIV_5_DYN_
DLY |
DIV_4_DYN_
DLY |
DIV_23_DYN_
DLY |
DIV_01_DYN_
DLY |
REFDETCTL |
25 |
0x55 |
DETECT_MODE_SEC[1:0] |
DETECT_MODE_PRI[1:0] |
LVL_SEL_SEC[1:0] |
LVL_SEL_PRI[1:0] |
STAT0_INT |
27 |
0x58 |
STAT0_SEL[3:0] |
STAT0_POL |
RSRVD |
STAT1 |
28 |
0x28 |
STAT1_SEL[3:0] |
STAT1_POL |
RSRVD |
OSCCTL1 |
29 |
0x06 |
DETECT_BYP |
RSRVD |
TERM2GND_
SEC |
TERM2GND_
PRI |
DIFFTERM_SEC |
DIFFTERM_PRI |
AC_MODE_SEC |
AC_MODE_PRI |
PWDN |
30 |
0x00 |
RSRVD |
CMOSCHPWDN |
CH7PWDN |
CH6PWDN |
CH5PWDN |
CH4PWDN |
CH23PWDN |
CH01PWDN |
OUTCTL_0 |
31 |
0xB0 |
RSRVD |
OUT_0_SEL[1:0] |
OUT_0_MODE1[1:0] |
OUT_0_MODE2[1:0] |
RSRVD |
OUTCTL_1 |
32 |
0x30 |
RSRVD |
OUT_1_SEL[1:0] |
OUT_1_MODE1[1:0] |
OUT_1_MODE2[1:0] |
RSRVD |
OUTDIV_0_1 |
33 |
0x01 |
OUT_0_1_DIV[7:0] |
OUTCTL_2 |
34 |
0xB0 |
RSRVD |
OUT_2_SEL[1:0] |
OUT_2_MODE1[1:0] |
OUT_2_MODE2[1:0] |
RSRVD |
OUTCTL_3 |
35 |
0x30 |
RSRVD |
OUT_3_SEL[1:0] |
OUT_3_MODE1[1:0] |
OUT_3_MODE2[1:0] |
RSRVD |
OUTDIV_2_3 |
36 |
0x03 |
OUT_2_3_DIV[7:0] |
OUTCTL_4 |
37 |
0x18 |
CH_4_MUX[1:0] |
OUT_4_SEL[1:0] |
OUT_4_MODE1[1:0] |
OUT_4_MODE2[1:0] |
OUTDIV_4 |
38 |
0x02 |
OUT_4_DIV[7:0] |
OUTCTL_5 |
39 |
0x18 |
CH_5_MUX[1:0] |
OUT_5_SEL[1:0] |
OUT_5_MODE1[1:0] |
OUT_5_MODE2[1:0] |
OUTDIV_5 |
40 |
0x02 |
OUT_5_DIV[7:0] |
OUTCTL_6 |
41 |
0x18 |
CH_6_MUX[1:0] |
OUT_6_SEL[1:0] |
OUT_6_MODE1[1:0] |
OUT_6_MODE2[1:0] |
OUTDIV_6 |
42 |
0x05 |
OUT_6_DIV[7:0] |
OUTCTL_7 |
43 |
0x18 |
CH_7_MUX[1:0] |
OUT_7_SEL[1:0] |
OUT_7_MODE1[1:0] |
OUT_7_MODE2[1:0] |
OUTDIV_7 |
44 |
0x05 |
OUT_7_DIV[7:0] |
CMOSDIVCTRL |
45 |
0x0A |
RSRVD |
PLLCMOSPREDIV[1:0] |
STATUS1MUX[1:0] |
STATUS0MUX[1:0] |
CMOSDIV0 |
46 |
0x00 |
CMOSDIV0[7:0] |
STATUS_SLEW |
49 |
0x00 |
RSRVD |
STATUS1SLEW[1:0] |
STATUS0SLEW[1:0] |
IPCLKSEL |
50 |
0x95 |
SECBUFSEL[1:0] |
PRIBUFSEL[1:0] |
RSRVD |
INSEL_PLL[1:0] |
IPCLKCTL |
51 |
0x03 |
CLKMUX_
BYPASS |
RSRVD |
SECONSWITCH |
SECBUFGAIN |
PRIBUFGAIN |
PLL_RDIV |
52 |
0x00 |
RSRVD |
PLLRDIV[2:0] |
PLL_MDIV |
53 |
0x00 |
RSRVD |
PLLMDIV[4:0] |
PLL_CTRL0 |
56 |
0x1E |
RSRVD |
PLL_P[2:0] |
PLL_SYNC_EN |
PLL_PDN |
PLL_CTRL1 |
57 |
0x18 |
RSRVD |
PRI_D |
PLL_CP[3:0] |
PLL_NDIV_BY1 |
58 |
0x00 |
RSRVD |
PLL_NDIV[11:8] |
PLL_NDIV_BY0 |
59 |
0x66 |
PLL_NDIV[7:0] |
PLL_
FRACNUM_BY2 |
60 |
0x00 |
RSRVD |
PLL_NUM[21:16] |
PLL_
FRACNUM_BY1 |
61 |
0x00 |
PLL_NUM[15:8] |
PLL_
FRACNUM_BY0 |
62 |
0x00 |
PLL_NUM[7:0] |
PLL_
FRACDEN_BY2 |
63 |
0x00 |
RSRVD |
PLL_DEN[21:16] |
PLL_
FRACDEN_BY1 |
64 |
0x00 |
PLL_DEN[15:8] |
PLL_
FRACDEN_BY0 |
65 |
0x00 |
PLL_DEN[7:0] |
PLL_
MASHCTRL |
66 |
0x0C |
RSRVD |
PLL_DTHRMODE[1:0] |
PLL_ORDER[1:0] |
PLL_LF_R2 |
67 |
0x24 |
RSRVD |
PLL_LF_R2[5:0] |
PLL_LF_C1 |
68 |
0x00 |
RSRVD |
PLL_LF_C1[2:0] |
PLL_LF_R3 |
69 |
0x00 |
RSRVD |
PLL_LF_R3[5:0] |
PLL_LF_INT_FRAC |
PLL_LF_C3 |
70 |
0x00 |
RSRVD |
|
PLL_LF_C3[2:0] |
SEC_CTRL |
72 |
0x18 |
RSRVD |
SEC_D |
RSRVD |
XO_MARGINING |
86 |
0x00 |
RSRVD |
MARGIN_DIG_STEP[2:0] |
MARGIN_OPTION[1:0] |
RSRVD |
RSRVD |
XO_OFFSET_
GPIO5_STEP_1_BY1 |
88 |
0x00 |
RSRVD |
XOOFFSET_STEP1[9:8] |
XO_OFFSET_
GPIO5_STEP_1_BY0 |
89 |
0xDE |
XOOFFSET_STEP1[7:0] |
XO_OFFSET_
GPIO5_STEP_2_BY1 |
90 |
0x01 |
RSRVD |
XOOFFSET_STEP2[9:8] |
XO_OFFSET_
GPIO5_STEP_2_BY0 |
91 |
0x18 |
XOOFFSET_STEP2[7:0] |
XO_OFFSET_
GPIO5_STEP_3_BY1 |
92 |
0x01 |
RSRVD |
XOOFFSET_STEP3[9:8] |
XO_OFFSET_
GPIO5_STEP_3_BY0 |
93 |
0x4B |
XOOFFSET_STEP3[7:0] |
XO_OFFSET_
GPIO5_STEP_4_BY1 |
94 |
0x01 |
RSRVD |
XOOFFSET_STEP4[9:8] |
XO_OFFSET_
GPIO5_STEP_4_BY0 |
95 |
0x86 |
XOOFFSET_STEP4[7:0] |
XO_OFFSET_
GPIO5_STEP_5_BY1 |
96 |
0x01 |
RSRVD |
XOOFFSET_STEP5[9:8] |
XO_OFFSET_
GPIO5_STEP_5_BY0 |
97 |
0xBE |
XOOFFSET_STEP5[7:0] |
XO_OFFSET_
GPIO5_STEP_6_BY1 |
98 |
0x01 |
RSRVD |
XOOFFSET_STEP6[9:8] |
XO_OFFSET_
GPIO5_STEP_6_BY0 |
99 |
0xFE |
XOOFFSET_STEP6[7:0] |
XO_OFFSET_
GPIO5_STEP_7_BY1 |
100 |
0x02 |
RSRVD |
XOOFFSET_STEP7[9:8] |
XO_OFFSET_
GPIO5_STEP_7_BY0 |
101 |
0x47 |
XOOFFSET_STEP7[7:0] |
XO_OFFSET_
GPIO5_STEP_8_BY1 |
102 |
0x02 |
RSRVD |
XOOFFSET_STEP8[9:8] |
XO_OFFSET_
GPIO5_STEP_8_BY0 |
103 |
0x9E |
XOOFFSET_STEP8[7:0] |
XO_OFFSET_
SW_BY1 |
104 |
0x00 |
RSRVD |
XOOFFSET_SW[9:8] |
XO_OFFSET_
SW_BY0 |
105 |
0x00 |
XOOFFSET_SW[7:0] |
PLL_CTRL2 |
117 |
0x00 |
PLL_STRETCH |
RSRVD |
PLL_CTRL3 |
118 |
0x03 |
RSRVD |
PLL_DISABLE_4TH[2:0] |
PLL_
CALCTRL0 |
119 |
0x01 |
RSRVD |
PLL_CLSDWAIT[1:0] |
PLL_VCOWAIT[1:0] |
PLL_
CALCTRL1 |
120 |
0x00 |
RSRVD |
PLL_LOOPBW |
NVMSCRC |
135 |
0x00 |
NVMSCRC[7:0] |
NVMCNT |
136 |
0x00 |
NVMCNT[7:0] |
NVMCTL |
137 |
0x10 |
RSRVD |
REGCOMMIT |
NVMCRCERR |
NVMAUTOCRC |
NVMCOMMIT |
NVMBUSY |
RSRVD |
NVMPROG |
NVMLCRC |
138 |
0x00 |
NVMLCRC[7:0] |
MEMADR_BY1 |
139 |
0x00 |
RSRVD |
MEMADR[11:8] |
MEMADR_BY0 |
140 |
0x00 |
MEMADR[7:0] |
NVMDAT |
141 |
0x00 |
NVMDAT[7:0] |
RAMDAT |
142 |
0x00 |
RAMDAT[7:0] |
ROMDAT |
143 |
0x00 |
ROMDAT[7:0] |
NVMUNLK |
144 |
0x00 |
NVMUNLK[7:0] |
REGCOMMIT_
PAGE |
145 |
0x00 |
RSRVD |
REGCOMMIT_PG[3:0] |
XOCAPCTRL_
BY1 |
199 |
0x00 |
RSRVD |
XO_CAP_CTRL[9:8] |
XOCAPCTRL_
BY0 |
200 |
0x00 |
XO_CAP_CTRL[7:0] |