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  • DP83867E/IS/CS 稳健型高抗扰性小型 10/100/1000 以太网物理层收发器

    • ZHCSEC3F October   2015  – January 2025 DP83867CS , DP83867E , DP83867IS

      PRODUCTION DATA  

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  • DP83867E/IS/CS 稳健型高抗扰性小型 10/100/1000 以太网物理层收发器
  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions
    2. 5.2 Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Power-Up Timing
    7. 6.7  Reset Timing
    8. 6.8  MII Serial Management Timing
    9. 6.9  SGMII Timing
    10. 6.10 RGMII Timing
    11. 6.11 DP83867E Start of Frame Detection Timing
    12. 6.12 DP83867IS/CS Start of Frame Detection Timing
    13. 6.13 Timing Diagrams
    14. 6.14 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 WoL (Wake-on-LAN) Packet Detection
        1. 7.3.1.1 Magic Packet Structure
        2. 7.3.1.2 Magic Packet Example
        3. 7.3.1.3 Wake-on-LAN Configuration and Status
      2. 7.3.2 Start of Frame Detect for IEEE 1588 Time Stamp
        1. 7.3.2.1 SFD Latency Variation and Determinism
          1. 7.3.2.1.1 1000Mb SFD Variation in Master Mode
          2. 7.3.2.1.2 1000Mb SFD Variation in Slave Mode
          3. 7.3.2.1.3 100Mb SFD Variation
      3. 7.3.3 Clock Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 MAC Interfaces
        1. 7.4.1.1 Serial GMII (SGMII)
        2. 7.4.1.2 Reduced GMII (RGMII)
          1. 7.4.1.2.1 1000Mbps Mode Operation
          2. 7.4.1.2.2 1000Mbps Mode Timing
          3. 7.4.1.2.3 10- and 100Mbps Mode
      2. 7.4.2 Serial Management Interface
        1. 7.4.2.1 Extended Address Space Access
          1. 7.4.2.1.1 Write Address Operation
          2. 7.4.2.1.2 Read Address Operation
          3. 7.4.2.1.3 Write (No Post Increment) Operation
          4. 7.4.2.1.4 Read (No Post Increment) Operation
          5. 7.4.2.1.5 Write (Post Increment) Operation
          6. 7.4.2.1.6 Read (Post Increment) Operation
          7. 7.4.2.1.7 Example of Read Operation Using Indirect Register Access
          8. 7.4.2.1.8 Example of Write Operation Using Indirect Register Access
      3. 7.4.3 Auto-Negotiation
        1. 7.4.3.1 Speed and Duplex Selection - Priority Resolution
        2. 7.4.3.2 Master and Slave Resolution
        3. 7.4.3.3 Pause and Asymmetrical Pause Resolution
        4. 7.4.3.4 Next Page Support
        5. 7.4.3.5 Parallel Detection
        6. 7.4.3.6 Restart Auto-Negotiation
        7. 7.4.3.7 Enabling Auto-Negotiation Through Software
        8. 7.4.3.8 Auto-Negotiation Complete Time
        9. 7.4.3.9 Auto-MDIX Resolution
      4. 7.4.4 Loopback Mode
        1. 7.4.4.1 Near-End Loopback
          1. 7.4.4.1.1 MII Loopback
          2. 7.4.4.1.2 PCS Loopback
          3. 7.4.4.1.3 Digital Loopback
          4. 7.4.4.1.4 Analog Loopback
        2. 7.4.4.2 External Loopback
        3. 7.4.4.3 Far-End (Reverse) Loopback
      5. 7.4.5 BIST Configuration
      6. 7.4.6 Cable Diagnostics
        1. 7.4.6.1 TDR
        2. 7.4.6.2 Energy Detect
        3. 7.4.6.3 Fast Link Detect
        4. 7.4.6.4 Speed Optimization
        5. 7.4.6.5 Mirror Mode
        6. 7.4.6.6 Interrupt
        7. 7.4.6.7 IEEE 802.3 Test Modes
    5. 7.5 Programming
      1. 7.5.1 Strap Configuration
      2. 7.5.2 LED Configuration
      3. 7.5.3 LED Operation From 1.8V I/O VDD Supply
      4. 7.5.4 PHY Address Configuration
      5. 7.5.5 Reset Operation
        1. 7.5.5.1 Hardware Reset
        2. 7.5.5.2 IEEE Software Reset
        3. 7.5.5.3 Global Software Reset
        4. 7.5.5.4 Global Software Restart
        5. 7.5.5.5 PCS Restart
      6. 7.5.6 Power-Saving Modes
        1. 7.5.6.1 IEEE Power Down
        2. 7.5.6.2 Deep Power-Down Mode
        3. 7.5.6.3 Active Sleep
        4. 7.5.6.4 Passive Sleep
    6. 7.6 Register Maps
      1. 7.6.1   Basic Mode Control Register (BMCR)
      2. 7.6.2   Basic Mode Status Register (BMSR)
      3. 7.6.3   PHY Identifier Register #1 (PHYIDR1)
      4. 7.6.4   PHY Identifier Register #2 (PHYIDR2)
      5. 7.6.5   Auto-Negotiation Advertisement Register (ANAR)
      6. 7.6.6   Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
      7. 7.6.7   Auto-Negotiate Expansion Register (ANER)
      8. 7.6.8   Auto-Negotiation Next Page Transmit Register (ANNPTR)
      9. 7.6.9   Auto-Negotiation Next Page Receive Register (ANNPRR)
      10. 7.6.10  1000BASE-T Configuration Register (CFG1)
      11. 7.6.11  Status Register 1 (STS1)
      12. 7.6.12  Extended Register Addressing
        1. 7.6.12.1 Register Control Register (REGCR)
        2. 7.6.12.2 Address or Data Register (ADDAR)
      13. 7.6.13  1000BASE-T Status Register (1KSCR)
      14. 7.6.14  PHY Control Register (PHYCR)
      15. 7.6.15  PHY Status Register (PHYSTS)
      16. 7.6.16  MII Interrupt Control Register (MICR)
      17. 7.6.17  Interrupt Status Register (ISR)
      18. 7.6.18  Configuration Register 2 (CFG2)
      19. 7.6.19  Receiver Error Counter Register (RECR)
      20. 7.6.20  BIST Control Register (BISCR)
      21. 7.6.21  Status Register 2 (STS2)
      22. 7.6.22  LED Configuration Register 1 (LEDCR1)
      23. 7.6.23  LED Configuration Register 2 (LEDCR2)
      24. 7.6.24  LED Configuration Register (LEDCR3)
      25. 7.6.25  Configuration Register 3 (CFG3)
      26. 7.6.26  Control Register (CTRL)
      27. 7.6.27  Testmode Channel Control (TMCH_CTRL)
      28. 7.6.28  Robust Auto MDIX Timer Configuration Register (AMDIX_TMR_CFG)
      29. 7.6.29  Fast Link Drop Configuration Register (FLD_CFG)
      30. 7.6.30  Fast Link Drop Threshold Configuration Register (FLD_THR_CFG)
      31. 7.6.31  Configuration Register 4 (CFG4)
      32. 7.6.32  RGMII Control Register (RGMIICTL)
      33. 7.6.33  RGMII Control Register 2 (RGMIICTL2)
      34. 7.6.34  SGMII Auto-Negotiation Status (SGMII_ANEG_STS)
      35. 7.6.35  100BASE-TX Configuration (100CR)
      36. 7.6.36  Viterbi Module Configuration (VTM_CFG)
      37. 7.6.37  Skew FIFO Status (SKEW_FIFO)
      38. 7.6.38  Strap Configuration Status Register 1 (STRAP_STS1)
      39. 7.6.39  Strap Configuration Status Register 2 (STRAP_STS2)
      40. 7.6.40  BIST Control and Status Register 1 (BICSR1)
      41. 7.6.41  BIST Control and Status Register 2 (BICSR2)
      42. 7.6.42  BIST Control and Status Register 3 (BICSR3)
      43. 7.6.43  BIST Control and Status Register 4 (BICSR4)
      44. 7.6.44  Configuration for Receiver's Equalizer (CRE)
      45. 7.6.45  RGMII Delay Control Register (RGMIIDCTL)
      46. 7.6.46  ANA_LD_TXG_FINE_GAINSEL_AB (ALTFGAB)
      47. 7.6.47  ANA_LD_TXG_FINE_GAINSEL_CD (ALTFGCD)
      48. 7.6.48  ANA_LD_FILTER_TUNE_AB (ALFTAB)
      49. 7.6.49  ANA_LD_FILTER_TUNE_CD (ALFTCD)
      50. 7.6.50  Configuration of Receiver's LPF (CRLPF)
      51. 7.6.51  Enable Control of Receiver's Equalizer (ECRE)
      52. 7.6.52  PLL Clock-out Control Register (PLLCTL)
      53. 7.6.53  SGMII Control Register 1 (SGMIICTL1)
      54. 7.6.54  Sync FIFO Control (SYNC_FIFO_CTRL)
      55. 7.6.55  Loopback Configuration Register (LOOPCR)
      56. 7.6.56  DSP Configuration (DSP_CONFIG)
      57. 7.6.57  DSP Feedforward Equalizer Configuration (DSP_FFE_CFG)
      58. 7.6.58  Receive Configuration Register (RXFCFG)
      59. 7.6.59  Receive Status Register (RXFSTS)
      60. 7.6.60  Pattern Match Data Register 1 (RXFPMD1)
      61. 7.6.61  Pattern Match Data Register 2 (RXFPMD2)
      62. 7.6.62  Pattern Match Data Register 3 (RXFPMD3)
      63. 7.6.63  SecureOn Pass Register 2 (RXFSOP1)
      64. 7.6.64  SecureOn Pass Register 2 (RXFSOP2)
      65. 7.6.65  SecureOn Pass Register 3 (RXFSOP3)
      66. 7.6.66  Receive Pattern Register 1 (RXFPAT1)
      67. 7.6.67  Receive Pattern Register 2 (RXFPAT2)
      68. 7.6.68  Receive Pattern Register 3 (RXFPAT3)
      69. 7.6.69  Receive Pattern Register 4 (RXFPAT4)
      70. 7.6.70  Receive Pattern Register 5 (RXFPAT5)
      71. 7.6.71  Receive Pattern Register 6 (RXFPAT6)
      72. 7.6.72  Receive Pattern Register 7 (RXFPAT7)
      73. 7.6.73  Receive Pattern Register 8 (RXFPAT8)
      74. 7.6.74  Receive Pattern Register 9 (RXFPAT9)
      75. 7.6.75  Receive Pattern Register 10 (RXFPAT10)
      76. 7.6.76  Receive Pattern Register 11 (RXFPAT11)
      77. 7.6.77  Receive Pattern Register 12 (RXFPAT12)
      78. 7.6.78  Receive Pattern Register 13 (RXFPAT13)
      79. 7.6.79  Receive Pattern Register 14 (RXFPAT14)
      80. 7.6.80  Receive Pattern Register 15 (RXFPAT15)
      81. 7.6.81  Receive Pattern Register 16 (RXFPAT16)
      82. 7.6.82  Receive Pattern Register 17 (RXFPAT17)
      83. 7.6.83  Receive Pattern Register 18 (RXFPAT18)
      84. 7.6.84  Receive Pattern Register 19 (RXFPAT19)
      85. 7.6.85  Receive Pattern Register 20 (RXFPAT20)
      86. 7.6.86  Receive Pattern Register 21 (RXFPAT21)
      87. 7.6.87  Receive Pattern Register 22 (RXFPAT22)
      88. 7.6.88  Receive Pattern Register 23 (RXFPAT23)
      89. 7.6.89  Receive Pattern Register 24 (RXFPAT24)
      90. 7.6.90  Receive Pattern Register 25 (RXFPAT25)
      91. 7.6.91  Receive Pattern Register 26 (RXFPAT26)
      92. 7.6.92  Receive Pattern Register 27 (RXFPAT27)
      93. 7.6.93  Receive Pattern Register 28 (RXFPAT28)
      94. 7.6.94  Receive Pattern Register 29 (RXFPAT29)
      95. 7.6.95  Receive Pattern Register 30 (RXFPAT30)
      96. 7.6.96  Receive Pattern Register 31 (RXFPAT31)
      97. 7.6.97  Receive Pattern Register 32 (RXFPAT32)
      98. 7.6.98  Receive Pattern Byte Mask Register 1 (RXFPBM1)
      99. 7.6.99  Receive Pattern Byte Mask Register 2 (RXFPBM2)
      100. 7.6.100 Receive Pattern Byte Mask Register 3 (RXFPBM3)
      101. 7.6.101 Receive Pattern Byte Mask Register 4 (RXFPBM4)
      102. 7.6.102 Receive Pattern Control (RXFPATC)
      103. 7.6.103 10M SGMII Configuration (10M_SGMII_CFG)
      104. 7.6.104 I/O Configuration (IO_MUX_CFG)
      105. 7.6.105 GPIO Mux Control Register (GPIO_MUX_CTRL)
      106. 7.6.106 TDR General Configuration Register 1 (TDR_GEN_CFG1)
      107. 7.6.107 TDR Peak Locations Register 1 (TDR_PEAKS_LOC_1)
      108. 7.6.108 TDR Peak Locations Register 2 (TDR_PEAKS_LOC_2)
      109. 7.6.109 TDR Peak Locations Register 3 (TDR_PEAKS_LOC_3)
      110. 7.6.110 TDR Peak Locations Register 4 (TDR_PEAKS_LOC_4)
      111. 7.6.111 TDR Peak Locations Register 5 (TDR_PEAKS_LOC_5)
      112. 7.6.112 TDR Peak Locations Register 6 (TDR_PEAKS_LOC_6)
      113. 7.6.113 TDR Peak Locations Register 7 (TDR_PEAKS_LOC_7)
      114. 7.6.114 TDR Peak Locations Register 8 (TDR_PEAKS_LOC_8)
      115. 7.6.115 TDR Peak Locations Register 9 (TDR_PEAKS_LOC_9)
      116. 7.6.116 TDR Peak Locations Register 10 (TDR_PEAKS_LOC_10)
      117. 7.6.117 TDR Peak Amplitudes Register 1 (TDR_PEAKS_AMP_1)
      118. 7.6.118 TDR Peak Amplitudes Register 2 (TDR_PEAKS_AMP_2)
      119. 7.6.119 TDR Peak Amplitudes Register 3 (TDR_PEAKS_AMP_3)
      120. 7.6.120 TDR Peak Amplitudes Register 4 (TDR_PEAKS_AMP_4)
      121. 7.6.121 TDR Peak Amplitudes Register 5 (TDR_PEAKS_AMP_5)
      122. 7.6.122 TDR Peak Amplitudes Register 6 (TDR_PEAKS_AMP_6)
      123. 7.6.123 TDR Peak Amplitudes Register 7 (TDR_PEAKS_AMP_7)
      124. 7.6.124 TDR Peak Amplitudes Register 8 (TDR_PEAKS_AMP_8)
      125. 7.6.125 TDR Peak Amplitudes Register 9 (TDR_PEAKS_AMP_9)
      126. 7.6.126 TDR Peak Amplitudes Register 10 (TDR_PEAKS_AMP_10)
      127. 7.6.127 TDR General Status (TDR_GEN_STATUS)
      128. 7.6.128 TDR Peak Sign AB (TDR_PEAK_SIGN_A_B)
      129. 7.6.129 TDR Peak Sign CD (TDR_PEAK_SIGN_C_D)
      130. 7.6.130 Programmable Gain Register (PROG_GAIN)
      131. 7.6.131 MMD3 PCS Control Register (MMD3_PCS_CTRL)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Cable Line Driver
        2. 8.2.1.2 Clock In (XI) Recommendation
        3. 8.2.1.3 Crystal Recommendations
        4. 8.2.1.4 Clock Out (CLK_OUT) Phase Noise
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 MAC Interface
          1. 8.2.2.1.1 SGMII Layout Guidelines
          2. 8.2.2.1.2 RGMII Layout Guidelines
        2. 8.2.2.2 Media Dependent Interface (MDI)
          1. 8.2.2.2.1 MDI Layout Guidelines
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Signal Traces
        2. 8.4.1.2 Return Path
        3. 8.4.1.3 Transformer Layout
        4. 8.4.1.4 Metal Pour
        5. 8.4.1.5 PCB Layer Stacking
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
  13. 重要声明
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Data Sheet

DP83867E/IS/CS 稳健型高抗扰性小型 10/100/1000 以太网物理层收发器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

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1 特性

  • 超低延迟，TX < 90ns，RX < 290ns
  • 符合时间敏感网络 (TSN) 标准
  • 低功耗：457mW
  • 超过 8000V IEC 61000-4-2 ESD 保护等级
  • 符合 EN55011 B 类发射标准
  • 在 RX/TX 上提供 16 种可编程 RGMII 延迟模式
  • 集成 MDI 终端电阻器
  • 可编程 MAC 接口端接阻抗
  • WoL（局域网唤醒）数据包检测
  • 25MHz 或 125MHz 同步时钟输出
  • IEEE 1588 时间戳帧起始检测
  • RJ45 镜像模式
  • 完全符合 IEEE 802.3 10BASE-Te、100BASE-TX 和 1000BASE-T 规范
  • 电缆诊断
  • RGMII 和 SGMII MAC 接口选项
  • 可配置 I/O 电压（3.3V、2.5V、1.8V）
  • 快速链路断开模式
  • JTAG 支持

2 应用

  • 电机驱动器
  • 工厂自动化
  • 现场总线支持
  • 工业嵌入式计算
  • 有线和无线通信基础设施
  • 测试和测量
  • 消费类电子产品

3 说明

DP83867 器件是一款稳健型低功耗全功能物理层收发器，它集成了 PMD 子层以支持 10BASE-Te、100BASE-TX 和 1000BASE-T 以太网协议。DP83867 经优化可提供 ESD 保护，超过了 8kV IEC 61000-4-2 标准（直接接触）。

DP83867 旨在轻松实现 10/100/1000Mbps 以太网 LAN。DP83867 通过外部变压器直接连接双绞线介质。此器件通过 RGMII 或嵌入式时钟 SGMII 直接与 MAC 层相连。

DP83867 提供精确时钟同步，其中包括同步以太网时钟输出。DP83867 具有低延迟，并提供 IEEE 1588 帧起始检测。

DP83867 采用低功耗设计，满功率运行时仅消耗 457mW。局域网唤醒可用于降低系统功耗。

封装信息
器件型号 温度 封装 (1) 封装尺寸(2)
DP83867CSRGZ 0°C 至 +70°C RGZ（VQFN，48） 7mm × 7mm
DP83867ISRGZ -40°C 至 +85°C RGZ（VQFN，48） 7mm × 7mm
DP83867ERGZ -40°C 至 +105°C RGZ（VQFN，48） 7mm × 7mm
(1) 有关所有可用封装，请参阅节 11。
(2) 封装尺寸（长 × 宽）为标称值，并包括引脚（如适用）。
DP83867CS DP83867IS DP83867E

4 Device Comparison

Table 4-1 Device Features Comparison
DEVICE MAC TEMPERATURE RANGE TEMPERATURE GRADE
DP83867CSRGZ SGMII/RGMII 0°C 70°C Commercial
DP83867ISRGZ SGMII/RGMII –40°C 85°C Industrial
DP83867ERGZ SGMII/RGMII –40°C 105°C Extended

5 Pin Configuration and Functions

DP83867CS DP83867IS DP83867E RGZ Package48-Pin VQFNTop View Figure 5-1 RGZ Package
48-Pin VQFN
Top View

5.1 Pin Functions

Table 5-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
MAC INTERFACES (SGMII, RGMII)
TX_D325I, PDTRANSMIT DATA Bit 3: This signal carries data from the MAC to the PHY in RGMII mode. This pin is synchronous to the transmit clock GTX_CLK.
TX_D226I, PDTRANSMIT DATA Bit 2: This signal carries data from the MAC to the PHY in RGMII mode. This pin is synchronous to the transmit clock GTX_CLK.
SGMII_SIP27I, PDDifferential SGMII Data Input: This signal carries data from the MAC to the PHY in SGMII mode. This pin is synchronous to the differential SGMII clock input.
This pin can be AC-coupled to the MAC through a 0.1µF capacitor when operating in SGMII mode.
TX_D127I, PDTRANSMIT DATA Bit 1: This signal carries data from the MAC to the PHY in RGMII mode. This pin is synchronous to the transmit clock GTX_CLK.
SGMII_SIN28I, PDDifferential SGMII Data Input: This signal carries data from the MAC to the PHY in SGMII mode. This pin is synchronous to the differential SGMII clock input.
This pin can be AC-coupled to the MAC through a 0.1µF capacitor when operating in SGMII mode.
TX_D028I, PDTRANSMIT DATA Bit 0: This signal carries data from the MAC to the PHY in RGMII mode. This pin is synchronous to the transmit clock GTX_CLK.
GTX_CLK29I, PDRGMII TRANSMIT CLOCK: This continuous clock signal is sourced from the MAC layer to the PHY. Nominal frequency is 125MHz.
RX_CLK32ORGMII RECEIVE CLOCK: Provides the recovered receive clocks for different modes of operation:
2.5MHz in 10Mbps mode.
25MHz in 100Mbps mode.
125MHz in 1000Mbps mode.
SGMII_COP33S, ODifferential SGMII Clock Output: This signal is a continuous 625MHz clock signal driven by the PHY in SGMII mode.
This pin can be AC-coupled to the MAC through a 0.1µF capacitor when operating in SGMII mode.
RX_D033S, O, PDRECEIVE DATA Bit 0: This signal carries data from the PHY to the MAC in RGMII mode. This pin is synchronous to the receive clock RX_CLK.
SGMII_CON34S, O, PDDifferential SGMII Clock Output: This signal is a continuous 625MHz clock signal driven by the MAC in SGMII mode.
This pin can be AC-coupled to the MAC through a 0.1µF capacitor when operating in SGMII mode.
RX_D134O, PDRECEIVE DATA Bit 1: This signal carries data from the PHY to the MAC in RGMII mode. This pin is synchronous to the receive clock RX_CLK.
SGMII_SOP35S, O, PDDifferential SGMII Data Output: This signal carries data from the PHY to the MAC in SGMII mode. This pin is synchronous to the differential SGMII clock output.
This pin can be AC-coupled to the MAC through a 0.1µF capacitor when operating in SGMII mode.
RX_D235S, O, PDRECEIVE DATA Bit 2: This signal carries data from the PHY to the MAC in RGMII mode. This pin is synchronous to the receive clock RX_CLK.
SGMII_SON36S, O, PDDifferential SGMII Data Output: This signal carries data from the PHY to the MAC in SGMII mode. This pin is synchronous to the differential SGMII clock output.
This pin can be AC-coupled to the MAC through a 0.1µF capacitor when operating in SGMII mode.
RX_D336O, PDRECEIVE DATA Bit 3: This signal carries data from the PHY to the MAC in RGMII mode. This pin is synchronous to the receive clock RX_CLK.
TX_CTRL37I, PDTRANSMIT CONTROL: In RGMII mode, This pin combines the transmit enable and the transmit error signals of GMII mode using both clock edges.
RX_CTRL38S, O, PDRECEIVE CONTROL: In RGMII mode, the receive data available and receive error are combined (RXDV_ER) using both rising and falling edges of the receive clock (RX_CLK).
GENERAL-PURPOSE I/O
GPIO_039S, O, PDGeneral-Purpose I/O: This signal provides a multi-function configurable I/O. Refer to the GPIO_MUX_CTRL register for details.
GPIO_140S, O, PDGeneral-Purpose I/O: This signal provides a multi-function configurable I/O. Refer to the GPIO_MUX_CTRL register for details.
MANAGEMENT INTERFACE
MDC16I, PDMANAGEMENT DATA CLOCK: Synchronous clock to the MDIO serial management input and output data. This clock can be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 25MHz and no minimum.
MDIO17I/OMANAGEMENT DATA I/O: Bidirectional management instruction and data signal that can be sourced by the management station or the PHY. This pin requires pullup resistor. The IEEE specified resistor value is 1.5kΩ, but a 2.2kΩ is acceptable.
INT / PWDN44I/O, PUINTERRUPT / POWER DOWN:
The default function of this pin is POWER DOWN.
POWER DOWN: This is an Active Low Input. Asserting this signal low enables the power-down mode of operation. In this mode, the device powers down and consume minimum power. Register access is available through the Management Interface to configure and power up the device.
INTERRUPT: When operating the pin as an interrupt, this pin uses an open-drain architecture. TI recommends using an external 2.2kΩ resistor connected to the VDDIO supply.
RESET
RESET_N43I, PURESET: The active low RESET initializes or reinitializes the DP83867. All internal registers re-initialize to default state upon assertion of RESET. The RESET input must be held low for a minimum of 1µs.
CLOCK INTERFACE
XI15ICRYSTAL/OSCILLATOR INPUT: 25MHz oscillator or crystal input (50ppm)
XO14OCRYSTAL OUTPUT: Second terminal for 25MHz crystal. Must be left floating if a clock oscillator is used.
CLK_OUT18OCLOCK OUTPUT: Output clock
JTAG INTERFACE
JTAG_CLK20I, PUJTAG TEST CLOCK: IEEE 1149.1 Test Clock input, primary clock source for all test logic input and output controlled by the testing entity. Supports a maximum clock frequency of 2.5MHz.
JTAG_TDO21OJTAG TEST DATA OUTPUT: IEEE 1149.1 Test Data Output pin, the most recent test results are scanned out of the device through TDO.
JTAG_TMS22I, PUJTAG TEST MODE SELECT: IEEE 1149.1 Test Mode Select pin, the TMS pin sequences the Tap Controller (16-state FSM) to select the desired test instruction. TI recommends applying 3 clock cycles with JTAG_TMS high to reset the JTAG.
JTAG_TDI23I, PUJTAG TEST DATA INPUT: IEEE 1149.1 Test Data Input pin, test data is scanned into the device through TDI.
LED INTERFACE
LED_245S, I/O, PDLED_2: By default, this pin indicates receive or transmit activity. Additional functionality is configurable through LEDCR1[11:8] register bits.
LED_146S, I/O, PDLED_1: By default, this pin indicates that 1000BASE-T link is established. Additional functionality is configurable through LEDCR1[7:4] register bits.
LED_047S, I/O, PDLED_0: By default, this pin indicates that link is established. Additional functionality is configurable through LEDCR1[3:0] register bits.
MEDIA DEPENDENT INTERFACE
TD_P_A1ADifferential Transmit and Receive Signals
TD_M_A2ADifferential Transmit and Receive Signals
TD_P_B4ADifferential Transmit and Receive Signals
TD_M_B5ADifferential Transmit and Receive Signals
TD_P_C7ADifferential Transmit and Receive Signals
TD_M_C8ADifferential Transmit and Receive Signals
TD_P_D10ADifferential Transmit and Receive Signals
TD_M_D11ADifferential Transmit and Receive Signals
OTHER PINS
RBIAS12ABias Resistor Connection. A 11kΩ ±1% resistor can be connected from RBIAS to GND.
POWER AND GROUND PINS
VDDA2P53, 9P2.5V Analog Supply (±5%). Each pin requires a 1µF and 0.1µF capacitor to GND.
VDD1P06, 24, 31, 42P1V Analog Supply (+15.5%, –5%). Each pin requires a 1µF and 0.1µF capacitor to GND.
VDDA1P813, 48P1.8V Analog Supply (±5%).
No external supply is required for this pin. When unused, no connections can be made to this pin.
For additional power savings, an external 1.8V supply can be connected to these pins. When using an external supply, each pin requires a 1µF and 0.1µF capacitor to GND.
VDDIO19, 30, 41PI/O Power: 1.8V (±5%), 2.5V (±5%) or 3.3V (±5%). Each pin requires a 1µF and 0.1µF capacitor to GND
GNDDie Attach PadPGround
(1)

The definitions below define the functionality of each pin.

  • Type: I Input
  • Type: O Output
  • Type: I/O Input/Output
  • Type: PD, PU Internal Pulldown/Pullup
  • Type: S Configuration Pin
  • Type: P Power or GND
  • Type: A Analog pins

5.2 Unused Pins

DP83867 has internal pullups or pulldowns on most pins. The data sheet details which pins have internal pullups or pulldowns and which pins require external pull resistors.

Even though a device can have internal pullup or pulldown resistors, a good practice is to terminate unused inputs rather than allowing them to float. Floating inputs can result in unstable conditions. Except for VDDA1P8 pins, if the pins are not used then those pins can be left floating. A safer practice to pull an unused input pin high or low with a pullup or pulldown resistor. Another possibility to group together adjacent unused input pins, and as a group pull them up or down using a single resistor.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MINMAXUNIT
Supply voltageVDDA2P5–0.33V
VDDA1P8–0.32.1
VDD1P0–0.31.3
VDDIO3.3V option–0.33.8
2.5V option–0.33
1.8V option–0.32.1
PinsMDI–0.36.5V
MAC interface, MDIO, MDC, GPIO–0.3VDDIO + 0.3
INT/PWDN, RESET–0.3VDDIO + 0.3
JTAG–0.3VDDIO + 0.3
XI (Oscillator Clock Input)–0.32.1V
Storage temperature, Tstg –60 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability.

6.2 ESD Ratings

VALUEUNIT
DP83867ERGZ and DP83867ISRGZ in the RGZ Package
V(ESD)Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)All pins except 1, 2, 4, 5, 7, 8, 10, and 11±2500V
Pins 1, 2, 4, 5, 7, 8, 10, and 11(3)±8000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)±1500
DP83867CSRGZ in the RGZ Package
V(ESD)Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)All pins except 1, 2, 4, 5, 7, 8, 10, and 11±2500V
Pins 1, 2, 4, 5, 7, 8, 10, and 11(3)±6000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)±1500
(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500V HBM is possible with the necessary precautions. Pins listed as ±8V and/or ± 2V can actually have higher performance.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250V CDM is possible with the necessary precautions. Pins listed as ±500V can actually have higher performance.
(3) MDI Pins tested as per IEC 61000-4-2 standards.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
Supply voltage VDDA2P5 2.375 2.5 2.625 V
VDDA1P8 1.71 1.8 1.89
VDD1P0 0.95 1 1.155
VDDIO 3.3V option 3.15 3.3 3.45
2.5V option 2.375 2.5 2.625
1.8V option 1.71 1.8 1.89
Operating junction temperature Commercial (DP83867CSRGZ) 0 90 °C
Industrial (DP83867ISRGZ) –40 105
Extended (DP83867ERGZ) –40 125
Operating free air temperature Commercial (DP83867CSRGZ) 0 25 70 °C
Industrial (DP83867ISRGZ) –40 25 85
Extended (DP83867ERGZ) –40 25 105

 
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