MSP430FR2433 微控制器 (MCU) 是 MSP430™超值系列检测产品组合中的一个器件,该超值系列是 TI 成本最低的 MCU 系列,适用于检测和测量 应用。该架构、FRAM 和集成外设与多种低功耗模式相结合,经过优化延长了采用小型 VQFN 封装 (4mm × 4mm) 应用的 电池寿命。
TI 的 MSP430 超低功耗 FRAM 微控制器平台将独特的嵌入式 FRAM 和全面的超低功耗系统架构相结合,从而使系统设计人员能够在降低能耗的同时提升性能。FRAM 技术兼有 RAM 的低功耗快速写入、灵活性、耐用性和闪存非易失性等特性。
MSP430FR2433 MCU 由一个由各种软、硬件资源组成的生态系统提供支持,并配套提供有参考设计和代码示例,可帮助您快速开展设计。开发套件包括 MSP‑EXP430FR2433LaunchPad™开发套件和 MSP‑TS430RGE24A 24 引脚目标开发板。TI 还提供免费的 MSP430Ware™ 软件,该软件以 Code Composer Studio™ IDE 台式机和云版本组件的形式提供(位于 TI Resource Explorer)。E2E™ 支持论坛还为 MSP430 MCU 提供广泛的在线配套资料、培训和在线支持。
有关完整的模块说明,请参阅《MSP430FR4xx 和 MSP430FR2xx 系列器件用户指南》。
器件型号 | 封装 | 封装尺寸(2) |
---|---|---|
MSP430FR2433IRGE | 超薄四方扁平无引线 (VQFN) (24) | 4mm x 4mm |
MSP430FR2433IYQW | DSBGA (24) | 2.29mm × 2.34mm |
CAUTION
系统级静电放电 (ESD) 保护必须符合器件级 ESD 规范,以防发生电气过载或对数据或代码存储器造成干扰。有关更多信息,请参阅《MSP430 系统级 ESD 注意事项》。
Figure 1-1 给出了功能方框图。
从修订版本 E 更改为修订版本 F
Changes from August 20, 2019 to December 9, 2019
Changes from September 11, 2018 to August 19, 2019
Changes from August 29, 2018 to September 10, 2018
Changes from June 20, 2017 to August 28, 2018
Changes from June 9, 2017 to June 19, 2017
Changes from October 21, 2015 to June 8, 2017
Table 3-1 summarizes the features of the available family members.
DEVICE | PROGRAM FRAM + INFORMATION FRAM (bytes) | SRAM (bytes) | TA0 TO TA3 | eUSCI_A | eUSCI_B | 10-BIT ADC CHANNELS | GPIOs | PACKAGE | |
---|---|---|---|---|---|---|---|---|---|
UART | SPI | ||||||||
MSP430FR2433IRGE | 15360 + 512 | 4096 | 2, 3 × CCR(3)
2, 2 × CCR |
up to 2 | up to 2 | 1 | 8 | 19 | 24 RGE (VQFN) |
MSP430FR2433IYQW | 15360 + 512 | 4096 | 2, 3 × CCR(3)
2, 2 × CCR |
up to 2 | 1 | 1 | 8 | 17 | 24 YQW (DSBGA) |
For information about other devices in this family of products or related products, see the following links.
TI 16-bit and 32-bit microcontrollers
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Companion products for MSP430FR2433
Review products that are frequently purchased or used with this product.
Reference designs for MSP430FR2433
Find reference designs leveraging the best in TI technology – from analog and power management to embedded processors
Figure 4-1 shows the pinout of the 24-pin RGE package.
Figure 4-2 shows the pinout of the 24-pin YQW package.
Table 4-1 lists the attributes of all pins.
PIN NUMBER | SIGNAL NAME(1)(4) | SIGNAL TYPE(2) | BUFFER TYPE(3) | POWER SOURCE(5) | RESET STATE AFTER BOR(6) | |
---|---|---|---|---|---|---|
RGE | YQW | |||||
1 | E1 | RST (RD) | I | LVCMOS | DVCC | OFF |
NMI | I | LVCMOS | DVCC | – | ||
SBWTDIO | I/O | LVCMOS | DVCC | – | ||
2 | D2 | TEST (RD) | I | LVCMOS | DVCC | OFF |
SBWTCK | I | LVCMOS | DVCC | – | ||
3 | D1 | P1.4 (RD) | I/O | LVCMOS | DVCC | OFF |
UCA0TXD | O | LVCMOS | DVCC | – | ||
UCA0SIMO | I/O | LVCMOS | DVCC | – | ||
TA1.2 | I/O | LVCMOS | DVCC | – | ||
TCK | I | LVCMOS | DVCC | – | ||
A4 | I | Analog | DVCC | – | ||
VREF+ | O | Power | DVCC | – | ||
4 | C2 | P1.5 (RD) | I/O | LVCMOS | DVCC | OFF |
UCA0RXD | I | LVCMOS | DVCC | – | ||
UCA0SOMI | I/O | LVCMOS | DVCC | – | ||
TA1.1 | I/O | LVCMOS | DVCC | – | ||
TMS | I | LVCMOS | DVCC | – | ||
A5 | I | Analog | DVCC | – | ||
5 | C3 | P1.6 (RD) | I/O | LVCMOS | DVCC | OFF |
UCA0CLK | I/O | LVCMOS | DVCC | – | ||
TA1CLK | I | LVCMOS | DVCC | – | ||
TDI | I | LVCMOS | DVCC | – | ||
TCLK | I | LVCMOS | DVCC | – | ||
A6 | I | Analog | DVCC | – | ||
6 | B3 | P1.7 (RD) | I/O | LVCMOS | DVCC | OFF |
UCA0STE | I/O | LVCMOS | DVCC | – | ||
SMCLK | O | LVCMOS | DVCC | – | ||
TDO | O | LVCMOS | DVCC | – | ||
A7 | I | Analog | DVCC | – | ||
7 | B1 | P1.0 (RD) | I/O | LVCMOS | DVCC | OFF |
UCB0STE | I/O | LVCMOS | DVCC | – | ||
TA0CLK | I | LVCMOS | DVCC | – | ||
A0 | I | Analog | DVCC | – | ||
Veref+ | I | Power | DVCC | – | ||
8 | A1 | P1.1 (RD) | I/O | LVCMOS | DVCC | OFF |
UCB0CLK | I/O | LVCMOS | DVCC | – | ||
TA0.1 | I/O | LVCMOS | DVCC | – | ||
A1 | I | Analog | DVCC | – | ||
9 | B2 | P1.2 (RD) | I/O | LVCMOS | DVCC | OFF |
UCB0SIMO | I/O | LVCMOS | DVCC | – | ||
UCB0SDA | I/O | LVCMOS | DVCC | – | ||
TA0.2 | I/O | LVCMOS | DVCC | – | ||
A2 | I | Analog | DVCC | – | ||
Veref- | I | Power | DVCC | – | ||
10 | A2 | P1.3 (RD) | I/O | LVCMOS | DVCC | OFF |
UCB0SOMI | I/O | LVCMOS | DVCC | – | ||
UCB0SCL | I/O | LVCMOS | DVCC | – | ||
MCLK | O | LVCMOS | DVCC | – | ||
A3 | I | Analog | DVCC | – | ||
11 | A3 | P2.2 (RD) | I/O | LVCMOS | DVCC | OFF |
ACLK | I/O | LVCMOS | DVCC | – | ||
12 | A4 | P3.0 | I/O | LVCMOS | DVCC | OFF |
13 | A5 | P2.3 | I/O | LVCMOS | DVCC | OFF |
14 | – | P3.1 (RD) | I/O | LVCMOS | DVCC | OFF |
UCA1STE | I/O | LVCMOS | DVCC | – | ||
15 | – | P2.4 (RD) | I/O | LVCMOS | DVCC | OFF |
UCA1CLK | I/O | LVCMOS | DVCC | – | ||
16 | B4 | P2.5 (RD) | I/O | LVCMOS | DVCC | OFF |
UCA1RXD | I | LVCMOS | DVCC | – | ||
UCA1SOMI | I/O | LVCMOS | DVCC | – | ||
17 | B5 | P2.6 (RD) | I/O | LVCMOS | DVCC | OFF |
UCA1TXD | O | LVCMOS | DVCC | – | ||
UCA1SIMO | I/O | LVCMOS | DVCC | – | ||
18 | – | DVSS | P | Power | DVCC | N/A |
– | C5 | NC | – | – | – | – |
19 | E5 | P2.7 | I/O | LVCMOS | DVCC | OFF |
20 | D4 | P3.2 | I/O | LVCMOS | DVCC | OFF |
21 | E4 | P2.0 (RD) | I/O | LVCMOS | DVCC | OFF |
XOUT | O | LVCMOS | DVCC | – | ||
22 | E3 | P2.1 (RD) | I/O | LVCMOS | DVCC | OFF |
XIN | I | LVCMOS | DVCC | – | ||
23 | D3 | DVSS | P | Power | DVCC | N/A |
24 | E2 | DVCC | P | Power | DVCC | N/A |
Table 4-2 describes the device signals.
FUNCTION | SIGNAL NAME | PIN NUMBER | PIN TYPE(1) | DESCRIPTION | |
---|---|---|---|---|---|
RGE | YQW | ||||
ADC | A0 | 7 | B1 | I | Analog input A0 |
A1 | 8 | A1 | I | Analog input A1 | |
A2 | 9 | B2 | I | Analog input A2 | |
A3 | 10 | A2 | I | Analog input A3 | |
A4 | 3 | D1 | I | Analog input A4 | |
A5 | 4 | C2 | I | Analog input A5 | |
A6 | 5 | C3 | I | Analog input A6 | |
A7 | 6 | B3 | I | Analog input A7 | |
Veref+ | 7 | B1 | I | ADC positive reference | |
Veref- | 9 | B2 | I | ADC negative reference | |
Clock | ACLK | 11 | A3 | O | ACLK output |
MCLK | 10 | A2 | O | MCLK output | |
SMCLK | 6 | B3 | O | SMCLK output | |
XIN | 22 | E3 | I | Input terminal for crystal oscillator | |
XOUT | 21 | E4 | O | Output terminal for crystal oscillator | |
Debug | SBWTCK | 2 | D2 | I | Spy-Bi-Wire input clock |
SBWTDIO | 1 | E1 | I/O | Spy-Bi-Wire data input/output | |
TCK | 3 | D1 | I | Test clock | |
TCLK | 5 | C3 | I | Test clock input | |
TDI | 5 | C3 | I | Test data input | |
TDO | 6 | B3 | O | Test data output | |
TEST | 2 | D2 | I | Test Mode pin – selected digital I/O on JTAG pins | |
TMS | 4 | C2 | I | Test mode select | |
GPIO | P1.0 | 7 | B1 | I/O | General-purpose I/O |
P1.1 | 8 | A1 | I/O | General-purpose I/O | |
P1.2 | 9 | B2 | I/O | General-purpose I/O | |
P1.3 | 10 | A2 | I/O | General-purpose I/O | |
P1.4 | 3 | D1 | I/O | General-purpose I/O(2) | |
P1.5 | 4 | C2 | I/O | General-purpose I/O(2) | |
P1.6 | 5 | C3 | I/O | General-purpose I/O(2) | |
P1.7 | 6 | B3 | I/O | General-purpose I/O(2) | |
P2.0 | 21 | E4 | I/O | General-purpose I/O | |
P2.1 | 22 | E3 | I/O | General-purpose I/O | |
P2.2 | 11 | A3 | I/O | General-purpose I/O | |
P2.3 | 13 | A5 | I/O | General-purpose I/O | |
P2.4 | 15 | – | I/O | General-purpose I/O | |
P2.5 | 16 | B4 | I/O | General-purpose I/O | |
P2.6 | 17 | B5 | I/O | General-purpose I/O | |
P2.7 | 19 | E5 | I/O | General-purpose I/O | |
P3.0 | 12 | A4 | I/O | General-purpose I/O | |
P3.1 | 14 | – | I/O | General-purpose I/O | |
P3.2 | 20 | D4 | I/O | General-purpose I/O | |
I2C | UCB0SCL | 10 | A2 | I/O | eUSCI_B0 I2C clock |
UCB0SDA | 9 | B2 | I/O | eUSCI_B0 I2C data | |
Power | DVCC | 24 | E2 | P | Power supply |
DVSS | 23 | D3 | P | Power ground | |
VREF+ | 3 | D1 | P | Output of positive reference voltage with ground as reference | |
SPI | UCA0CLK | 5 | C3 | I/O | eUSCI_A0 SPI clock input/output |
UCA0SIMO | 3 | D1 | I/O | eUSCI_A0 SPI slave in/master out | |
UCA0SOMI | 4 | C2 | I/O | eUSCI_A0 SPI slave out/master in | |
UCA0STE | 6 | B3 | I/O | eUSCI_A0 SPI slave transmit enable | |
UCA1CLK | 15 | – | I/O | eUSCI_A1 SPI clock input/output | |
UCA1SIMO | 17 | B5 | I/O | eUSCI_A1 SPI slave in/master out | |
UCA1SOMI | 16 | B4 | I/O | eUSCI_A1 SPI slave out/master in | |
UCA1STE | 14 | – | I/O | eUSCI_A1 SPI slave transmit enable | |
UCB0CLK | 8 | A1 | I/O | eUSCI_B0 clock input/output | |
UCB0SIMO | 9 | B2 | I/O | eUSCI_B0 SPI slave in/master out | |
UCB0SOMI | 10 | A2 | I/O | eUSCI_B0 SPI slave out/master in | |
UCB0STE | 7 | B1 | I/O | eUSCI_B0 slave transmit enable | |
System | NMI | 1 | E1 | I | Nonmaskable interrupt input |
RST | 1 | E1 | I | Active-low reset input | |
Timer_A | TA0.1 | 8 | A1 | I/O | Timer TA0 CCR1 capture: CCI1A input, compare: Out1 outputs |
TA0.2 | 9 | B2 | I/O | Timer TA0 CCR2 capture: CCI2A input, compare: Out2 outputs | |
TA0CLK | 7 | B1 | I | Timer clock input TACLK for TA0 | |
TA1.1 | 4 | C2 | I/O | Timer TA1 CCR1 capture: CCI1A input, compare: Out1 outputs | |
TA1.2 | 3 | D1 | I/O | Timer TA1 CCR2 capture: CCI2A input, compare: Out2 outputs | |
TA1CLK | 5 | C3 | I | Timer clock input TACLK for TA1 | |
UART | UCA0RXD | 4 | C2 | I | eUSCI_A0 UART receive data |
UCA0TXD | 3 | D1 | O | eUSCI_A0 UART transmit data | |
UCA1RXD | 16 | B4 | I | eUSCI_A1 UART receive data | |
UCA1TXD | 17 | B5 | O | eUSCI_A1 UART transmit data | |
No connection | NC | C4, C5, D5 | I/O | No connection | |
VQFN Pad | VQFN thermal pad | Pad | N/A | VQFN package exposed thermal pad. Connection to VSS is recommended |
Pin multiplexing for these MCUs is controlled by both register settings and operating modes (for example, if the MCU is in test mode). For details of the settings for each pin and schematics of the multiplexed ports, see Section 6.11.
Table 4-3 defines the pin buffer types that are listed in Table 4-1.
BUFFER TYPE (STANDARD) | NOMINAL VOLTAGE | HYSTERESIS | PU OR PD | NOMINAL PU OR PD STRENGTH (µA) | OUTPUT DRIVE STRENGTH (mA) | OTHER CHARACTERISTICS |
---|---|---|---|---|---|---|
LVCMOS | 3.0 V | Y(1) | Programmable | See Section 5.11.4 | See Section 5.11.4 | |
Analog | 3.0 V | N | N/A | N/A | N/A | See analog modules in Section 5 for details. |
Power (DVCC) | 3.0 V | N | N/A | N/A | N/A | SVS enables hysteresis on DVCC. |
Power (AVCC) | 3.0 V | N | N/A | N/A | N/A |