• Menu
  • Product
  • Email
  • PDF
  • Order now

  • MSP430FR2433 混合信号微控制器

    • ZHCSEA0F October   2015  – December 2019 MSP430FR2433

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • MSP430FR2433 混合信号微控制器
  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Types
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1       Absolute Maximum Ratings
    2. 5.2       ESD Ratings
    3. 5.3       Recommended Operating Conditions
    4. 5.4       Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5       Active Mode Supply Current Per MHz
    6. 5.6       Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 5.7       Low-Power Mode (LPM3 and LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8       Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 5.9       Typical Characteristics - Low-Power Mode Supply Currents
    10. Table 5-1 Typical Characteristics – Current Consumption Per Module
    11. 5.10      Thermal Resistance Characteristics
    12. 5.11      Timing and Switching Characteristics
      1. 5.11.1  Power Supply Sequencing
        1. Table 5-2 PMM, SVS and BOR
      2. 5.11.2  Reset Timing
        1. Table 5-3 Wake-up Times From Low-Power Modes and Reset
      3. 5.11.3  Clock Specifications
        1. Table 5-4 XT1 Crystal Oscillator (Low Frequency)
        2. Table 5-5 DCO FLL, Frequency
        3. Table 5-6 DCO Frequency
        4. Table 5-7 REFO
        5. Table 5-8 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        6. Table 5-9 Module Oscillator (MODOSC)
      4. 5.11.4  Digital I/Os
        1. Table 5-10 Digital Inputs
        2. Table 5-11 Digital Outputs
        3. 5.11.4.1   Typical Characteristics – Outputs at 3 V and 2 V
      5. 5.11.5  VREF+ Built-in Reference
        1. Table 5-12 VREF+
      6. 5.11.6  Timer_A
        1. Table 5-13 Timer_A
      7. 5.11.7  eUSCI
        1. Table 5-14 eUSCI (UART Mode) Clock Frequency
        2. Table 5-15 eUSCI (UART Mode)
        3. Table 5-16 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-17 eUSCI (SPI Master Mode)
        5. Table 5-18 eUSCI (SPI Slave Mode)
        6. Table 5-19 eUSCI (I2C Mode)
      8. 5.11.8  ADC
        1. Table 5-20 ADC, Power Supply and Input Range Conditions
        2. Table 5-21 ADC, 10-Bit Timing Parameters
        3. Table 5-22 ADC, 10-Bit Linearity Parameters
      9. 5.11.9  FRAM
        1. Table 5-23 FRAM
      10. 5.11.10 Debug and Emulation
        1. Table 5-24 JTAG, Spy-Bi-Wire Interface
        2. Table 5-25 JTAG, 4-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Standard Interface
    7. 6.7  Spy-Bi-Wire Interface (SBW)
    8. 6.8  FRAM
    9. 6.9  Memory Protection
    10. 6.10 Peripherals
      1. 6.10.1  Power-Management Module (PMM)
      2. 6.10.2  Clock System (CS) and Clock Distribution
      3. 6.10.3  General-Purpose Input/Output Port (I/O)
      4. 6.10.4  Watchdog Timer (WDT)
      5. 6.10.5  System (SYS) Module
      6. 6.10.6  Cyclic Redundancy Check (CRC)
      7. 6.10.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 6.10.8  Timers (Timer0_A3, Timer1_A3, Timer2_A2 and Timer3_A2)
      9. 6.10.9  Hardware Multiplier (MPY)
      10. 6.10.10 Backup Memory (BAKMEM)
      11. 6.10.11 Real-Time Clock (RTC)
      12. 6.10.12 10-Bit Analog-to-Digital Converter (ADC)
      13. 6.10.13 Embedded Emulation Module (EEM)
    11. 6.11 Input/Output Diagrams
      1. 6.11.1 Port P1 Input/Output With Schmitt Trigger
      2. 6.11.2 Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
      3. 6.11.3 Port P2 (P2.3 to P2.7) Input/Output With Schmitt Trigger
      4. 6.11.4 Port P3 (P3.0 to P3.2) Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors
    13. 6.13 Memory
      1. 6.13.1 Memory Organization
      2. 6.13.2 Peripheral File Map
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
  8. 8器件和文档支持
    1. 8.1 入门和后续步骤
    2. 8.2 器件命名规则
    3. 8.3 工具和软件
    4. 8.4 文档支持
    5. 8.5 社区资源
    6. 8.6 商标
    7. 8.7 静电放电警告
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9机械、封装和可订购信息
  10. 重要声明
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

MSP430FR2433 混合信号微控制器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 器件概述

1.1 特性

  • 嵌入式微控制器
    • 16 位 RISC 架构
    • 支持的时钟频率最高可达 16MHz
    • 3.6V 至 1.8V 的宽电源电压范围（最低电源电压受限于 SVS 电平，请参阅 SVS 规格）
  • 优化的超低功耗模式
    • 激活模式：126µA/MHz（典型值）
    • 待机模式：VLO 的电流小于 1µA
    • 采用 32768Hz 晶振的 LPM3.5 实时时钟 (RTC) 计数器：730nA（典型值）
    • 关断电流 (LPM4.5)：16nA（典型值）
  • 高性能模拟
    • 8 通道 10 位模数转换器 (ADC)
      • 1.5V 的内部基准电压
      • 采样与保持 200ksps
  • 增强型串行通信
    • 两个增强型通用串行通信接口 (eUSCI_A) 支持 UART、IrDA 和 SPI
    • 一个 eUSCI (eUSCI_B) 支持 SPI 和 I2C
  • 智能数字外设
    • 四个 16 位计时器
      • 两个计时器，每个计时器具有三个捕捉/比较寄存器 (Timer_A3)
      • 两个计时器，每个计时器具有两个捕捉/比较寄存器 (Timer_A2)
    • 一个仅用作计数器的 16 位 RTC
    • 16 位循环冗余校验 (CRC)
  • 低功耗铁电 RAM (FRAM)
    • 容量高达 15.5KB 的非易失性存储器
    • 内置错误修正码 (ECC)
    • 可配置的写保护
    • 对程序、常量和存储的统一存储
    • 耐写次数达 1015 次
    • 抗辐射和非磁性
    • FRAM 与 SRAM 之比高达 4：1
  • 时钟系统 (CS)
    • 片上 32kHz RC 振荡器 (REFO)
    • 带有锁频环 (FLL) 的片上 16MHz 数控振荡器 (DCO)
      • 室温下的精度为 ±1%（具有片上基准）
    • 片上超低频 10kHz 振荡器 (VLO)
    • 片上高频调制振荡器 (MODOSC)
    • 外部 32kHz 晶振 (LFXT)
    • 可编程 MCLK 预分频器（1 至 128）
    • 通过可编程预分频器（1、2、4 或 8）从 MCLK 获得的 SMCLK
  • 通用输入/输出和引脚功能
    • 共计 19 个 I/O（采用 VQFN-24 封装）
    • 16 个中断引脚（P1 和 P2）可以将 MCU 从低功耗模式下唤醒
  • 开发工具和软件
    • 开发工具
      • LaunchPad™开发套件 (MSP‑EXP430FR2433)
      • 目标开发板 (MSP‑TS430RGE24A)
  • 系列成员（另请参阅器件比较）
    • MSP430FR2433：15KB 程序 FRAM、512B 信息 FRAM、4KB RAM
  • 封装选项
    • 24 引脚：VQFN (RGE)
    • 24 引脚：DSBGA (YQW)

1.2 应用

  • 小型工业传感器
  • 低功耗医疗、健康和健身器材
  • 电子门锁
  • 能量收集

1.3 说明

MSP430FR2433 微控制器 (MCU) 是 MSP430™超值系列检测产品组合中的一个器件，该超值系列是 TI 成本最低的 MCU 系列，适用于检测和测量 应用。该架构、FRAM 和集成外设与多种低功耗模式相结合，经过优化延长了采用小型 VQFN 封装 (4mm × 4mm) 应用的 电池寿命。

TI 的 MSP430 超低功耗 FRAM 微控制器平台将独特的嵌入式 FRAM 和全面的超低功耗系统架构相结合，从而使系统设计人员能够在降低能耗的同时提升性能。FRAM 技术兼有 RAM 的低功耗快速写入、灵活性、耐用性和闪存非易失性等特性。

MSP430FR2433 MCU 由一个由各种软、硬件资源组成的生态系统提供支持，并配套提供有参考设计和代码示例，可帮助您快速开展设计。开发套件包括 MSP‑EXP430FR2433LaunchPad™开发套件和 MSP‑TS430RGE24A 24 引脚目标开发板。TI 还提供免费的 MSP430Ware™ 软件，该软件以 Code Composer Studio™ IDE 台式机和云版本组件的形式提供（位于 TI Resource Explorer）。E2E™ 支持论坛还为 MSP430 MCU 提供广泛的在线配套资料、培训和在线支持。

有关完整的模块说明，请参阅《MSP430FR4xx 和 MSP430FR2xx 系列器件用户指南》。

器件信息(1)

器件型号 封装 封装尺寸(2)
MSP430FR2433IRGE 超薄四方扁平无引线 (VQFN) (24) 4mm x 4mm
MSP430FR2433IYQW DSBGA (24) 2.29mm × 2.34mm
(1) 要获得最新的产品、封装和订购信息，请参见封装选项附录（Section 9），或者访问德州仪器 (TI) 网站 www.ti.com.cn。
(2) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸，请参见机械数据（Section 9中）。

CAUTION

系统级静电放电 (ESD) 保护必须符合器件级 ESD 规范，以防发生电气过载或对数据或代码存储器造成干扰。有关更多信息，请参阅《MSP430 系统级 ESD 注意事项》。

1.4 功能方框图

Figure 1-1 给出了功能方框图。

MSP430FR2433 msp430fr2433-functional-block-diagram.gifFigure 1-1 功能框图
  • MCU 的主电源对 DVCC 和 DVSS 分别为数字模块和模拟模块供电。推荐的旁路电容和去耦电容分别为 4.7μF 至 10μF 和 0.1μF，精度为 ±5%。
  • P1 和 P2 特有引脚中断功能，可将 MCU 从所有 LPM 唤醒（包括 LPM3.5 和 LPM4）。
  • 每个 Timer_A3 具有 3 个捕捉/比较寄存器，不过仅 CCR1 和 CCR2 从外部连接。CCR0 寄存器仅用于内部周期时序和生成中断。
  • 每个 Timer_A2 具有两个捕捉/比较寄存器，仅 CCR1 具有比较/捕捉功能。CCR0 寄存器仅用于内部周期时序和生成中断。
  • 在 LPM3.5 模式下，RTC 模块可在其他外设停止工作的情况下继续工作。

2 修订历史记录

从修订版本 E 更改为修订版本 F

Changes from August 20, 2019 to December 9, 2019

  • Changed the note that begins "Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset..." in Section 5.3, Recommended Operating ConditionsGo
  • Added the note that begins "TI recommends that power to the DVCC pin must not exceed the limits..." in Section 5.3, Recommended Operating ConditionsGo
  • Changed the note that begins "A capacitor tolerance of ±20% or better is required..." in Section 5.3, Recommended Operating ConditionsGo
  • Changed the note that begins "Requires external capacitors at both terminals..." in Table 5-4, XT1 Crystal Oscillator (Low Frequency)Go
  • Added the t(int) parameter in Table 5-10, Digital InputsGo
  • Corrected the test conditions for the RI,MUX parameter in Table 5-20, ADC, Power Supply and Input Range ConditionsGo
  • Added the note that begins "tSample = ln(2n+1) × τ ..." in Table 5-21, ADC, 10-Bit Timing ParametersGo
  • Changed the CRC covered end address to 0x1AF5 in note (1) in Table 6-22, Device DescriptorsGo

Changes from September 11, 2018 to August 19, 2019

  • Changed the parameter symbol from RI to RI,MUX in Table 5-20 , ADC, Power Supply and Input Range ConditionsGo
  • Added RI,Misc TYP value of 34 kΩ in Table 5-20 , ADC, Power Supply and Input Range ConditionsGo
  • Added formula for RI calculation in Table 5-21 , ADC, 10-Bit Timing ParametersGo
  • Removed the description of "±3°C" in table note that starts "The device descriptor structure ..." of Table 5-22, ADC, 10-Bit Linearity ParametersGo
  • Corrected bitfield from IRDSEL to IRDSSEL in Section 6.10.8, Timers (Timer0_A3, Timer1_A3, Timer2_A2 and Timer3_A2), in the description that starts "The interconnection of Timer0_A3 and ..."Go
  • Corrected the ADCINCHx column heading in Table 6-15, ADC Channel ConnectionsGo
  • Corrected the ADCSHSx column heading in Table 6-16, ADC Trigger Signal ConnectionsGo
  • Added P1SELC information in Table 6-32, Port P1, P2 Registers (Base Address: 0200h)Go
  • Added P2SELC information in Table 6-32, Port P1, P2 Registers (Base Address: 0200h)Go
  • Added P3SELC information in Table 6-33, Port P3 Registers (Base Address: 0220h)Go

Changes from August 29, 2018 to September 10, 2018

  • Removed SYNC signal (not supported) from Figure 4-1, 32-Pin RHB Package (Top View)Go
  • Combined two YQW pinout figures into one, and removed SYNC signal (not supported) in Figure 4-2, 24-Pin YQW Package (Top and Bottom Views)Go
  • Removed SYNC signal (not supported) from figure and table in Section 6.11.2, Port P2 (P2.0 to P2.2) Input/Output With Schmitt TriggerGo

Changes from June 20, 2017 to August 28, 2018

  • Updated Section 3.1, Related ProductsGo
  • Corrected description of pin C5 on YQW package (changed from DVSS to NC) in Table 4-1, Pin AttributesGo
  • Corrected typos in the pin numbers of P2.3,5,6 in the RGE package in Table 4-2Go
  • Corrected typos in the pin numbers of UCA1RXD and UCA1TXD in the RGE package in Table 4-2Go
  • Changed description of NC pins from "No internal connection" to "No connection" in Table 4-2, Signal DescriptionsGo
  • Corrected package type in VQFN row (changed from QFN to VQFN) in Table 4-2, Signal DescriptionsGo
  • Changed HBM limit to ±1000 V and CDM limit to ±250 V in Section 5.2, ESD RatingsGo
  • Added note to VSVSH- and VSVSH+ parameters in Table 5-2, PMM, SVS and BORGo
  • Moved "FRAM access time error" to "System Reset" row and added ACCTEIFG to interrupt flag column in Table 6-2, Interrupt Sources, Flags, and VectorsGo
  • Corrected the offset for P2SEL1 in Table 6-32, Port P1, P2 Registers (Base Address: 0200h)Go
  • 更新了Section 8.2器件命名规则 中的文本和图Go

Changes from June 9, 2017 to June 19, 2017

  • 更正了Figure 1-1（功能框图）中的 FRAM 和 RAM 大小Go

Changes from October 21, 2015 to June 8, 2017

  • 向开头为“宽电源电压范围...”的列表项添加了说明Go
  • 在Section 1.1，特性 中的“封装选项”列表中添加了 DSBGA (YQW) 封装Go
  • 在器件信息 表（位于Section 1.3“说明”中）中添加了 DSBGA (YQW) 封装选项Go
  • Added row for MSP430FR2433IYQW to Table 3-1, Device ComparisonGo
  • Added Section 3.1, Related ProductsGo
  • Added DSBGA (YQW) package to Table 4-1, Pin AttributesGo
  • Added DSBGA (YQW) package to Table 4-2, Signal DescriptionsGo
  • Added row for VQFN thermal padGo
  • Removed FRAM reflow noteGo
  • In the note that starts "Low-power mode 3, VLO, excludes SVS test conditions...", changed "fXT1 = 0 Hz" to "fXT1 = 32768 Hz"Go
  • Added DSBGA (YQW) package and changed notes for Section 5.10, Thermal Resistance CharacteristicsGo
  • Added note that starts "The VLO clock frequency is reduced by 15%..."Go
  • Removed ADCDIV from the formula for the TYP value in the second row of the tCONVERT parameter in Table 5-21, ADC, 10-Bit Timing Parameters (removed because ADCCLK is after division)Go
  • Added note to "Clock" in Table 6-1, Operating ModesGo
  • Added note that starts "XT1CLK and VLOCLK can be active during LPM4..."Go
  • Add description of blank device detectionGo
  • Corrected description in Section 6.10.10, Backup Memory (BKMEM)Go
  • Changed the paragraph that starts "Quickly switching digital signals and ..." in Section 7.2.1.2, Design RequirementsGo
  • 更新了Figure 8-1，器件命名规则Go
  • 将先前的开发工具支持 部分替换为Section 8.3“工具和软件”Go
  • 更新了Section 8.4“文档支持”的格式和内容Go

3 Device Comparison

Table 3-1 summarizes the features of the available family members.

Table 3-1 Device Comparison(1)(2)

DEVICE PROGRAM FRAM + INFORMATION FRAM (bytes) SRAM (bytes) TA0 TO TA3 eUSCI_A eUSCI_B 10-BIT ADC CHANNELS GPIOs PACKAGE
UART SPI
MSP430FR2433IRGE 15360 + 512 4096 2, 3 × CCR(3)
2, 2 × CCR		 up to 2 up to 2 1 8 19 24 RGE (VQFN)
MSP430FR2433IYQW 15360 + 512 4096 2, 3 × CCR(3)
2, 2 × CCR		 up to 2 1 1 8 17 24 YQW (DSBGA)
(1) For the most current package and ordering information, see the Package Option Addendum in Section 9, or see the TI website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging.
(3) A CCR register is a configurable register that provides internal and external capture or compare inputs, or internal and external PWM outputs.

3.1 Related Products

For information about other devices in this family of products or related products, see the following links.

TI 16-bit and 32-bit microcontrollers

High-performance, low-power solutions to enable the autonomous future

Products for MSP430 ultra-low-power sensing & measurement MCUs

One platform. One ecosystem. Endless possibilities.

Companion products for MSP430FR2433

Review products that are frequently purchased or used with this product.

Reference designs for MSP430FR2433

Find reference designs leveraging the best in TI technology – from analog and power management to embedded processors

4 Terminal Configuration and Functions

4.1 Pin Diagram

Figure 4-1 shows the pinout of the 24-pin RGE package.

MSP430FR2433 SLAS942_PINOUT_QFN24C.gifFigure 4-1 24-Pin RGE Package (Top View)

Figure 4-2 shows the pinout of the 24-pin YQW package.

MSP430FR2433 SLAS942_PINOUT_DSBGA_YQW-no-cap-combined-view.gifFigure 4-2 24-Pin YQW Package (Top and Bottom Views)

4.2 Pin Attributes

Table 4-1 lists the attributes of all pins.

Table 4-1 Pin Attributes

PIN NUMBER SIGNAL NAME(1)(4) SIGNAL TYPE(2) BUFFER TYPE(3) POWER SOURCE(5) RESET STATE AFTER BOR(6)
RGE YQW
1 E1 RST (RD) I LVCMOS DVCC OFF
NMI I LVCMOS DVCC –
SBWTDIO I/O LVCMOS DVCC –
2 D2 TEST (RD) I LVCMOS DVCC OFF
SBWTCK I LVCMOS DVCC –
3 D1 P1.4 (RD) I/O LVCMOS DVCC OFF
UCA0TXD O LVCMOS DVCC –
UCA0SIMO I/O LVCMOS DVCC –
TA1.2 I/O LVCMOS DVCC –
TCK I LVCMOS DVCC –
A4 I Analog DVCC –
VREF+ O Power DVCC –
4 C2 P1.5 (RD) I/O LVCMOS DVCC OFF
UCA0RXD I LVCMOS DVCC –
UCA0SOMI I/O LVCMOS DVCC –
TA1.1 I/O LVCMOS DVCC –
TMS I LVCMOS DVCC –
A5 I Analog DVCC –
5 C3 P1.6 (RD) I/O LVCMOS DVCC OFF
UCA0CLK I/O LVCMOS DVCC –
TA1CLK I LVCMOS DVCC –
TDI I LVCMOS DVCC –
TCLK I LVCMOS DVCC –
A6 I Analog DVCC –
6 B3 P1.7 (RD) I/O LVCMOS DVCC OFF
UCA0STE I/O LVCMOS DVCC –
SMCLK O LVCMOS DVCC –
TDO O LVCMOS DVCC –
A7 I Analog DVCC –
7 B1 P1.0 (RD) I/O LVCMOS DVCC OFF
UCB0STE I/O LVCMOS DVCC –
TA0CLK I LVCMOS DVCC –
A0 I Analog DVCC –
Veref+ I Power DVCC –
8 A1 P1.1 (RD) I/O LVCMOS DVCC OFF
UCB0CLK I/O LVCMOS DVCC –
TA0.1 I/O LVCMOS DVCC –
A1 I Analog DVCC –
9 B2 P1.2 (RD) I/O LVCMOS DVCC OFF
UCB0SIMO I/O LVCMOS DVCC –
UCB0SDA I/O LVCMOS DVCC –
TA0.2 I/O LVCMOS DVCC –
A2 I Analog DVCC –
Veref- I Power DVCC –
10 A2 P1.3 (RD) I/O LVCMOS DVCC OFF
UCB0SOMI I/O LVCMOS DVCC –
UCB0SCL I/O LVCMOS DVCC –
MCLK O LVCMOS DVCC –
A3 I Analog DVCC –
11 A3 P2.2 (RD) I/O LVCMOS DVCC OFF
ACLK I/O LVCMOS DVCC –
12 A4 P3.0 I/O LVCMOS DVCC OFF
13 A5 P2.3 I/O LVCMOS DVCC OFF
14 – P3.1 (RD) I/O LVCMOS DVCC OFF
UCA1STE I/O LVCMOS DVCC –
15 – P2.4 (RD) I/O LVCMOS DVCC OFF
UCA1CLK I/O LVCMOS DVCC –
16 B4 P2.5 (RD) I/O LVCMOS DVCC OFF
UCA1RXD I LVCMOS DVCC –
UCA1SOMI I/O LVCMOS DVCC –
17 B5 P2.6 (RD) I/O LVCMOS DVCC OFF
UCA1TXD O LVCMOS DVCC –
UCA1SIMO I/O LVCMOS DVCC –
18 – DVSS P Power DVCC N/A
– C5 NC – – – –
19 E5 P2.7 I/O LVCMOS DVCC OFF
20 D4 P3.2 I/O LVCMOS DVCC OFF
21 E4 P2.0 (RD) I/O LVCMOS DVCC OFF
XOUT O LVCMOS DVCC –
22 E3 P2.1 (RD) I/O LVCMOS DVCC OFF
XIN I LVCMOS DVCC –
23 D3 DVSS P Power DVCC N/A
24 E2 DVCC P Power DVCC N/A
(1) Signals names with (RD) denote the reset default pin name.
(2) Signal Types: I = Input, O = Output, I/O = Input or Output
(3) Buffer Types: LVCMOS, Analog, or Power (see Table 4-3)
(4) To determine the pin mux encodings for each pin, see Section 6.11, Input/Output Diagrams.
(5) The power source shown in this table is the I/O power source, which may differ from the module power source.
(6) Reset States:
OFF = High-impedance with Schmitt trigger and pullup or pulldown (if available) disabled
N/A = Not applicable

4.3 Signal Descriptions

Table 4-2 describes the device signals.

Table 4-2 Signal Descriptions

FUNCTION SIGNAL NAME PIN NUMBER PIN TYPE(1) DESCRIPTION
RGE YQW
ADC A0 7 B1 I Analog input A0
A1 8 A1 I Analog input A1
A2 9 B2 I Analog input A2
A3 10 A2 I Analog input A3
A4 3 D1 I Analog input A4
A5 4 C2 I Analog input A5
A6 5 C3 I Analog input A6
A7 6 B3 I Analog input A7
Veref+ 7 B1 I ADC positive reference
Veref- 9 B2 I ADC negative reference
Clock ACLK 11 A3 O ACLK output
MCLK 10 A2 O MCLK output
SMCLK 6 B3 O SMCLK output
XIN 22 E3 I Input terminal for crystal oscillator
XOUT 21 E4 O Output terminal for crystal oscillator
Debug SBWTCK 2 D2 I Spy-Bi-Wire input clock
SBWTDIO 1 E1 I/O Spy-Bi-Wire data input/output
TCK 3 D1 I Test clock
TCLK 5 C3 I Test clock input
TDI 5 C3 I Test data input
TDO 6 B3 O Test data output
TEST 2 D2 I Test Mode pin – selected digital I/O on JTAG pins
TMS 4 C2 I Test mode select
GPIO P1.0 7 B1 I/O General-purpose I/O
P1.1 8 A1 I/O General-purpose I/O
P1.2 9 B2 I/O General-purpose I/O
P1.3 10 A2 I/O General-purpose I/O
P1.4 3 D1 I/O General-purpose I/O(2)
P1.5 4 C2 I/O General-purpose I/O(2)
P1.6 5 C3 I/O General-purpose I/O(2)
P1.7 6 B3 I/O General-purpose I/O(2)
P2.0 21 E4 I/O General-purpose I/O
P2.1 22 E3 I/O General-purpose I/O
P2.2 11 A3 I/O General-purpose I/O
P2.3 13 A5 I/O General-purpose I/O
P2.4 15 – I/O General-purpose I/O
P2.5 16 B4 I/O General-purpose I/O
P2.6 17 B5 I/O General-purpose I/O
P2.7 19 E5 I/O General-purpose I/O
P3.0 12 A4 I/O General-purpose I/O
P3.1 14 – I/O General-purpose I/O
P3.2 20 D4 I/O General-purpose I/O
I2C UCB0SCL 10 A2 I/O eUSCI_B0 I2C clock
UCB0SDA 9 B2 I/O eUSCI_B0 I2C data
Power DVCC 24 E2 P Power supply
DVSS 23 D3 P Power ground
VREF+ 3 D1 P Output of positive reference voltage with ground as reference
SPI UCA0CLK 5 C3 I/O eUSCI_A0 SPI clock input/output
UCA0SIMO 3 D1 I/O eUSCI_A0 SPI slave in/master out
UCA0SOMI 4 C2 I/O eUSCI_A0 SPI slave out/master in
UCA0STE 6 B3 I/O eUSCI_A0 SPI slave transmit enable
UCA1CLK 15 – I/O eUSCI_A1 SPI clock input/output
UCA1SIMO 17 B5 I/O eUSCI_A1 SPI slave in/master out
UCA1SOMI 16 B4 I/O eUSCI_A1 SPI slave out/master in
UCA1STE 14 – I/O eUSCI_A1 SPI slave transmit enable
UCB0CLK 8 A1 I/O eUSCI_B0 clock input/output
UCB0SIMO 9 B2 I/O eUSCI_B0 SPI slave in/master out
UCB0SOMI 10 A2 I/O eUSCI_B0 SPI slave out/master in
UCB0STE 7 B1 I/O eUSCI_B0 slave transmit enable
System NMI 1 E1 I Nonmaskable interrupt input
RST 1 E1 I Active-low reset input
Timer_A TA0.1 8 A1 I/O Timer TA0 CCR1 capture: CCI1A input, compare: Out1 outputs
TA0.2 9 B2 I/O Timer TA0 CCR2 capture: CCI2A input, compare: Out2 outputs
TA0CLK 7 B1 I Timer clock input TACLK for TA0
TA1.1 4 C2 I/O Timer TA1 CCR1 capture: CCI1A input, compare: Out1 outputs
TA1.2 3 D1 I/O Timer TA1 CCR2 capture: CCI2A input, compare: Out2 outputs
TA1CLK 5 C3 I Timer clock input TACLK for TA1
UART UCA0RXD 4 C2 I eUSCI_A0 UART receive data
UCA0TXD 3 D1 O eUSCI_A0 UART transmit data
UCA1RXD 16 B4 I eUSCI_A1 UART receive data
UCA1TXD 17 B5 O eUSCI_A1 UART transmit data
No connection NC C4, C5, D5 I/O No connection
VQFN Pad VQFN thermal pad Pad N/A VQFN package exposed thermal pad. Connection to VSS is recommended
(1) Pin Types: I = Input, O = Output, I/O = Input or Output, P = Power
(2) Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to prevent collisions.

4.4 Pin Multiplexing

Pin multiplexing for these MCUs is controlled by both register settings and operating modes (for example, if the MCU is in test mode). For details of the settings for each pin and schematics of the multiplexed ports, see Section 6.11.

4.5 Buffer Types

Table 4-3 defines the pin buffer types that are listed in Table 4-1.

Table 4-3 Buffer Types

BUFFER TYPE (STANDARD) NOMINAL VOLTAGE HYSTERESIS PU OR PD NOMINAL PU OR PD STRENGTH (µA) OUTPUT DRIVE STRENGTH (mA) OTHER CHARACTERISTICS
LVCMOS 3.0 V Y(1) Programmable See Section 5.11.4 See Section 5.11.4
Analog 3.0 V N N/A N/A N/A See analog modules in Section 5 for details.
Power (DVCC) 3.0 V N N/A N/A N/A SVS enables hysteresis on DVCC.
Power (AVCC) 3.0 V N N/A N/A N/A
(1) Only for input pins.

 
Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale