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  • MSP430FR698x(1)、MSP430FR598x(1) 混合信号微控制器

    • ZHCSCU7D June   2014  – August 2018 MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR59891 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891

      PRODUCTION DATA.  

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  • MSP430FR698x(1)、MSP430FR598x(1) 混合信号微控制器
  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions – MSP430FR698x and MSP430FR698x1
      2. Table 4-2 Signal Descriptions – MSP430FR598x and MSP430FR598x1
    3. 4.3 Pin Multiplexing
    4. 4.4 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics, Active Mode Supply Currents
    6. 5.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    10. 5.10 Typical Characteristics, Low-Power Mode Supply Currents
    11. 5.11 Typical Characteristics, Current Consumption per Module
    12. 5.12 Thermal Resistance Characteristics
    13. 5.13 Timing and Switching Characteristics
      1. 5.13.1 Power Supply Sequencing
        1. Table 5-1 Brownout and Device Reset Power Ramp Requirements
        2. Table 5-2 SVS
      2. 5.13.2 Reset Timing
        1. Table 5-3 Reset Input
      3. 5.13.3 Clock Specifications
        1. Table 5-4 Low-Frequency Crystal Oscillator, LFXT
        2. Table 5-5 High-Frequency Crystal Oscillator, HFXT
        3. Table 5-6 DCO
        4. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-8 Module Oscillator (MODOSC)
      4. 5.13.4 Wake-up Characteristics
        1. Table 5-9  Wake-up Times From Low-Power Modes and Reset
        2. Table 5-10 Typical Wake-up Charge
        3. 5.13.4.1   Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 5.13.5 Peripherals
        1. 5.13.5.1 Digital I/Os
          1. Table 5-11 Digital Inputs
          2. Table 5-12 Digital Outputs
          3. 5.13.5.1.1 Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
          4. Table 5-13 Pin-Oscillator Frequency, Ports Px
          5. 5.13.5.1.2 Typical Characteristics, Pin-Oscillator Frequency
        2. 5.13.5.2 Timer_A and Timer_B
          1. Table 5-14 Timer_A
          2. Table 5-15 Timer_B
        3. 5.13.5.3 eUSCI
          1. Table 5-16 eUSCI (UART Mode) Clock Frequency
          2. Table 5-17 eUSCI (UART Mode)
          3. Table 5-18 eUSCI (SPI Master Mode) Clock Frequency
          4. Table 5-19 eUSCI (SPI Master Mode)
          5. Table 5-20 eUSCI (SPI Slave Mode)
          6. Table 5-21 eUSCI (I2C Mode)
        4. 5.13.5.4 LCD Controller
          1. Table 5-22 LCD_C, Recommended Operating Conditions
          2. Table 5-23 LCD_C Electrical Characteristics
        5. 5.13.5.5 ADC
          1. Table 5-24 12-Bit ADC, Power Supply and Input Range Conditions
          2. Table 5-25 12-Bit ADC, Timing Parameters
          3. Table 5-26 12-Bit ADC, Linearity Parameters With External Reference
          4. Table 5-27 12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference
          5. Table 5-28 12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference
          6. Table 5-29 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference
          7. Table 5-30 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference
          8. Table 5-31 12-Bit ADC, Dynamic Performance With 32.768-kHz Clock
          9. Table 5-32 12-Bit ADC, Temperature Sensor and Built-In V1/2
          10. Table 5-33 12-Bit ADC, External Reference
        6. 5.13.5.6 Reference
          1. Table 5-34 REF, Built-In Reference
        7. 5.13.5.7 Comparator
          1. Table 5-35 Comparator_E
        8. 5.13.5.8 Scan Interface
          1. Table 5-36 Extended Scan Interface, Port Drive, Port Timing
          2. Table 5-37 Extended Scan Interface, Sample Capacitor/Ri Timing
          3. Table 5-38 Extended Scan Interface, VCC/2 Generator
          4. Table 5-39 Extended Scan Interface, 12-Bit DAC
          5. Table 5-40 Extended Scan Interface, Comparator
          6. Table 5-41 Extended Scan Interface, ESICLK Oscillator and TSM Clock Signals
        9. 5.13.5.9 FRAM Controller
          1. Table 5-42 FRAM
      6. 5.13.6 Emulation and Debug
        1. Table 5-43 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
      1. 6.3.1 Peripherals in Low-Power Modes
        1. 6.3.1.1 Idle Currents of Peripherals in LPM3 and LPM4
    4. 6.4  Interrupt Vector Table and Signatures
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  FRAM
    8. 6.8  RAM
    9. 6.9  Tiny RAM
    10. 6.10 Memory Protection Unit Including IP Encapsulation
    11. 6.11 Peripherals
      1. 6.11.1  Digital I/O
      2. 6.11.2  Oscillator and Clock System (CS)
      3. 6.11.3  Power-Management Module (PMM)
      4. 6.11.4  Hardware Multiplier (MPY)
      5. 6.11.5  Real-Time Clock (RTC_C)
      6. 6.11.6  Watchdog Timer (WDT_A)
      7. 6.11.7  System Module (SYS)
      8. 6.11.8  DMA Controller
      9. 6.11.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 6.11.10 Extended Scan Interface (ESI)
      11. 6.11.11 Timer_A TA0, Timer_A TA1
      12. 6.11.12 Timer_A TA2
      13. 6.11.13 Timer_A TA3
      14. 6.11.14 Timer_B TB0
      15. 6.11.15 ADC12_B
      16. 6.11.16 Comparator_E
      17. 6.11.17 CRC16
      18. 6.11.18 CRC32
      19. 6.11.19 AES256 Accelerator
      20. 6.11.20 True Random Seed
      21. 6.11.21 Shared Reference (REF_A)
      22. 6.11.22 LCD_C
      23. 6.11.23 Embedded Emulation
        1. 6.11.23.1 Embedded Emulation Module (EEM)
        2. 6.11.23.2 EnergyTrace++™ Technology
      24. 6.11.24 Input/Output Diagrams
        1. 6.11.24.1  Digital I/O Functionality – Ports P1 to P10
        2. 6.11.24.2  Capacitive Touch Functionality Ports P1 to P10 and PJ
        3. 6.11.24.3  Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger
        4. 6.11.24.4  Port P1 (P1.4 to P1.7) Input/Output With Schmitt Trigger
        5. 6.11.24.5  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
        6. 6.11.24.6  Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
        7. 6.11.24.7  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
        8. 6.11.24.8  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
        9. 6.11.24.9  Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
        10. 6.11.24.10 Port P6 (P6.0 to P6.6) Input/Output With Schmitt Trigger
        11. 6.11.24.11 Port P6 (P6.7) Input/Output With Schmitt Trigger
        12. 6.11.24.12 Port P7 (P7.0 to P7.7) Input/Output With Schmitt Trigger
        13. 6.11.24.13 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
        14. 6.11.24.14 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger
        15. 6.11.24.15 Port P9 (P9.0 to P9.3) Input/Output With Schmitt Trigger
        16. 6.11.24.16 Port P9 (P9.4 to P9.7) Input/Output With Schmitt Trigger
        17. 6.11.24.17 Port P10 (P10.0 to P10.2) Input/Output With Schmitt Trigger
        18. 6.11.24.18 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
        19. 6.11.24.19 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
        20. 6.11.24.20 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors (TLV)
    13. 6.13 Memory
      1. 6.13.1 Peripheral File Map
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC12_B Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Detailed Design Procedure
        4. 7.2.1.4 Layout Guidelines
      2. 7.2.2 LCD_C Peripheral
        1. 7.2.2.1 Partial Schematic
        2. 7.2.2.2 Design Requirements
        3. 7.2.2.3 Detailed Design Procedure
        4. 7.2.2.4 Layout Guidelines
      3. 7.2.3 Extended Scan Interface (ESI) Peripheral
        1. 7.2.3.1 Overview
        2. 7.2.3.2 Design Requirements
        3. 7.2.3.3 Detailed Design Procedure
        4. 7.2.3.4 Layout Guidelines
  8. 8器件和文档支持
    1. 8.1  入门和后续步骤
    2. 8.2  器件命名规则
    3. 8.3  工具和软件
    4. 8.4  文档支持
    5. 8.5  相关链接
    6. 8.6  社区资源
    7. 8.7  商标
    8. 8.8  静电放电警告
    9. 8.9  出口管制提示
    10. 8.10 Glossary
  9. 9机械、封装和可订购信息
  10. 重要声明
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DATA SHEET

MSP430FR698x(1)、MSP430FR598x(1) 混合信号微控制器

本资源的原文使用英文撰写。 为方便起见,TI 提供了译文;由于翻译过程中可能使用了自动化工具,TI 不保证译文的准确性。 为确认准确性,请务必访问 ti.com 参考最新的英文版本(控制文档)。

1 器件概述

1.1 特性

  • 嵌入式微控制器
    • 高达 16MHz 时钟频率的 16 位 RISC 架构
    • 3.6V 至 1.8V 的宽电源电压范围(最低电源电压受限于 SVS 电平,请参阅 SVS 规格)
  • 经优化的超低功耗模式
    • 工作模式:大约 100µA/MHz
    • 待机(具有低功率低频内部时钟源 (VLO) 的 LPM3):0.4µA(典型值)
    • 实时时钟 (RTC) (LPM3.5):0.35µA(典型值) (1)
    • 关断 (LPM4.5):0.02µA(典型值)
    • 1. 实时时钟 (RTC) 由 3.7pF 晶振计时。
  • 超低功耗铁电 RAM (FRAM)
    • 高达 128KB 的非易失性存储器
    • 超低功耗写入
    • 125ns 每个字的快速写入(4ms 内写入 64KB)
    • 统一标准存储器 = 单个空间内的程序 + 数据 + 存储
    • 1015 写入周期持久性
    • 抗辐射和非磁性
  • 智能数字外设
    • 32 位硬件乘法器 (MPY)
    • 三通道内部直接存储器存取 (DMA)
    • 带有日历和和报警功能的 RTC
    • 5 个 16 位计时器,每个计时器具有多达 7 个捕捉/比较寄存器
    • 16 位和 32 位循环冗余校验器(CRC16、CRC32)
  • 高性能模拟
    • 扩展扫描接口 (ESI),可用于在后台测量水容积、热量和气体体积
    • 16 通道模拟比较器
    • 12 位模数转换器 (ADC),具有内部基准和采样保持以及多达 16 个外部输入通道
    • 具有高达 320 段对比度控制的集成 LCD 驱动器
  • 多功能输入/输出端口
    • 所有 P1 至 P10 以及 PJ 引脚均支持电容式触控功能,无需外部组件
    • 可每位、每字节和每字访问(成对访问)
    • 可通过 P1、P2、P3 和 P4 端口从 LPM 唤醒,边沿可选
    • 所有端口上可编程上拉和下拉
  • 代码安全性和加密
    • 128 位或 256 位 AES 安全加密和解密协处理器
    • 针对随机数生成算法的真随机种子
  • 增强型串行通信
    • eUSCI_A0 和 eUSCI_A1 支持:
      • 支持自动波特率侦测的通用异步收发器 (UART)
      • IrDA 编码和解码
      • SPI
    • eUSCI_B0 和 eUSCI_B1 均支持:
      • 支持多从设备寻址的 I2C
      • SPI
    • 硬件 UART 和 I2C 引导加载程序 (BSL)
  • 灵活时钟系统
    • 具有 10 个可选厂家调整频率的定频数控振荡器 (DCO)
    • 低功率低频内部时钟源 (VLO)
    • 32kHz 晶振 (LFXT)
    • 高频晶振 (HFXT)
  • 开发工具和软件
    • 自由的专业开发环境 具有 EnergyTrace++™技术
    • 实验和开发套件
  • 系列产品成员
    • 器件比较 总结了器件型号和可用封装类型
  • 要获得完整的模块说明,请参见《MSP430FR58xx、MSP430FR59xx 和 MSP430FR6xx 系列用户指南》

1.2 应用

  • 水表
  • 热量计
  • 热量分配表
  • 便携式医疗仪表
  • 数据日志
  • 有关 TI Designs,请参阅扩展扫描接口 (ESI) 外设

1.3 说明

MSP430™超低功耗 (ULP) FRAM 平台将独特的嵌入式 FRAM 和整体超低功耗系统架构组合在一起,从而使得创新人员能够以较少的能源预算增加性能。FRAM 技术以低很多的功耗将 SRAM 的速度、灵活性和耐久性与闪存的稳定性和可靠性组合在一起。

MSP430 ULP FRAM 产品系列由多种采用 FRAM 、ULP 16 位 MSP430 CPU 的器件和智能外设组成,可适用于各种 应用。ULP 架构具有七种低功耗模式,这些模式都经过优化,可在能源受限的应用中实现较长的 电池寿命。

器件信息(1)

器件型号 封装 封装尺寸(2)
MSP430FR6989IPZ LQFP (100) 14mm x 14mm
MSP430FR6989IPN LQFP (80) 12mm x 12mm
MSP430FR5989IPM LQFP (64) 10mm x 10mm
MSP430FR5989IRGC VQFN (64) 9mm x 9mm
(1) 要获得最新的产品、封装和订购信息,请参见封装选项附录(Section 9),或者访问德州仪器 (TI) 网站 www.ti.com.cn。
(2) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸,请参见机械数据(Section 9)。

1.4 功能方框图

Figure 1-1 和Figure 1-2 显示 功能方框图。

MSP430FR6989 MSP430FR69891 MSP430FR6988 MSP430FR6987 MSP430FR5989 MSP430FR59891 MSP430FR5988 MSP430FR5987 MSP430FR5986 fbd_slas789.gifFigure 1-1 功能方框图 – MSP430FR698x、MSP430FR698x1
MSP430FR6989 MSP430FR69891 MSP430FR6988 MSP430FR6987 MSP430FR5989 MSP430FR59891 MSP430FR5988 MSP430FR5987 MSP430FR5986 fbd_slas789-lcd.gifFigure 1-2 功能方框图 – MSP430FR598x、MSP430FR598x1

2 修订历史记录

Changes from March 10, 2017 to August 29, 2018

  • Updated Section 3.1, Related ProductsGo
  • Added note (1) to Table 5-2, SVSGo
  • Changed capacitor value from 4.7 µF to 470 nF in Figure 7-5, ADC12_B Grounding and Noise ConsiderationsGo
  • Changed capacitor value from 4.7 µF to 470 nF in the last paragraph of Section 7.2.1.2, Design RequirementsGo
  • 更新了 Section 8.2,器件命名规则 中的文本和图Go

3 Device Comparison

Table 3-1 and Table 3-2 summarize the available family members.

Table 3-1 Device Comparison (With UART BSL)(1)(2)

DEVICE FRAM
(KB)
SRAM
(KB)
CLOCK SYSTEM Timer_A (3) Timer_B (4) eUSCI AES ADC12_B LCD_C I/O PACKAGE
A(7) B(8)
MSP430FR6989 128 2 DCO
HFXT
LFXT
3, 3 (5)
2, 5 (6)
7 2 2 yes 12 ext
16 ext
240 seg
320 seg
63
83
80 PN
100 PZ
MSP430FR6988 96 2 DCO
HFXT
LFXT
3, 3 (5)
2, 5 (6)
7 2 2 yes 12 ext
16 ext
240 seg
320 seg
63
83
80 PN
100 PZ
MSP430FR6987 64 2 DCO
HFXT
LFXT
3, 3 (5)
2, 5 (6)
7 2 2 yes 12 ext
16 ext
240 seg
320 seg
63
83
80 PN
100 PZ
MSP430FR5989 128 2 DCO
HFXT
LFXT
3, 3 (5)
2, 5 (6)
7 2 2 yes 12 ext N/A 48 64 PM
64 RGC
MSP430FR5988 96 2 DCO
HFXT
LFXT
3, 3 (5)
2, 5 (6)
7 2 2 yes 12 ext N/A 48 64 PM
64 RGC
MSP430FR5987 64 2 DCO
HFXT
LFXT
3, 3 (5)
2, 5 (6)
7 2 2 yes 12 ext N/A 48 64 PM
64 RGC
MSP430FR5986 48 2 DCO
HFXT
LFXT
3, 3 (5)
2, 5 (6)
7 2 2 yes 12 ext N/A 48 64 PM
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/package.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(5) Timer_A TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.
(6) Timer_A TA2 and TA3 provide only internal capture/compare inputs and only internal PWM outputs (if any).
(7) eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.
(8) eUSCI_B supports I2C with multiple slave addresses and SPI.

Table 3-2 Device Comparison (With I2C BSL) (1)(2)

DEVICE FRAM
(KB)
SRAM
(KB)
CLOCK SYSTEM Timer_A (3) Timer_B (4) eUSCI AES ADC12_B LCD_C I/O PACKAGE TYPE
A(7) B(8)
MSP430FR69891 128 2 DCO
HFXT
LFXT
3, 3 (5)
2, 5 (6)
7 2 2 yes 12 ext
16 ext
240 seg
320 seg
63
83
80 PN
100 PZ
MSP430FR59891 128 2 DCO
HFXT
LFXT
3, 3 (5)
2, 5 (6)
7 2 2 yes 12 ext N/A 48 64 PM
64 RGC

3.1 Related Products

For information about other devices in this family of products or related products, see the following links.

    TI 16-bit and 32-bit microcontrollers

    High-performance, low-power solutions to enable the autonomous future

    Products for MSP430 ultra-low-power sensing and measurement microcontrollers

    One platform. One ecosystem. Endless possibilities.

    Products for MSP430 ultrasonic and performance sensing microcontrollers

    Ultra-low-power single-chip MCUs with integrated sensing peripherals

    Companion products for MSP430FR6989

    Review products that are frequently purchased or used with this product.

    Reference designs for MSP430FR6989

    The TI Designs Reference Design Library is a robust reference design library that spans analog, embedded processor, and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download designs at ti.com/tidesigns.

4 Terminal Configuration and Functions

4.1 Pin Diagrams

Figure 4-1 shows the pinout of the 100-pin PZ package for the MSP430FR698x and MSP430FR698x1 MCUs.

MSP430FR6989 MSP430FR69891 MSP430FR6988 MSP430FR6987 MSP430FR5989 MSP430FR59891 MSP430FR5988 MSP430FR5987 MSP430FR5986 MSP430FR698x_100QFP.gif

NOTE:

On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX

NOTE:

On devices with I2C BSL: P1.6: BSLSDA; P1.7: BSLSCL
Figure 4-1 100-Pin PZ Package (Top View) – MSP430FR698x and MSP430FR698x1

Figure 4-2 shows the pinout of the 80-pin PN package for the MSP430FR698x and MSP430FR698x1 MCUs.

MSP430FR6989 MSP430FR69891 MSP430FR6988 MSP430FR6987 MSP430FR5989 MSP430FR59891 MSP430FR5988 MSP430FR5987 MSP430FR5986 MSP430FR698x_80QFP.gif

NOTE:

On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX

NOTE:

On devices with I2C BSL: P1.6: BSLSDA; P1.7: BSLSCL
Figure 4-2 80-Pin PN Package (Top View) – MSP430FR698x and MSP430FR698x1

Figure 4-3 shows the pinout of the 64-pin PM and RGC packages for the MSP430FR598x and MSP430FR598x1 MCUs.

MSP430FR6989 MSP430FR69891 MSP430FR6988 MSP430FR6987 MSP430FR5989 MSP430FR59891 MSP430FR5988 MSP430FR5987 MSP430FR5986 MSP430F588x_64QFP.gif

NOTE:

TI recommends connecting the RGC package pad to VSS.

NOTE:

On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX

NOTE:

On devices with I2C BSL: P1.6: BSLSDA; P1.7: BSLSCL
Figure 4-3 64-Pin PM or RGC Package (Top View) – MSP430FR598x and MSP430FR598x1

 

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