UCC27532-Q1 2.5A 和 5A、35VMAX VDD FET 和 IGBT 单栅极驱动器
- ZHCSC00C December 2013 – September 2024 UCC27532-Q1
  
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UCC27532-Q1 2.5A 和 5A、35V_MAX VDD FET 和 IGBT 单栅极驱动器

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1 特性

符合汽车应用要求
具有符合 AEC-Q100 标准的下列特性：
- 器件温度 1 级
低成本栅极驱动器（为驱动 FET 和 IGBT 提供理想解决方案）
分立式晶体管对驱动器的出色替代产品（提供与控制器的简便对接）
CMOS 兼容输入逻辑阈值（在 VDD 大于 18V 时变为固定值）
分离输出可实现独立接通和关闭调节
通过固定 TTL 兼容型阈值启用
在 18V VDD 下具有 2.5A 的高峰值驱动拉电流和 5A 的峰值驱动灌电流
从 10V 到高达 35V 的宽 VDD 范围
输入引脚可承受低于接地电压且高达 -5V 的直流电压
当输入悬空时或在 VDD UVLO 期间，输出保持低电平
短暂传播延迟（典型值为 17ns）
快速上升和下降时间
（1800pF 负载时的典型值分别为 15ns 和 7ns）
欠压锁定（UVLO）
用作高侧或低侧驱动器（如果采用适当的偏置和信号隔离设计）
低成本、节省空间的 6 引脚 DBV (SOT-23) 封装
工作温度范围为 –40°C 至 140°C

2 应用

3 说明

UCC27532-Q1 器件是一款单通道、高速、栅极驱动器，此驱动器可借助于高达 2.5A 拉电流和 5A 灌电流（非对称驱动）峰值电流来有效驱动金属氧化物半导体场效应晶体管 (MOSFET) 和 IGBT 电源开关。非对称驱动中的强劲灌电流能力提升了抗寄生米勒开通效应的能力。UCC27532-Q1 器件还特有一个分离输出配置，在此配置中栅极驱动电流从 OUTH 引脚拉出并从 OUTL 引脚被灌入。这个引脚安排使得用户能够分别在 OUTH 和 OUTL 引脚采用独立的接通和关闭电阻器，并且能很轻易地控制开关的转换率。

此驱动器具有轨到轨驱动功能以及 17ns（典型值）的极小传播延迟。

封装信息

器件型号	封装⁽¹⁾	本体尺寸（标称值）
UCC27532-Q1	DBV（SOT-23，6）	2.90mm × 1.60mm

(1) 有关所有可用封装，请参阅节 13。

无需负偏压即可驱动 IGBT

4 说明（续）

UCC27532-Q1 器件具有 CMOS 输入阈值，此阈值在 VDD 低于或等于 18V 时介于比 VDD 高 55% 的电压值与比 VDD 低 45% 的电压值范围内。当 VDD 高于 18V 时，输入阈值保持在最大水平上。

此驱动器具有一个 EN 引脚，此引脚有一个固定的 TTL 兼容阈值。EN 被内部上拉；将 EN 下拉为低电平禁用驱动器，而将其保持打开可提供正常运行。EN 引脚可被用作一个额外输入，其性能与 IN 引脚一样。

将驱动器的输入引脚保持开状态将把输出保持为低电平。驱动器的逻辑行为如时序图、输入/输出逻辑真值表和节 8.2 所示。

VDD 引脚上的内部电路提供一个欠压闭锁功能，此功能在 VDD 电源电压处于运行范围内之前将输出保持为低电平。

UCC27532-Q1 驱动器采用 6 引脚标准 SOT-23 (DBV) 封装。此器件在 -40°C 至 140°C 的宽运行温度范围内运行。

5 Pin Configuration and Functions

UCC27532-Q1 DBV Package6-Pin SOT-23
Top View

Figure 5-1 DBV Package6-Pin SOT-23 Top View

Table 5-1 Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
EN	1	I	Enable (Pull EN to GND to disable output, pull it high or leave it open to enable the output)
GND	4	—	Ground (all signals are referenced to this node)
IN	2	I	Driver noninverting input (CMOS threshold)
OUTL	5	O	5-A sink current output of driver
OUTH	6	O	2.5-A source current output of driver
VDD	3	I	Bias supply input

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾⁽³⁾

			MIN	MAX	UNIT
Supply voltage range	VDD		–0.3	35	V
	Continuous	OUTH, OUTL	–0.3	VDD +0.3
	Continuous	IN, EN	–2	VDD +0.3
	Pulse	OUTH, OUTL (200 ns)	–5	27	V
	Pulse	IN, EN (1.5 µs)	–6.5	27	V
Operating virtual junction temperature range, T_J			–40	150	°C
Lead temperature	Soldering, 10 seconds			300
Lead temperature	Reflow			260
Storage temperature range, T_stg			–65	150

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See Packaging Section of the data sheet for thermal limitations and considerations of packages.

(3) These devices are sensitive to electrostatic discharge; follow proper device handling procedures.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±750	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	NOM	MAX	UNIT
Supply voltage range, VDD	10	18	32	V
Operating junction temperature range	–40		140	°C
Input voltage, IN	–5		25	V
Enable, EN	–5		25	V

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		UCC27532-Q1	UNIT
		DBV (SOT-23)
		6 PINS
R_θJA	Junction-to-ambient thermal resistance	178.3	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	109.7	°C/W
R_θJB	Junction-to-board thermal resistance	28.3	°C/W
ψ_JT	Junction-to-top characterization parameter	14.7	°C/W
ψ_JB	Junction-to-board characterization parameter	27.8	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Unless otherwise noted, VDD = 18 V, T_A = T_J = –40°C to 140°C, IN switching from 0 V to VDD, 1-µF capacitor from VDD to GND, ƒ = 100 kHz. Currents are positive into and negative out of the specified terminal. OUTH and OUTL are tied together. Typical condition specifications are at 25°C.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
BIAS CURRENTS
I_DDoff	Startup current, VDD = 7	IN, EN = VDD	100	240	350	μA
I_DDoff	Startup current, VDD = 7	IN, EN = GND	100	250	350	μA
UNDERVOLTAGE LOCKOUT (UVLO)
V_ON	Supply start threshold		8	8.9	9.8	V
V_OFF	Minimum operating voltage after supply start		7.3	8.2	9.1	V
V_{DD_H}	Supply voltage hysteresis			0.7		V
INPUT (IN)
V_{IN_H}	Input signal high threshold	VDD = 16V, Output high	8.8	9.4	10	V
V_{IN_L}	Input signal low threshold	VDD = 16V, Output low	6.7	7.3	7.9	V
V_{IN_HYS}	Input signal hysteresis	VDD = 16V		2.1		V
ENABLE (EN)
V_{EN_H}	Enable signal high threshold	VDD = 16V, Output high	1.7	1.9	2.1	V
V_{EN_L}	Enable signal low threshold	VDD = 16V, Output low	0.8	1	1.2	V
V_{EN_HYS}	Enable signal hysteresis	VDD = 16V		0.9		V
OUTPUTS (OUTH/OUTL)
I_SRC/SNK	Source peak current (OUTH)/ sink peak current (OUTL)⁽¹⁾	C_LOAD = 0.22 µF, ƒ = 1 kHz		–2.5 / 5		A
V_OH	OUTH, high voltage	I_OUTH = –10 mA	VDD –0.2	VDD –0.12	VDD –0.07	V
V_OL	OUTL, low voltage	I_OUTL = 100 mA		0.065	0.125	V
R_OH	OUTH, pullup resistance⁽¹⁾	T_A = 25°C, I_OUT = -10 mA	11	12	12.5	Ω
R_OH	OUTH, pullup resistance⁽¹⁾	T_A = –40°C to 140°C, I_OUT = -10 mA	7	12	20	Ω
R_OL	OUTL, pulldown resistance	T_A = 25°C, I_OUT = 100 mA	0.45	0.65	0.85	Ω
R_OL	OUTL, pulldown resistance	T_A = –40°C to 140°C, I_OUT = 100 mA	0.3	0.65	1.25	Ω

(1) Output pullup resistance here is a DC measurement that measures resistance of PMOS structure only, not N-channel structure. The effective dynamic pullup resistance is 3 × R_OL.

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
t_R	Rise time	C_LOAD = 1.8 nF	15		ns
t_F	Fall time	C_LOAD = 1.8 nF	7		ns
t_D1	Turnon propagation delay	C_LOAD = 1.8 nF, IN = 0 V to VDD	17	26	ns
t_D2	Turnoff propagation delay	C_LOAD = 1.8 nF, IN = VDD to 0 V	17	26	ns

(1) Ensured by design and tested during characterization. Not production tested.

(2) See Figure 6-1.

UCC27532-Q1 Timing Diagram: (OUTH Tied To
OUTL) Input = IN, Output = OUT (EN = VDD) Or Input = EN, Output = OUT (IN =
VDD)

Figure 6-1 Timing Diagram: (OUTH Tied To OUTL) Input = IN, Output = OUT (EN = VDD) Or Input = EN, Output = OUT (IN = VDD)

6.7 Typical Characteristics

Figure 6-2 Rise Time vs Supply Voltage

UCC27532-Q1 Propagation Delay vs Supply Voltage

Figure 6-4 Propagation Delay vs Supply Voltage

UCC27532-Q1 Start-Up Current vs Temperature

Figure 6-6 Start-Up Current vs Temperature

UCC27532-Q1 UVLO Threshold Voltage vs Temperature

Figure 6-8 UVLO Threshold Voltage vs Temperature

UCC27532-Q1 Enable Threshold vs Temperature

Figure 6-10 Enable Threshold vs Temperature

UCC27532-Q1 Output Pulldown Resistance vs Temperature

Figure 6-12 Output Pulldown Resistance vs Temperature

UCC27532-Q1 Input-to-Output Propagation Delay vs Temperature

Figure 6-14 Input-to-Output Propagation Delay vs Temperature

Figure 6-16 Fall Time vs Temperature

Figure 6-18 Rise Time vs Supply Voltage

Figure 6-3 Fall Time vs Supply Voltage

UCC27532-Q1 Operating Supply Current vs Frequency

Figure 6-5 Operating Supply Current vs Frequency

UCC27532-Q1 Operating Supply Current vs Temperature (Output Switching)

Figure 6-7 Operating Supply Current vs Temperature (Output Switching)

UCC27532-Q1 Input Threshold vs Temperature

Figure 6-9 Input Threshold vs Temperature

UCC27532-Q1 Output Pullup Resistance vs Temperature

Figure 6-11 Output Pullup Resistance vs Temperature

UCC27532-Q1 Operating Supply Current vs Temperature (Output In DC ON and OFF Condition)

Figure 6-13 Operating Supply Current vs Temperature (Output In DC ON and OFF Condition)

Figure 6-15 Rise Time vs Temperature

UCC27532-Q1 Operating Supply Current vs Supply Voltage (Output Switching)

Figure 6-17 Operating Supply Current vs Supply Voltage (Output Switching)

Figure 6-19 Fall Time vs Supply Voltage

7 Detailed Description

7.1 Overview

High-current gate driver devices are required in switching power applications for a variety of reasons. To enable fast switching of power devices and reduce associated switching power losses, a powerful gate driver can be used between the PWM output of controllers or signal isolation devices and the gates of the power semiconductor devices. Further, gate drivers are indispensable when having the PWM controller directly drive the gates of the switching devices is not feasible. This situation is often encountered because the PWM signal from a digital controller or signal isolation device is often a 3.3-V or 5-V logic signal which is not capable of effectively turning on a power switch. A level shifting circuitry is required to boost the logic-level signal to the gate-drive voltage in order to fully turn on the power device and minimize conduction losses. Traditional buffer drive circuits based on NPN and PNP bipolar (or P-channel and N-channel MOSFET) transistors in totem-pole arrangement, being emitter-follower configurations, prove inadequate for this function because these circuits lack level-shifting capability and low-drive voltage protection. Gate drivers effectively combine both the level-shifting, buffer drive, and UVLO functions. Gate drivers have other uses such as minimizing the effect of switching noise by locating the high-current driver physically close to the power switch, driving gate-drive transformers, controlling floating power device gates, and reducing power dissipation and thermal stress in controllers by moving gate charge power losses into itself.

The UCC27532-Q1 device is very flexible in this role with a strong current-drive capability and wide supply-voltage range up to 35 V. These features allow the driver to be used in 12-V Si MOSFET applications, 20-V and –5-V (relative to source) SiC FET applications, 15-V and –15-V (relative to emitter) IGBT applications, and many others. As a single-channel driver, the UCC27532-Q1 device can be used as a low-side or high-side driver. To use the device as a low-side driver, the switch ground is typically the system ground so it can be connected directly to the gate driver. To use as a high-side driver with a floating return node, however, signal isolation is required from the controller as well as an isolated bias to the UCC27532-Q1 device. Alternatively, in a high-side drive configuration the UCC27532-Q1 device can be tied directly to the controller signal and biased with a non-isolated supply. However, in this configuration the outputs of the UCC27532-Q1 device must drive a pulse transformer which then drives the power-switch to work properly with the floating source and emitter of the power switch. Further, having the ability to control turnon and turnoff speeds independently with both the OUTH and OUTL pins ensures optimum efficiency while maintaining system reliability. These requirements coupled with the need for low propagation delays and availability in compact, low-inductance packages with good thermal capability makes gate driver devices such as the UCC27532-Q1 device extremely important components in switching power combining benefits of high-performance, low cost, component count and board-space reduction, and simplified system design.

Table 7-1 UCC27532-Q1 Features and Benefits

FEATURE	BENEFIT
High source and sink current capability, 2.5 A and 5 A (asymmetrical).	High current capability offers flexibility in employing UCC27532-Q1 device device to drive a variety of power switching devices at varying speeds.
Low 17 ns (typ) propagation delay.	Extremely low pulse transmission distortion.
Wide VDD operating range of 10 V to 32 V.	Flexibility in system design.
	Can be used in split-rail systems such as driving IGBTs with both positive and negative (relative to Emitter) supplies.
	Optimal for many SiC FETs.
VDD UVLO protection.	Outputs are held Low in UVLO condition, which ensures predictable, glitch-free operation at power up and power down.
VDD UVLO protection.	High UVLO of 8.9 V typical ensures that power switch is not on in high-impedance state which could result in high power dissipation or even failures.
Outputs held low when input pin (IN) in floating condition.	Safety feature, especially useful in passing abnormal condition tests during safety certification
Split output structure (OUTH, OUTL).	Allows independent optimization of turnon and turnoff speeds using series gate resistors.
Strong sink current (5 A) and low pulldown impedance (0.65 Ω).	High immunity to high dV/dt Miller turnon events.
CMOS compatible input threshold logic with wide 2.1-V hysteresis.	Excellent noise immunity.
Input capable of withstanding –6.5 V.	Enhanced signal reliability in noisy environments that experience ground bounce on the gate driver.