ZHCSBE5D August   2013  – June 2025 TPS62090-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Enable and Disable (EN)
      2. 6.3.2  Soft Start (SS) and Hiccup Current Limit During Start-Up
      3. 6.3.3  Voltage Tracking (SS)
      4. 6.3.4  Short-Circuit Protection (Hiccup Mode)
      5. 6.3.5  Output Discharge Function
      6. 6.3.6  Power Good Output (PG)
      7. 6.3.7  Frequency Set Pin (FREQ)
      8. 6.3.8  Undervoltage Lockout (UVLO)
      9. 6.3.9  Thermal Shutdown
      10. 6.3.10 Charge Pump (CP, CN)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Pulse Width Modulation Operation
      2. 6.4.2 Power Save Mode Operation
      3. 6.4.3 Low-Dropout Operation (100% Duty Cycle)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Inductor Selection
        2. 7.2.2.2 Input and Output Capacitor Selection
        3. 7.2.2.3 Setting the Output Voltage
      3. 7.2.3 Application Curves
    3. 7.3 System Examples
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 器件和文档支持
    1. 8.1 器件支持
      1. 8.1.1 第三方产品免责声明
    2. 8.2 文档支持
      1. 8.2.1 相关文档
    3. 8.3 接收文档更新通知
    4. 8.4 支持资源
    5. 8.5 商标
    6. 8.6 静电放电警告
    7. 8.7 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

TPS62090-Q1 RGT Package16-Pin QFN With Exposed Thermal Pad(Top View)
The exposed thermal pad is connected to AGND.
Figure 4-1 RGT Package16-Pin QFN With Exposed Thermal Pad(Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
AGND 6 — Analog ground
AVIN 10 I Bias supply input voltage pin
CN 8 I/O Internal charge-pump flying capacitor. Connect a 10-nF capacitor between CP and CN.
CP 7 I/O Internal charge-pump flying capacitor. Connect a 10-nF capacitor between CP and CN.
EN 13 I Device enable. To enable the device this pin must be pulled high. Pulling this pin low disables the device. This pin has a pulldown resistor of typically 400 kΩ, which is active when EN is low.
Exposed Thermal Pad — — The exposed thermal pad is connected to AGND. This pin must be soldered for mechanical reliability.
FB 5 I Feedback pin of the device.
For the adjustable version, connect a resistor divider to set the output voltage.
FREQ 3 I This pin selects the switching frequency of the device. FREQ = Low sets the typical switching frequency to 2.8 MHz. FREQ = High sets the typical switching frequency to 1.4 MHz. This pin has an active pulldown resistor of typically 400 kΩ and can be left floating for 2.8-MHz operation.
PG 4 O Power good open-drain output. This pin is high impedance if the output voltage is within regulation. This pin is pulled low if the output is below the nominal value. The pullup resistor can not be connected to any voltage higher than the input voltage of the device.
PGND 14, 15 — Power ground connection
PVIN 11, 12 I Power supply input voltage pin
SS 9 I Soft-start control pin. A capacitor is connected to this pin and sets the soft-start time. Leaving this pin floating sets the minimum start-up time.
SW 1, 2 I/O Switch pin of the power stage
VOS 16 I Output voltage sense pin. This pin must be connected to the output voltage.
(1) I = input, O = output