TPA6133A2 138mW DirectPath™ 立体声耳机放大器
1 特性
2 应用范围
- 移动电话
- 音频耳机
- 笔记本电脑
- 高保真应用
3 说明
TPA6133A2是一款具有 GPIO 控制的立体声 DirectPath™ 头戴式耳机放大器。 TPA6133A2具有最小的静态流耗，IDD的典型值为 4.2mA，这使得它非常适合于便携式应用。 GPIO 控制使得此器件能够被置于低功耗关断模式中。
TPA6133A2是一款信噪比为 93dB 的高保真放大器。 大于 100dB 的 PSRR 可在不影响收听体验的同时实现与电池的直接连接。 12 μVrms 的输出噪声（典型值输入信噪比 (A-weighted)）在默声周期期间提供最小的噪声背景。 可配置差分输入和高 CMRR 可在一个移动器件所处的嘈杂环境中实现最大噪声抑制。
- 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
4 简化应用示意图
5 修订历史记录
Changes from A Revision (August 2014) to B Revision
- Changed "PIN QFN" To: "NUMBER" in the Pin Functions tableGo
- Added a NOTE to the Applications and Implementation section Go
- Added new paragraph to the Application Information sectionGo
Changes from * Revision (June 2013) to A Revision
- 添加了处理额定值表，特性描述部分，器件功能模式，应用和实施部分，电源相关建议部分，布局部分，器件和文档支持部分以及机械、封装和可订购信息部分。Go
- 添加了器件信息表 Go
- Moved "Minimum Load Impedance" From the Absolute Maximum Ratings table To the Recommended Operating Conditions tableGo
- Added the Thermal Information Table Go
- Changed text in the Overview section From: "toggling the SD pin to logic 1." To: "asserting the SD pin to logic 1."Go
- Changed text in the Headphone Amplifier section From: "the output signal is severely clipped" To: "power consumption will be higher"Go
- Added the Optional Test Setup sectionGo
- Added the Layout Example image Go
6 Pin Configuration and Functions
Pin Functions
7 Specification
7.1 Absolute Maximum Ratings(1)
over operating free-air temperature range, TA = 25°C (unless otherwise noted)| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| Supply voltage, VDD | –0.3 | 6 | V | ||
| Input voltage | RIGHTINx, LEFTINx | CPVSS-0.2 V to minimum of (3.6 V, VDD+0.2 V) |
|||
| SD, TEST1, TEST2 | –0.3 | 7 | V | ||
| Output continuous total power dissipation | See the Thermal Information Table | ||||
| Operating free-air temperature range, TA | –40 | 85 | °C | ||
| Operating junction temperature range, TJ | –40 | 150 | °C | ||
7.2 Handling Ratings
| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| Tstg | Storage temperature range | –65 | 150 | °C | |
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | –3 | 3 | kV |
| Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | –750 | 750 | V | ||
7.3 Recommended Operating Conditions
7.4 Thermal Information
| THERMAL METRIC(1) | RTJ | UNIT | |
|---|---|---|---|
| 20 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 34.8 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 32.5 | |
| RθJB | Junction-to-board thermal resistance | 11.6 | |
| ψJT | Junction-to-top characterization parameter | 0.4 | |
| ψJB | Junction-to-board characterization parameter | 11.6 | |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 3.1 | |
7.5 Electrical Characteristics
TA = 25°C (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| |VOS| | Output offset voltage | VDD = 2.5 V to 5.5 V, inputs grounded | 135 | 400 | μV | ||
| PSRR | DC Power supply rejection ratio | VDD = 2.5 V to 5.5 V, inputs grounded | –101 | -85 | dB | ||
| CMRR | Common mode rejection ratio | VDD = 2.5 V to 5.5 V | –69 | dB | |||
| |IIH| | High-level input current | VDD = 5.5 V, VI = VDD | TEST1, TEST2 | 1 | µA | ||
| SD | 10 | ||||||
| |IIL| | Low-level input current | VDD = 5.5 V, VI = 0 V | SD | 1 | µA | ||
| IDD | Supply current | VDD = 2.5 V to 5.5 V, SD = VDD | 4.2 | 6 | mA | ||
| Shutdown mode, VDD = 2.5V to 5.5 V, SD = 0 V | 0.08 | 1 | µA | ||||
7.6 Operating Characteristics
VDD = 3.6 V , TA = 25°C, RL = 16 Ω (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| PO | Output power | Stereo, Outputs out of phase, THD = 1%, f = 1 kHz, Gain = +4 dB |
VDD = 2.5V | 63 | mW | ||
| VDD = 3.6V | 133 | ||||||
| VDD = 5V | 142 | ||||||
| THD+N | Total harmonic distortion plus noise | PO = 35 mW | f = 100 Hz | 0.0096% | |||
| f = 1 kHz | 0.007% | ||||||
| f = 20 kHz | 0.0021% | ||||||
| kSVR | Supply ripple rejection ratio | 200 mVpp ripple, f = 217 Hz | -94.3 | -85 | dB | ||
| 200 mVpp ripple, f = 1 kHz | -92 | ||||||
| 200 mVpp ripple, f = 20 kHz | -77.1 | ||||||
| Av | Channel DC Gain | SD = VDD | 1.597 | V/V | |||
| ΔAv | Gain matching | 0.1% | |||||
| Slew rate | 0.4 | V/µs | |||||
| Vn | Noise output voltage | VDD = 3.6V, A-weighted, Gain = +4 dB | 12 | µVRMS | |||
| fosc | Charge pump switching frequency | 300 | 381 | 500 | kHz | ||
| Start-up time from shutdown | 4.8 | ms | |||||
| Differential input impedance | 36.6 | kΩ | |||||
| SNR | Signal-to-noise ratio | Po = 35 mW | 93 | dB | |||
| Thermal shutdown | Threshold | 180 | °C | ||||
| Hysteresis | 35 | °C | |||||
| ZO | HW Shutdown HP output impedance | SD = 0 V, measured output to ground. | 112 | Ω | |||
| CO | Output capacitance | 80 | pF | ||||
7.7 Typical Characteristics
Table 1. Table of Graphs
| Figure | ||
|---|---|---|
| Total harmonic distortion + noise | versus Output power | Figure 1–Figure 4 |
| Total harmonic distortion + noise | versus Frequency | Figure 5–Figure 12 |
| Supply voltage rejection ratio | versus Frequency | Figure 13-Figure 14 |
| Common mode rejection ratio | versus Frequency | Figure 15-Figure 16 |
| Crosstalk | versus Frequency | Figure 17-Figure 18 |
Figure 1. Total Harmonic Distortion + Noise vs Output Power
Figure 3. Total Harmonic Distortion + Noise vs Output Power
Figure 2. Total Harmonic Distortion + Noise vs Output Power
Figure 4. Total Harmonic Distortion + Noise vs Output Power
Figure 5. Total Harmonic Distortion + Noise vs Frequency
Figure 7. Total Harmonic Distortion + Noise vs Frequency
Figure 9. Total Harmonic Distortion + Noise vs Frequency
Figure 11. Total Harmonic Distortion + Noise vs Frequency
Figure 13. Supply Voltage Rejection Ratio vs Frequency
Figure 15. Common Mode Rejection Ratio vs Frequency
Figure 17. Crosstalk vs Frequency
Figure 6. Total Harmonic Distortion + Noise vs Frequency
Figure 8. Total Harmonic Distortion + Noise vs Frequency
Figure 10. Total Harmonic Distortion + Noise vs Frequency
Figure 12. Total Harmonic Distortion + Noise vs Frequency
Figure 14. Supply Voltage Rejection Ratio vs Frequency
Figure 16. Common Mode Rejection Ratio vs Frequency
Figure 18. Crosstalk vs Frequency
8 Detailed Description
8.1 Overview
Headphone channels and the charge pump are activated by asserting the SD pin to logic 1. The charge pump generates a negative supply voltage for the output amplifiers. This allows a 0 V bias at the outputs, eliminating the need for bulky output capacitors. The thermal block detects faults and shuts down the device before damage occurs. The current limit block prevents the output current from getting high enough to damage the device. The De-Pop block eliminates audible pops during power-up, power-down, and amplifier enable and disable events.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Headphone Amplifiers
Single-supply headphone amplifiers typically require dc-blocking capacitors. The capacitors are required because most headphone amplifiers have a dc bias on the outputs pin. If the dc bias is not removed, power consumption will be higher, and large amounts of dc current rush through the headphones, potentially damaging them. The top drawing in Figure 19 illustrates the conventional headphone amplifier connection to the headphone jack and output signal.
DC blocking capacitors are often large in value. The headphone speakers (typical resistive values of 16 Ω or 32 Ω) combine with the dc blocking capacitors to form a high-pass filter. Equation 1 shows the relationship between the load impedance (RL), the capacitor (CO), and the cutoff frequency (fC).
CO can be determined using Equation 2, where the load impedance and the cutoff frequency are known.
If fc is low, the capacitor must then have a large value because the load resistance is small. Large capacitance values require large package sizes. Large package sizes consume PCB area, stand high above the PCB, increase cost of assembly, and can reduce the fidelity of the audio output signal.
Two different headphone amplifier applications are available that allow for the removal of the output dc blocking capacitors. The capless amplifier architecture is implemented in the same manner as the conventional amplifier with the exception of the headphone jack shield pin. This amplifier provides a reference voltage, which is connected to the headphone jack shield pin. This is the voltage on which the audio output signals are centered. This voltage reference is half of the amplifier power supply to allow symmetrical swing of the output voltages. Do not connect the shield to any GND reference or large currents will result. The scenario can happen if, for example, an accessory other than a floating GND headphone is plugged into the headphone connector. See the second block diagram and waveform in Figure 19.
Figure 19. Amplifier Applications
The DirectPath™ amplifier architecture operates from a single supply but makes use of an internal charge pump to provide a negative voltage rail. Combining the user provided positive rail and the negative rail generated by the IC, the device operates in what is effectively a split supply mode. The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail. The DirectPath™ amplifier requires no output dc blocking capacitors, and does not place any voltage on the sleeve. The bottom block diagram and waveform of Figure 19 illustrate the ground-referenced headphone architecture. This is the architecture of the TPA6133A2.
8.4 Device Functional Modes
8.4.1 Modes of Operation
The TPA6133A2 supports two modes of operation. When the SD pin is driven to logic 0, the device is in low power mode where the charge pump is powered down, the headphone channel is disabled and the outputs are pulled to ground. When the SD pin is driven to logic 1, the device enters an active mode with charge pump powered up and headphone channel enabled with channel gain of +4dB. The transition from inactive to active and active to inactive states is done softly to avoid audible artifacts.
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPA6133A2 is a stereo DirectPath™ headphone amplifier with GPIO control. The TPA6133A2 has minimal quiescent current consumption, with a typical IDD of 4.2 mA, making it optimal for portable applications.
9.2 Typical Application
Figure 20 shows a typical application circuit for the TPA6133A2 with a stereo headphone jack and supporting power supply decupling capacitors.
Figure 20. Simplified Applications Circuit
9.2.1 Design Requirements
For this design example, use the following as the input parameters.
Table 2. Design Parameters
| DESIGN PARAMTER | EXAMPLE VALUE |
|---|---|
| Input voltage | 2.5 V – 5.5 V |
| Minimum current limit | 4 mA |
| Maximum current limit | 6 mA |
9.2.2 Detailed Design Procedure
9.2.2.1 Input-Blocking Capacitors
DC input-blocking capacitors block the dc portion of the audio source, and allow the inputs to properly bias. Maximum performance is achieved when the inputs of the TPA6133A2 are properly biased. Performance issues such as pop are optimized with proper input capacitors.
The dc input-blocking capacitors may be removed provided the inputs are connected differentially and within the input common mode range of the amplifier, the audio signal does not exceed ±3 V, and pop performance is sufficient.
CIN is a theoretical capacitor used for mathematical calculations only. Its value is the series combination of the dc input-blocking capacitors, C(DCINPUT-BLOCKING). Use Equation 3 to determine the value of C(DCINPUT-BLOCKING). For example, if CIN is equal to 0.22 μF, then C(DCINPUT-BLOCKING) is equal to about 0.47 μF.
The two C(DCINPUT-BLOCKING) capacitors form a high-pass filter with the input impedance of the TPA6133A2. Use Equation 3 to calculate CIN, then calculate the cutoff frequency using CIN and the differential input impedance of the TPA6133A2, RIN, using Equation 4. Note that the differential input impedance changes with gain. The frequency and/or capacitance can be determined when one of the two values are given.
If a high pass filter with a -3 dB point of no more than 20 Hz is desired over all gain settings, the minimum impedance would be used in the above equation. The capacitor value by the above equation would be 0.215 μF. However, this is CIN, and the desired value is for C(DCINPUT-BLOCKING). Multiplying CIN by 2 yields 0.43 μF, which is close to the standard capacitor value of 0.47 μF. Place 0.47 μF capacitors at each input terminal of the TPA6133A2 to complete the filter.
9.2.2.2 Charge Pump Flying Capacitor and CPVSS Capacitor
The charge pump flying capacitor serves to transfer charge during the generation of the negative supply voltage. The CPVSS capacitor must be at least equal to the flying capacitor in order to allow maximum charge transfer. Low ESR capacitors are an ideal selection, and a value of 1 µF is typical.
9.2.2.3 Decoupling Capacitors
The TPA6133A2 is a DirectPath™ headphone amplifier that requires adequate power supply decoupling to ensure that the noise and total harmonic distortion (THD) are low. Use good low equivalent-series-resistance (ESR) ceramic capacitors, typically 1.0 µF. Find the smallest package possible, and place as close as possible to the device VDD lead. Placing the decoupling capacitors close to the TPA6133A2 is important for the performance of the amplifier. Use a 10 μF or greater capacitor near the TPA6133A2 to filter lower frequency noise signals. The high PSRR of the TPA6133A2 will make the 10 μF capacitor unnecessary in most applications.
9.2.3 Application Curves
Figure 22. Shutdown Time
Figure 23. Startup Time
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range of 2.5 V to 5.5 V. Therefore, the output voltage range of power supply should be within this range and well regulated. The current capability of upper power should not exceed the max current limit of the power switch.
11 Layout
11.1 Layout Guidelimes
11.1.1 Exposed Pad On TPA6133A2RTJ Package
- Solder the exposed metal pad on the TPA6133A2RTJ QFN package to the a pad on the PCB. The pad on the PCB may be grounded or may be allowed to float (not be connected to ground or power).
- If the pad is grounded, it must be connected to the same ground as the GND pins (3, 9, 10, 13, and 19). See the layout and mechanical drawings at the end of the datasheet for proper sizing.
- Soldering the thermal pad improves mechanical reliability, improves grounding of the device, and enhances thermal conductivity of the package.
11.1.2 GND Connections
- The GND pin for charge pump should be decoupled to the charge pump VDD pin, and the GND pin adjacent to the Analog VDD pin should be separately decoupled to each other.
