具有 32 位 384kHz PCM 接口的 PCM512x 2VRMS DirectPath™ 112dB 和 106dB 音频立体声 DAC
- ZHCSAC2C August 2012 – October 2018 PCM5121 , PCM5122
  
  PRODUCTION DATA.

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DATA SHEET

具有 32 位 384kHz PCM 接口的 PCM512x 2VRMS DirectPath™ 112dB 和 106dB 音频立体声 DAC

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

可通过寄存器选择的自动处理功能最高可达 48kHz f_S
- 动态范围控制 (DRC)
- 均衡 (EQ)
- 过滤
数模转换器 (DAC) 功能（f_S 达 384kHz）
市场领先的低带外噪声
可选数字滤波器延迟与性能
无需隔直电容
集成负电荷泵
智能静音系统；软斜升或斜降搭配模拟静音，实现 120dB 静音信噪比 (SNR)
具有 BCK 基准的集成高性能音频锁相环 (PLL)，可在内部生成 SCK
接受 16 位、20 位、24 位和 32 位音频数据
脉冲编码调制 (PCM) 数据格式：I²S、左对齐、右对齐、时分复用 (TDM)/数字信号处理 (DSP)
通用串行接口 (SPI) 或者 I²C 控制
软件或者硬件配置
禁用 LRCK 和 BCK 时进入自动节能模式
1.8V 或 3.3V 故障安全低电压互补金属氧化物半导体 (LVCMOS) 数字输入
单电源运算：
- 3.3V 模拟，1.8V 或 3.3V 数字
集成上电复位
28 引脚小型封装

2 应用

A/V 接收器
DVD，BD 播放器
HDTV 接收器
需要 2 V_RMS 音频输出的应用

3 说明

PCM512x 器件属于单片 CMOS 集成电路系列，由立体声数模转换器 (DAC) 和采用薄型小外形尺寸 (TSSOP) 封装的附加支持电路组成。PCM512x 使用 TI 最新一代高级分段 DAC 架构产品，可实现出色的动态性能并提升针对时钟抖动的耐受度。

此PCM512x系列产品成员集成了带有可编程系数的预置音频处理功能，这使得开发人员能够改变他们产品内的内插滤波器，扬声器 EQ，动态范围控制以及平均音量控制的特性。

PCM512x 提供 2.1 V_RMS 中央接地输出（设计人员无需在输出上连接隔直电容）以及传统意义上与单电源线路驱动器相关的外部静音电路。

集成线路驱动器支持低至 1kΩ 的负载，从而在性能上超过其他所有基于电荷泵的线路驱动器。PCM512x 支持低至 1kΩ 的负载，实际能够驱动多达 10 个并联产品（LCD TV、DVDR 和 AV 接收器等）。

器件上集成的 PLL 免除了对于系统时钟（通常称为主时钟）的需要，从而实现 3 线制 I²S 连接，同时减少系统电磁干扰 (EMI)。

器件信息⁽¹⁾

器件型号	封装	封装尺寸（标称值）
PCM5121	TSSOP (28)	9.7mm × 4.4mm
PCM5122	TSSOP (28)	9.7mm × 4.4mm

如需了解所有可用封装，请参阅数据表末尾的封装选项附录。

Device Images

简化系统图

PCM5121 PCM5122 line_out_pcm1865_pcm512x_tpa3130_tpa6120a2_sysdiag.gif

4 修订历史记录

Changes from B Revision (January 2016) to C Revision

Added bullet item with additional description for 3-wire mode operation to Design Requirements section Go

Changes from A Revision (September 2012) to B Revision

Changed 接受 16 位、24 位和 32 位音频数据至接受 16 位、20 位、24 位和 32 位音频数据Go
Deleted 内部无喀嗒和噼啪声控制，用于更改采样率或暂停时钟，.. 无喀嗒和噼啪声操作Go
Added 引脚配置和功能 部分、ESD 额定值 表、特性说明 部分、器件功能模式 部分、应用和实施 部分、电源建议 部分、布局部分、器件和文档支持 部分以及机械、封装和可订购信息 部分Go
Clarified Pin Functions table.Go
Deleted redundant PLL specification in Recommended Operating ConditionsGo
Deleted Intelligent clock error... and ...for pop-free performance in the Overview section.Go
Added note on instruction cycle requirements.Go
Added note on instruction cycles in Fixed Audio Processing Flow (Program 5).Go
Changed Ouptut to OutputGo
Deleted VREF mode provides 2.1V_rms full-scale output at both AVDD levels.Go
Clarified clock generation explanation in Reset and System Clock FunctionsGo
Clarified external SCK discussion in Clock Slave Mode with BCK PLL to Generate Internal Clocks (3-Wire PCM).Go
Deleted The PCM512x disables the internal PLL when an external SCK is supplied.Go

Changes from * Revision (August 2012) to A Revision

已将器件状态由“产品预览”改为“量产数据”Go

5 Device Comparison

Table 1. Differences Between PCM512x Devices

PART NUMBER	DYNAMIC RANGE	SNR	THD
PCM5122A	112 dB	112 dB	–93 dB
PCM5121A	106 dB	106 dB	–92 dB

Table 2. Typical Performance (3.3-V Power Supply)

PARAMETER	PCM5122 / PCM5121
SNR	112 / 106 dB
Dynamic range	112 /106 dB
THD+N at –1 dBFS	–93/ –92 dB
Full-scale single-ended output	2.1 V_RMS (GND center)
Normal 8× oversampling digital filter latency	20/f_S
Low latency 8× oversampling digital filter latency	3.5/f_S
Sampling frequency	8 kHz to 384 kHz
System clock multiples (f_SCK): 64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, 3072	Up to 50 MHz

6 Pin Configuration and Functions

6.0.1 RHB Package
I²C Mode
(MODE1 tied to DGND and MODE2 tied to DVDD)
Top View

PCM5121 PCM5122 po_pcm512x-4x_mode1-gnd_mode2-dvdd_i2c.gif

6.0.3 RHB Package
Hardwired Mode
(MODE1 tied to DGND, MODE2 tied to DGND)
Top View

PCM5121 PCM5122 po_pcm512x-4x_mode1-gnd_mode2-gnd_hardwired.gif

6.0.2 RHB Package
SPI Mode
(MODE1 tied to DVDD)
Top View

PCM5121 PCM5122 po_pcm512x-4xmode1-dvdd_spi.gif

Table 3. Gain and Attenuation in Hardwired Mode

ATT PIN CONDITION (ATT2 : ATT1 : ATT0)	GAIN AND ATTENUATION LEVEL
( 0 0 0 )	0 dB
( 0 0 1 )	3 dB
( 0 1 0 )	6 dB
( 0 1 1 )	9 dB
( 1 0 0 )	12 dB
( 1 0 1 )	15 dB
( 1 1 0 )	–6 dB
( 1 1 1 )	–3 dB

Pin Functions

PIN				I/O	DESCRIPTION
NAME	MODE, NO.
NAME	I²C	SPI	HW
CPVDD	1	1	1	-	Charge pump power supply, 3.3 V
CAPP	2	2	2	O	Charge pump flying capacitor terminal for positive rail
CPGND	3	3	3	-	Charge pump ground
CAPM	4	4	4	O	Charge pump flying capacitor terminal for negative rail
VNEG	5	5	5	O	Negative charge pump rail terminal for decoupling, –3.3 V
OUTL	6	6	6	O	Analog output from DAC left channel
OUTR	7	7	7	O	Analog output from DAC right channel
AVDD	8	8	8	-	Analog power supply, 3.3 V
AGND	9	9	9	-	Analog ground
VCOM	10	10	–	O	I²C, SPI	VCOM output (optional mode selected by register; default setting is VREF mode.) When in VREF mode (default), this pin ties to GND. When in VCOM mode, decoupling capacitor to GND is required.
DEMP	–	–	10	I	HW	DEMP: De-emphasis control for 44.1-kHz sampling rate: Off (Low) / On (High)
SDA	11	–	–	I/O	I²C	Data for I²C⁽¹⁾⁽²⁾
MOSI	–	11	–	I	SPI	Input data for SPI⁽²⁾
ATT2	–	–	11	I	HW	Digital gain and attenuation control pin
SCL	12	–	–	I	I²C	Input clock for I²C⁽²⁾
MC	–	12	–		SPI	Input clock for SPI⁽²⁾
ATT1	–	–	12		HW	Digital gain and attenuation control pin
GPIO5	13	13	–	I/O	I²C, SPI	General purpose digital input and output port ⁽³⁾
ATT0	–	–	13	I/O	HW	Digital gain and attenuation control pin
GPIO4	14	14	–	I/O	I²C, SPI	General purpose digital input and output port ⁽³⁾
MAST	–	–	14	I/O	HW	I²S Master clock select pin : Master (High) BCK/LRCK outputs, Slave (Low) BCK/LRCK inputs
GPIO3	15	15	–	I/O	I²C, SPI	General purpose digital input and output port ⁽³⁾
AGNS	–	–	15	I/O	HW	Analog gain selector : 0-dB 2-V_RMS output (Low), –6-dB 1-V_RMS output (High)
ADR2	16	–	–	I/O	I²C	2nd LSB address select bit for I²C
GPIO2	–	16	–	I/O	SPI	General purpose digital input and output port
DOUT	–	–	16	O	HW	General Purpose Output (Low level)
MODE1	17	17	17	I		Mode control selection pin ⁽²⁾ MODE1 = Low, MODE2 = Low : Hardwired mode MODE1 = Low, MODE2 = High: I²C mode MODE1 = High: SPI mode
MODE2	18	–	18		I²C, HW	MODE2
MS	–	18	–	I	SPI	MS pin (chip select for SPI)
GPIO6	19	19	–	I/O	I²C, SPI	General purpose digital input and output port
FLT	–	–	19	I	HW	Filter select : Normal latency (Low) / Low latency (High)
SCK	20	20	20	I	System clock input⁽²⁾
BCK	21	21	21	I/O	Audio data bit clock input (slave) or output (master)⁽²⁾
DIN	22	22	22	I	Audio data input⁽²⁾
LRCK	23	23	23	I/O	Audio data word clock input (slave) or output (master)⁽²⁾
ADR1	24	–	–	I/O	I²C	LSB address select bit for I²C
MISO (GPIO1)	–	24	–		SPI	Primary output data for SPI readback. Secondary; general purpose digital input/output port controlled by register
FMT	–	–	24		HW	Audio format selection : I²S (Low) / Left justified (High)
XSMT	25	25	25	I	Soft mute control Soft mute⁽²⁾ (Low) / soft un-mute (High)
LDOO	26	26	26	-	Internal logic supply rail terminal for decoupling, 1.8 V
DGND	27	27	27	-	Digital ground
DVDD	28	28	28	-	Digital power supply, 3.3 V or 1.8 V

(1) Open-drain configuration in out mode.

(2) Failsafe LVCMOS Schmitt trigger input.

(3) Internal Pulldown

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Supply voltage	AVDD, CPVDD, DVDD	–0.3	3.9	V
Supply voltage	LDO with DVDD at 1.8 V	–0.3	2.25	V
Digital input voltage	DVDD at 1.8 V	–0.3	2.25	V
Digital input voltage	DVDD at 3.3 V	–0.3	3.9	V
Analog input voltage		–0.3	3.9	V
Operating junction temperature, T_J		–40	130	°C
Storage temperature, T_stg		–65	150	°C

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±750	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

				MIN	NOM	MAX	UNIT
A_VDD	Analog power supply voltage	Referenced to AGND⁽¹⁾	VCOM mode	3	3.3	3.46	V
A_VDD	Analog power supply voltage	Referenced to AGND⁽¹⁾	VREF mode	3.2	3.3	3.46	V
D_VDD	Digital power supply voltage	Referenced to DGND⁽¹⁾	1.8 V DVDD	1.65	1.8	1.95	V
D_VDD	Digital power supply voltage	Referenced to DGND⁽¹⁾	3.3 V DVDD	3.1	3.3	3.46	V
CPVDD	Charge pump supply voltage	Referenced to CPGND⁽¹⁾		3.1	3.3	3.46	V
MCLK	Master clock frequency					50	MHz
LOL, LOR	Stereo line output load resistance			1	10		kΩ
C_LOUT	Digital output load capacitance				10		pF
T_J	Operating junction temperature			–40		130	°C

(1) All grounds on board are tied together; they must not differ in voltage by more than 0.2-V maximum, for any combination of ground signals.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		PCM512x	UNIT
		RHB (TSSOP)
		32 PINS
R_θJA	Junction-to-ambient thermal resistance	72.2	°C/W
R_θJC(top)	Junction-to-case(top) thermal resistance	17.5	°C/W
R_θJB	Junction-to-board thermal resistance	35.0	°C/W
ψ_JT	Junction-to-top characterization parameter	0.4	°C/W
ψ_JB	Junction-to-board characterization parameter	34.5	°C/W

(1) For more information about trdational and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

T_A = 25°C, AV_DD = CPV_DD = DV_DD = 3.3 V, f_S = 48 kHz, system clock = 512 f_S and 24-bit data (unless otherwise noted).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
	Resolution		16	24	32	Bits
DIGITAL INPUT/OUTPUT
Logic Family: 3.3-V LVCMOS Compatible
V_IH	Input logic level, high		0.7 × DV_DD			V
V_IL	Input logic level, low				0.3 × DV_DD	V
I_IH	Input logic current, high	V_IN = V_DD			10	µA
I_IL	Input logic current, low	V_IN = 0 V			–10	µA
V_OH	Output logic level, high	I_OH = –4 mA	0.8 × DV_DD			V
V_OL	Output logic level, low	I_OL = 4 mA			0.22 × DV_DD	V
Logic Family 1.8-V LVCMOS Compatible
V_IH	Input logic level, high		0.7 × DV_DD			V
V_IL	Input logic level, low				0.3 × DV_DD	V
I_IH	Input logic current, high	V_IN = V_DD			10	µA
I_IL	Input logic current, low	V_IN = 0 V			–10	µA
V_OH	Output logic level, high	I_OH = –2 mA	0.8 × DV_DD			V
V_OL	Output logic level, low	I_OL = 2 mA			0.22 × DV_DD	V
DYNAMIC PERFORMANCE (PCM MODE)⁽¹⁾⁽²⁾
	THD+N at –1 dB⁽²⁾	f_S = 48 kHz		–93	–83	dB
		f_S = 96 kHz		–93
		f_S = 192 kHz		–93
	Dynamic range⁽²⁾	EIAJ, A-weighted, f_S = 48 kHz	108	112		dB
		EIAJ, A-weighted, f_S = 96 kHz		112
		EIAJ, A-weighted, f_S = 192 kHz		112
	Signal-to-noise ratio⁽²⁾	EIAJ, A-weighted, f_S = 48 kHz		112		dB
		EIAJ, A-weighted, f_S = 96 kHz		112
		EIAJ, A-weighted, f_S = 192 kHz		112
	Signal-to-noise ratio with analog mute⁽²⁾⁽³⁾	EIAJ, A-weighted, f_S = 48 kHz	113	123		dB
		EIAJ, A-weighted, f_S = 96 kHz	113	123
		EIAJ, A-weighted, f_S = 192 kHz	113	123
	Channel separation	f_S = 48 kHz	100 / 95	109 / 103		dB
		f_S = 96 kHz	100 / 95	109 / 103
		f_S = 192 kHz	100 / 95	109 / 103
ANALOG OUTPUT
	Single-ended output voltage			2.1		V_RMS
	Gain error		–6	±2.0	6	% of FSR
	Gain mismatch, channel-to-channel		–6	±0.5	6	% of FSR
	Load impedance		5			kΩ
FILTER CHARACTERISTICS–1: NORMAL (8x)
	Pass band				0.45 × f_S	kHz
	Stop band		0.55 × f_S			kHz
	Stop band attenuation		–60			dB
	Pass-band ripple				±0.02	dB
	Delay time			20 × t_S		s
FILTER CHARACTERISTICS–2: LOW LATENCY (8x)
	Pass band				0.47 × f_S	kHz
	Stop band		0.55 × f_S			kHz
	Stop band attenuation		–52			dB
	Pass-band ripple				±0.0001	dB
	Delay time			3.5 × t_S		s
FILTER CHARACTERISTICS–3: ASYMMETRIC FIR (8x)
	Pass band				0.4 × f_S	kHz
	Stop band		0.72 × f_S			kHz
	Stop band attenuation		–52			dB
	Pass-band ripple				±0.05	dB
	Delay time			1.2 × t_S		s
FILTER CHARACTERISTICS–4: HIGH-ATTENUATION (8x)
	Pass band				0.45 × f_S	kHz
	Stop band		0.45 × f_S			kHz
	Stop band attenuation			–100		dB
	Pass-band ripple				±0.0005	dB
	Delay time			33.7 × t_S		s
POWER SUPPLY REQUIREMENTS
DV_DD	Digital supply voltage	Target DV_DD = 1.8 V	1.65	1.8	1.95	VDC
DV_DD	Digital supply voltage	Target DV_DD = 3.3 V	3	3.3	3.6	VDC
AV_DD	Analog supply voltage		3	3.3	3.6	VDC
CPV_DD	Charge-pump supply voltage		3	3.3	3.6	VDC
I_DD	DV_DD supply current at 1.8 V	f_S = 48 kHz, input is bipolar zero data		11	14	mA
		f_S = 96 kHz, input is bipolar zero data		12
		f_S = 192 kHz, input is bipolar zero data		14
I_DD	DV_DD supply current at 1.8 V	f_S = 48 kHz, input is 1 kHz – 1 dBFS data		11	14	mA
		f_S = 96 kHz, input is 1 kHz – 1 dBFS data		12
		f_S = 192 kHz, input is 1 kHz – 1 dBFS data		14
I_DD	DV_DD supply current at 1.8 V⁽⁴⁾	f_S = N/A, power-down mode		0.3	0.6	mA
I_DD	DV_DD supply current at 3.3 V	f_S = 48 kHz, input is bipolar zero data		12	15	mA
		f_S = 96 kHz, input is bipolar zero data		13
		f_S = 192 kHz, input is bipolar zero data		15
I_DD	DV_DD supply current at 3.3 V	f_S = 48 kHz, input is 1 kHz – 1 dBFS data		12	15	mA
		f_S = 96 kHz, input is 1 kHz – 1 dBFS data		13
		f_S = 192 kHz, input is 1 kHz – 1 dBFS data		15
I_DD	DV_DD supply current at 3.3 V⁽⁴⁾	f_S = N/A, power-down mode		0.5	0.8	mA
I_CC	AV_DD + CPV_DD supply current	f_S = 48 kHz, input is bipolar zero data		11	16	mA
		f_S = 96 kHz, input is bipolar zero data		11
		f_S = 192 kHz, input is bipolar zero data		11
I_CC	AV_DD + CPV_DD supply current	f_S = 48 kHz, input is 1 kHz – 1 dBFS data		24	32	mA
		f_S = 96 kHz, input is 1 kHz – 1 dBFS data		24
		f_S = 192 kHz, input is 1 kHz – 1 dBFS data		24
I_CC	AV_DD + CPV_DD supply current⁽⁴⁾	f_S = N/A, power-down mode		0.2	0.4	mA
	Power dissipation, DV_DD = 1.8 V	f_S = 48 kHz, input is bipolar zero data		59.4	78	mW
		f_S = 96 kHz, input is bipolar zero data		61.2
		f_S = 192 kHz, input is bipolar zero data		64.8
	Power dissipation, DV_DD = 1.8 V	f_S = 48 kHz, input is 1 kHz – 1 dBFS data		99	130.8	mW
		f_S = 96 kHz, input is 1 kHz – 1 dBFS data		100.8
		f_S = 192 kHz, input is 1 kHz – 1 dBFS data		104.4
	Power dissipation, DV_DD = 1.8 V⁽⁴⁾	f_S = N/A, power-down mode		1.2		mW
	Power dissipation, DV_DD = 3.3 V	f_S = 48 kHz, input is bipolar zero data		79.2	103	mW
		f_S = 96 kHz, input is bipolar zero data		82.5
		f_S = 192 kHz, input is bipolar zero data		89.1
	Power dissipation, DV_DD = 3.3 V	f_S = 48 kHz, input is 1 kHz – 1 dBFS data		118.8	155	mW
		f_S = 96 kHz, input is 1 kHz – 1 dBFS data		122.1
		f_S = 192 kHz, input is 1 kHz – 1 dBFS data		128.7
	Power dissipation, DV_DD = 3.3 V⁽⁴⁾	f_S = N/A, power-down mode		2.3	4	mW

(1) Filter condition: THD+N: 20-Hz HPF, 20-kHz AES17 LPF Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Channel separation: 20-Hz HPF, 20-kHz AES17 LPF Analog performance specifications are measured using the System Two Cascade™ audio measurement system by Audio Precision™ in the RMS mode.

(2) Output load is 10 kΩ, with 470-Ω output resistor and a 2.2-nF shunt capacitor (see Recommended Output Filter for the PCM512x).

(3) Assert XSMT or both L-ch and R-ch PCM data are BPZ

(4) Power-down mode, with LRCK, BCK, and SCK halted at low level.

7.6 Timing Requirements: SCK Input

Figure 1 shows the timing requirements for the system clock input. For optimal performance, use a clock source with low phase jitter and noise.

			MIN	MAX	UNIT
t_SCY	System clock pulse cycle time		20	1000	ns
t_SCKH	System clock pulse width, high	DVDD = 1.8 V	8		ns
t_SCKH	System clock pulse width, high	DVDD = 3.3 V	9		ns
t_SCKL	System clock pulse width, low	DVDD = 1.8 V	8		ns
t_SCKL	System clock pulse width, low	DVDD = 3.3 V	9		ns

7.7 Timing Requirements: XSMT

		MIN	NOM	MAX	UNIT
t_r	Rise time			20	ns
t_f	Fall time			20	ns

7.8 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
DATA FORMAT (PCM MODE)
	Audio data interface format		I²S, left-justified, right-justified, and TDM
	Audio data bit length		16, 20, 24, 32-bit acceptable
	Audio data format		MSB first, twos-complement
f_S	Sampling frequency⁽¹⁾		8	384	kHz
CLOCKS
	System clock frequency		64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, or 3072 f_SCK, up to 50 Mhz
	PLL input frequency ⁽²⁾	Clock divider uses fractional divide D > 0, P=1	6.7	20	MHz
	PLL input frequency ⁽²⁾	Clock divider uses integer divide D = 0, P=1	1	20	MHz

(1) One sample time is defined as the reciprocal of the sampling frequency. 1 × t_S = 1 / f_S

(2) With the appropriate P coefficient setting, the PLL accepts up to 50 MHz. This clock is then divided to meet the ≤ 20-MHz requirement. See PLL Calculation.

PCM5121 PCM5122 f_pcm51xx_td_sck_req.gif

Figure 1. Timing Requirements for SCK Input

PCM5121 PCM5122 f_pcm51xx_td_xsmt_soft_mute.gif

Figure 2. XSMT Timing for Soft Mute and Soft Un-Mute

7.9 Typical Characteristics

Consumer grade (non-Q1) devices are specified for T_A = 25°C, AV_DD = CPV_DD = DV_DD = 3.3 V, f_S = 48 kHz, system clock = 512 f_S and 24-bit data (unless otherwise noted).

PCM5121 PCM5122 thd_n_input_level_5101.gif

Figure 3. PCM5121 THD+N vs Input Level

Figure 5. PCM5121 FFT Plot Using a 1-kHz Tone
(–60 dBFS) from DC to 20 kHz

Figure 7. PCM5121 FFT Plot at Bipolar Zero Data (BPZ)

Figure 9. PCM5121 FFT Plot at BPZ With Analog Mute (AMUTE)

PCM5121 PCM5122 fft_-60_sub_300kHz_5101.gif

Figure 11. PCM5121 FFT Plot Using a 1-kHz Tone
(–60 dBFS) from DC to 300 kHz

PCM5121 PCM5122 thd_n_input_level_5102.gif

Figure 4. PCM5122 THD+N vs Input Level

Figure 6. PCM5122 FFT Plot Using a 1-kHz Tone
(–60 dBFS) from DC to 20 kHz

Figure 8. PCM5122 FFT Plot at BPZ

Figure 10. PCM5122 FFT Plot at BPZ With Analog Mute (AMUTE)

PCM5121 PCM5122 fft_-60_sub_300kHz_5102.gif

Figure 12. PCM5122 FFT Plot Using a 1-kHz Tone
(–60 dBFS) from DC to 300 kHz

8 Detailed Description

8.1 Overview

The integrated PLL on the device provided adds the flexibility to remove the system clock (commonly known as master clock), allowing a 3-wire I²S connection and reducing system EMI. In addition, the PLL is completely programmable, allowing the device to become the I²S clock master and drive a DSP serial port as a slave. The PLL also accepts a non-standard clock (up to 50 MHz) as a source to generate the audio related clock (for example, 24.576 MHz).

Powersense undervoltage protection utilizes a two-level mute system. Upon clock error or system power failure, the device digitally attenuates the data (or last known good data) and then mutes the analog circuit.

Compared with existing DAC technology, the PCM512x devices offer up to 20 dB of lower out-of-band noise, reducing EMI and aliasing in downstream amplifiers/ADCs (from traditional 100-kHz OBN measurements to
3 MHz).

The PCM512x devices accept industry-standard audio data formats with 16-bit to 32-bit data. Sample rates up to 384 kHz are supported.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Terminology

Control registers in this data sheet are given by REGISTER BIT/BYTE NAME (Page.x HEX ADDRESS). SE refers to single-ended analog inputs. SCK (System Clock) and MCLK (Master Clock) are used interchangeably. Sampling frequency is symbolized by f_S. Full scale is symbolized by FS. Sample time as a unit is symbolized by t_S.

8.3.2 Audio Data Interface

8.3.2.1 Audio Serial Interface

The audio interface port is a 3-wire serial port with the signals LRCK, BCK, and DIN. BCK is the serial audio bit clock, used to clock the serial data present on DIN into the serial shift register of the audio interface. Serial data is clocked into the PCM512x on the rising edge of BCK. LRCK is the serial audio left/right word clock. LRCK polarity for left/right is given by the format selected.

Table 4. PCM512x Audio Data Formats, Bit Depths and Clock Rates

CONTROL MODE	FORMAT	DATA BITS	MAX LRCK FREQUENCY [f_S]	SCK RATE [x f_S]	BCK RATE [x f_S]
Software Control (SPI or I²S)	I²S/LJ	32, 24, 20, 16	Up to 192 kHz	128 – 3072	64, 48, 32
	I²S/LJ	32, 24, 20, 16	384 kHz	64, 128	64, 48, 32
	TDM/DSP	32, 24, 20, 16	Up to 48 kHz	128 – 3072	128, 256
			96 kHz	128 – 512	128, 256
			192 kHz	128, 192, 256	128
Hardware Control	I²S/LJ	32, 24, 20, 16	Up to 192 kHz	128 – 3072	64, 48, 32
Hardware Control	I²S/LJ	32, 24, 20, 16	384 kHz	64, 128	64, 48, 32

The PCM512x requires the synchronization of LRCK and system clock, but does not need a specific phase relation between LRCK and system clock.

If the relationship between LRCK and system clock changes more than ±5 SCK, internal operation (using an onchip oscillator) is initialized within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and system clock is completed.

If the relationship between LRCK and BCK are invalid more than 4 LRCK periods, internal operation (using an onchip oscillator) is initialized within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and BCK is completed.

8.3.2.2 PCM Audio Data Formats

The PCM512x supports industry-standard audio data formats, including standard I²S and left-justified. Data formats are selected via Register (Pg0Reg40). All formats require binary twos-complement, MSB-first audio data; up to 32-bit audio data is accepted.

The PCM512x also supports right-justified and TDM/DSP in software control mode. I²S, LJ, RJ, and TDM/DSP are selected using Register (Pg0Reg40). All formats require binary twos-complement, MSB-first audio data. Up to 32 bits are accepted. Default setting is I²S and 24-bit word length.

PCM5121 PCM5122 f_pcm51xx_aud_data_format_lj.gif

Figure 13. Left-Justified Audio Data Format

PCM5121 PCM5122 f_pcm51xx_aud_data_format_i2s.gif

I²S Data Format; L-channel = LOW, R-channel = HIGH

Figure 14. I²S Audio Data Format

The following data formats are only available in software mode.

PCM5121 PCM5122 f_pcm51xx_aud_data_format_rj.gif

Right Justified Data Format; L-channel = HIGH, R-channel = LOW

Figure 15. Right-Justified Audio Data Format

PCM5121 PCM5122 f_pcm51xx_aud_data_format_tdm1.gif

TDM/DSP Data Format; L-channel = FIRST, R-channel = LAST with OFFSET = 0

Figure 16. TDM/DSP 1 Audio Data Format

NOTE

In TDM Modes, Duty Cycle of LRCK should be 1x BCK at minimum. Rising edge is considered frame start.

PCM5121 PCM5122 f_pcm51xx_aud_data_format_tdm2.gif

TDM/DSP Data Format; L-channel = FIRST, R-channel = LAST with OFFSET = 1

Figure 17. TDM/DSP 2 Audio Data Format

PCM5121 PCM5122 f_pcm51xx_aud_data_format_tdm3.gif

TDM/DSP Data Format; L-channel = FIRST, R-channel = LAST with OFFSET = N

Figure 18. TDM/DSP 3 Audio Data Format

8.3.2.3 Zero Data Detect

The PCM512x has a zero-detect function. When the device detects the continuous zero data for both left and right channels, or separate channels, Analog mutes are set to both OUTL and OUTR, or separate OUTL and OUTR. These are controlled by Page 0, Register 65, D(2:1) as shown in Table 5.

Continuous Zero data cycles are counted by LRCK, and the threshold of decision for analog mute can be set by Page 0, Register 59, D(6:4) for L-ch, and D(2:0) for Rch as shown in Table 6. Default values are 0 for both channels.

In Hardware mode, the device uses default values. By default, Both L-ch and R-ch have to be zero data for zero data detection to begin the muting process etc.

Table 5. Zero Data Detection Mode

ATMUTECTL	VALUE	FUNCTION
Bit : 2	0	Independently L-ch or R-ch are zero data for zero data detection
Bit : 2	1 (Default)	Both L-ch and R-ch have to be zero data for zero data detection
Bit : 1	0	Zero detection and analog mute are disabled for R-ch
Bit : 1	1 (Default)	Zero detection analog mute are enabled for R-ch
Bit : 0	0	Zero detection analog mute are disabled for L-ch
Bit : 0	1 (Default)	Zero detection analog mute are enabled for L-ch

Table 6. Zero Data Detection Time

ATMUTETIML / ATMUTETIMR	NUMBER OF LRCKs	TIME AT 48 kHz
0 0 0	1024	21 ms
0 0 1	5120	106 ms
0 1 0	10240	213 ms
0 1 1	25600	533 ms
1 0 0	51200	1.066 sec
1 0 1	102400	2.133 sec
1 1 0	256000	5.333 sec
1 1 1	512000	10.66 sec

8.3.3 XSMT Pin (Soft Mute / Soft Un-Mute)

An external digital host controls the PCM512x soft mute function by driving the XSMT pin with a specific minimum rise time (t_r) and fall time (t_f) for soft mute and soft un-mute. The PCM512x requires t_r and t_f times of less than 20 ns. In the majority of applications, this is no problem; however, traces with high capacitance may have issues.

When the XSMT pin is shifted from high to low (3.3 V to 0 V), a soft digital attenuation ramp begins. –1-dB attenuation is then applied every sample time from 0 dBFS to –∞. The soft attenuation ramp takes 104 samples.

When the XSMT pin is shifted from low to high (0 V to 3.3 V), a soft digital un-mute is started. 1-dB gain steps are applied every sample time from –∞ to 0 dBFS. The un-mute takes 104 samples.

In systems where XSMT is not required, it can be directly connected to AVDD.

8.3.4 Audio Processing

8.3.4.1 PCM512x Audio Processing

8.3.4.1.1 Overview

The PCM512x supports a fixed audio processing flow with programmable coefficients. (Program 5 - Fixed Audio Processing Flow (Program 5) of this data sheet). Details can be found below.

NOTE

At higher sampling frequencies, fewer instruction cycles are available. (For example, 512 instructions can be done in a 96-kHz frame.)

The audio processing chain can run up to 1024 instructions on every audio sample at a 48-kHz sample rate.

8.3.4.1.2 Software

Software development for the PCM512x is supported through TI's comprehensive PurePath Studio Development Environment; a powerful, easy-to-use tool designed specifically to simplify software development on the PCM512x audio platform. The Graphical Development Environment consists of a library of common audio functions that can be dragged-and-dropped into an audio signal flow and graphically connected together. The DSP code can then be assembled from the graphical signal flow with the click of a mouse.

Please visit the PCM512x product folder on www.ti.com to learn more about PurePath Studio and the latest status on available, ready-to-use DSP algorithms.