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  • 具有 AM 抑制功能的 TPA3116D2 15W、30W、50W 无滤波器 D 类立体声放大器系列

    • ZHCS891G April   2012  – December 2017 TPA3116D2 , TPA3118D2 , TPA3130D2

      PRODUCTION DATA.  

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  • 具有 AM 抑制功能的 TPA3116D2 15W、30W、50W 无滤波器 D 类立体声放大器系列
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化应用电路
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 AC Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Gain Setting and Master and Slave
      2. 7.3.2  Input Impedance
      3. 7.3.3  Startup and Shutdown Operation
      4. 7.3.4  PLIMIT Operation
      5. 7.3.5  GVDD Supply
      6. 7.3.6  BSPx AND BSNx Capacitors
      7. 7.3.7  Differential Inputs
      8. 7.3.8  Device Protection System
      9. 7.3.9  DC Detect Protection
      10. 7.3.10 Short-Circuit Protection and Automatic Recovery Feature
      11. 7.3.11 Thermal Protection
      12. 7.3.12 Device Modulation Scheme
        1. 7.3.12.1 MODSEL = GND: BD-Modulation
        2. 7.3.12.2 MODSEL = HIGH: 1SPW-modulation
      13. 7.3.13 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
      14. 7.3.14 Ferrite Bead Filter Considerations
      15. 7.3.15 When to Use an Output Filter for EMI Suppression
      16. 7.3.16 AM Avoidance EMI Reduction
    4. 7.4 Device Functional Modes
      1. 7.4.1 Mono Mode (PBTL)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select the PWM Frequency
        2. 8.2.2.2 Select the Amplifier Gain and Master/Slave Mode
        3. 8.2.2.3 Select Input Capacitance
        4. 8.2.2.4 Select Decoupling Capacitors
        5. 8.2.2.5 Select Bootstrap Capacitors
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Heat Sink Used on the EVM
  11. 11器件和文档支持
    1. 11.1 相关链接
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息
  13. 重要声明
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DATA SHEET

具有 AM 抑制功能的 TPA3116D2 15W、30W、50W 无滤波器 D 类立体声放大器系列

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 支持多个输出配置
    • 21V 电压、4Ω BTL 负载条件下的功率为 2 × 50W (TPA3116D2)
    • 24V 电压、8Ω BTL 负载条件下的功率为 2 × 30W (TPA3118D2)
    • 15V 电压、8Ω BTL 负载条件下的功率为 2 × 15W (TPA3130D2)
  • 宽电压范围：4.5V 至 26V
  • 高效 D 类运行
    • 大于 90% 的电源效率加之较低空闲损耗，大幅减小了散热器尺寸
    • 高级调制方案
  • 多重开关频率
    • AM 抑制
    • 主从同步
    • 高达 1.2MHz 的开关频率
  • 采用具有高 PSRR 的反馈功率级架构，降低了 PSU 要求
  • 可编程功率限制
  • 差分和单端输入
  • 立体声模式和单声道模式（采用单滤波器单声道配置）
  • 采用单电源供电，减少了组件数量
  • 集成式自保护电路，包括过压、欠压、过热、直流检测和短路等保护，并且具有错误报告功能
  • 热增强型封装
    • DAD（32 引脚 HTSSOP 封装，焊盘朝上）
    • DAP（32 引脚 HTSSOP 封装，焊盘朝下）
  • -40°C 至 85°C 环境温度范围

2 应用

  • 小型-微型组件、条形音箱、扩展坞
  • 汽车零件市场
  • CRT TV
  • 消费类音频 应用

3 说明

TPA31xxD2 系列是高效的立体声数字放大器功率级，用于在单声道模式下驱动高达 100W/2Ω 的扬声器。TPA3130D2 的效率非常高，可在单层 PCB 上提供 2 × 15W 的功率，且无需外部散热器。TPA3118D2 甚至可以在不使用外部散热器的情况下在双层 PCB 上提供 2 × 30W/8Ω 的功率。如果需要更高的功率，可以选用 TPA3116D2，这款器件在其顶层 PowerPAD 上连接一个小型散热器后可提供 2 × 50W/4Ω 的功率。这三款器件的大小相同，这样一来，使用单个 PCB 即可满足不同功率级的需求。

TPA31xxD2 高级振荡器/PLL 电路采用了一个多开关频率选项来抑制 AM 干扰；搭配选择使用主从选项时，还可使多个器件实现同步。

TPA31xxD2 器件具有短路保护和热保护以及过压、欠压和直流保护，可全面防止出现故障。在过载情况下，器件会将故障情况反馈给处理器，从而避免自身遭到损坏。

器件信息(1)

器件型号封装封装尺寸（标称值）
TPA3116D2 中的器件型号 TPA3116D2 的封装 DAP (32) DAD (32) 11.00mm x 6.20mm
TPA3118D2
TPA3130D2		 DAP (32) 11.00mm x 6.20mm
  1. 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

Device Images

简化应用电路

TPA3116D2 TPA3118D2 TPA3130D2 app_cir_los708.gif

4 修订历史记录

Changes from F Revision (February 2017) to G Revision

  • Changed R to GND column row 1 From: "Short" To: "Open" in Table 3Go
  • Changed R to GVDD column row 1 From: "Open" To: "Short" in Table 3Go

Changes from E Revision (September 2015) to F Revision

  • Changed pin 20 Description From: ceramic cap to OUTPL To: ceramic cap to OUTNL in the Pin Functions tableGo
  • Changed pin 24 Description From: ceramic cap to OUTNL To: ceramic cap to OUTPL in the Pin Functions tableGo
  • Changed 2.3 Hz To 1.9 Hz for HIGH-PASS FILTER in Table 2Go

Changes from D Revision (January 2015) to E Revision

  • 删除了器件信息 表Go

Changes from C Revision (April 2012) to D Revision

  • Added 引脚配置和功能 部分、ESD 额定值 表、特性 说明 部分、器件功能模式、应用和实施 部分、电源相关建议 部分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分Go

Changes from B Revision (May 2012) to C Revision

  • Changed Notes 2 and 3 of the Thermal Information Table.Go
  • Changed the Gain (BTL) Test Condition values for R1 and R2Go
  • Changed the Gain (SLV) Test Condition values for R1 and R2Go
  • Changed the System Block DiagramGo

5 Pin Configuration and Functions

DAD Package
32-Pin HTSSOP With PowerPAD Up
TPA3116D2 Only, Top View
TPA3116D2 TPA3118D2 TPA3130D2 TERMINAL_ASSIGNMENT_los708.gif
DAP Package
32-Pin HTSSOP With PowerPAD Down
Top View
TPA3116D2 TPA3118D2 TPA3130D2 TERMINAL_ASSIGNMENT2_los708.gif

Pin Functions

PINTYPE(1)DESCRIPTION
NO.NAME
1 MODSEL I Mode selection logic input (LOW = BD mode, HIGH = 1 SPW mode). TTL logic levels with compliance to AVCC.
2 SDZ I Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with compliance to AVCC.
3 FAULTZ DO General fault reporting including Over-temp, DC Detect. Open drain.
FAULTZ = High, normal operation
FAULTZ = Low, fault condition
4 RINP I Positive audio input for right channel. Biased at 3 V.
5 RINN I Negative audio input for right channel. Biased at 3 V.
6 PLIMIT I Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect directly to GVDD for no power limit.
7 GVDD PO Internally generated gate voltage supply. Not to be used as a supply or connected to any component other than a 1 µF X7R ceramic decoupling capacitor and the PLIMIT and GAIN/SLV resistor dividers.
8 GAIN/SLV I Selects Gain and selects between Master and Slave mode depending on pin voltage divider.
9 GND G Ground
10 LINP I Positive audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode.
11 LINN I Negative audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode.
12 MUTE I Mute signal for fast disable/enable of outputs (HIGH = outputs Hi-Z, LOW = outputs enabled). TTL logic levels with compliance to AVCC.
13 AM2 I AM Avoidance Frequency Selection
14 AM1 I AM Avoidance Frequency Selection
15 AM0 I AM Avoidance Frequency Selection
16 SYNC DIO Clock input/output for synchronizing multiple class-D devices. Direction determined by GAIN/SLV terminal.
17 AVCC P Analog Supply
18 PVCC P Power supply
19 PVCC P Power supply
20 BSNL BST Boot strap for negative left channel output, connect to 220 nF X5R, or better ceramic cap to OUTNL
21 OUTNL PO Negative left channel output
22 GND G Ground
23 OUTPL PO Positive left channel output
24 BSPL BST Boot strap for positive left channel output, connect to 220 nF X5R, or better ceramic cap to OUTPL
25 GND G Ground
26 BSNR BST Boot strap for negative right channel output, connect to 220 nF X5R, or better ceramic cap to OUTNR
27 OUTNR PO Negative right channel output
28 GND G Ground
29 OUTPR PO Positive right channel output
30 BSPR BST Boot strap for positive right channel output, connect to 220 nF X5R or better ceramic cap to OUTPR
31 PVCC P Power supply
32 PVCC P Power supply
33 PowerPAD G Connect to GND for best system performance. If not connected to GND, leave floating.
(1) TYPE: DO = Digital Output, I = Analog Input, G = General Ground, PO = Power Output, BST = Boot Strap.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MINMAXUNIT
Supply voltage, VCC PVCC, AVCC –0.3 30 V
Input voltage, VI INPL, INNL, INPR, INNR –0.3 6.3 V
PLIMIT, GAIN / SLV, SYNC –0.3 GVDD+0.3 V
AM0, AM1, AM2, MUTE, SDZ, MODSEL –0.3 PVCC+0.3 V
Slew rate, maximum(2) AM0, AM1, AM2, MUTE, SDZ, MODSEL 10 V/ms
Operating free-air temperature, TA –40 85 °C
Operating junction temperature , TJ –40 150 °C
Storage temperature, Tstg –40 125 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) 100 kΩ series resistor is needed if maximum slew rate is exceeded.

6.2 ESD Ratings

VALUEUNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. .

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MINNOMMAXUNIT
VCC Supply voltage PVCC, AVCC 4.5 26 V
VIH High-level input voltage AM0, AM1, AM2, MUTE, SDZ, SYNC, MODSEL 2 V
VIL Low-level input voltage AM0, AM1, AM2, MUTE, SDZ, SYNC, MODSEL 0.8 V
VOL Low-level output voltage FAULTZ, RPULL-UP = 100 kΩ, PVCC = 26 V 0.8 V
IIH High-level input current AM0, AM1, AM2, MUTE, SDZ, MODSEL (VI = 2 V, VCC = 18 V) 50 µA
RL(BTL) Minimum load Impedance Output filter: L = 10 µH, C = 680 nF TPA3116D2, TPA3118D2 3.2 4 Ω
TPA3130D2 5.6 8
RL(PBTL) Output filter: L = 10 µH, C = 1 µF TPA3116D2, TPA3118D2 1.6
TPA3130D2 3.2 4
Lo Output-filter Inductance Minimum output filter inductance under short-circuit condition 1 µH

6.4 Thermal Information

THERMAL METRIC(1)TPA3130D2TPA3118D2TPA3116D2UNIT
DAP(2)DAP(3)DAD(4)
32 PINS32 PINS32 PINS
RθJA Junction-to-ambient thermal resistance 36 22 14 °C/W
ψJT Junction-to-top characterization parameter 0.4 0.3 1.2
ψJB Junction-to-board characterization parameter 5.9 4.7 5.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) For the PCB layout please see the TPA3130D2EVM user guide.
(3) For the PCB layout please see the TPA3118D2EVM user guide.
(4) The heat sink drawing used for the thermal model data are shown in the application section, size: 14mm wide, 50mm long, 25mm high.

6.5 DC Electrical Characteristics

TA = 25°C, AVCC = PVCC = 12 V to 24 V, RL = 4 Ω (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
| VOS | Class-D output offset voltage (measured differentially) VI = 0 V, Gain = 36 dB 1.5 15 mV
ICC Quiescent supply current SDZ = 2 V, No load or filter, PVCC = 12 V 20 35 mA
SDZ = 2 V, No load or filter, PVCC = 24 V 32 50
ICC(SD) Quiescent supply current in shutdown mode SDZ = 0.8 V, No load or filter, PVCC = 12 V <50 µA
SDZ = 0.8 V, No load or filter, PVCC = 24 V 50 400
rDS(on) Drain-source on-state resistance, measured pin to pin PVCC = 21 V, Iout = 500 mA, TJ = 25°C 120 mΩ
G Gain (BTL) R1 = 5.6 kΩ, R2 = Open 19 20 21 dB
R1 = 20 kΩ, R2 = 100 kΩ 25 26 27
R1 = 39 kΩ, R2 = 100 kΩ 31 32 33 dB
R1 = 47 kΩ, R2 = 75 kΩ 35 36 37
G Gain (SLV) R1 = 51 kΩ, R2 = 51 kΩ 19 20 21 dB
R1 = 75 kΩ, R2 = 47 kΩ 25 26 27
R1 = 100 kΩ, R2 = 39 kΩ 31 32 33 dB
R1 = 100 kΩ, R2 = 16 kΩ 35 36 37
ton Turn-on time SDZ = 2 V 10 ms
tOFF Turn-off time SDZ = 0.8 V 2 µs
GVDD Gate drive supply IGVDD < 200 µA 6.4 6.9 7.4 V
VO Output voltage maximum under PLIMIT control V(PLIMIT) = 2 V; VI = 1 Vrms 6.75 7.90 8.75 V

6.6 AC Electrical Characteristics

TA = 25°C, AVCC = PVCC = 12 V to 24 V, RL = 4 Ω (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
KSVR Power supply ripple rejection 200 mVPP ripple at 1 kHz, Gain = 20 dB, Inputs AC-coupled to GND –70 dB
PO Continuous output power THD+N = 10%, f = 1 kHz, PVCC = 14.4 V 25 W
THD+N = 10%, f = 1 kHz, PVCC = 21 V 50
THD+N Total harmonic distortion + noise VCC = 21 V, f = 1 kHz, PO = 25 W (half-power) 0.1%
Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB 65 µV
–80 dBV
Crosstalk VO = 1 Vrms, Gain = 20 dB, f = 1 kHz –100 dB
SNR Signal-to-noise ratio Maximum output at THD+N < 1%, f = 1 kHz, Gain = 20 dB, A-weighted 102 dB
fOSC Oscillator frequency AM2=0, AM1=0, AM0=0 376 400 424 kHz
AM2=0, AM1=0, AM0=1 470 500 530
AM2=0, AM1=1, AM0=0 564 600 636
AM2=0, AM1=1, AM0=1 940 1000 1060
AM2=1, AM1=0, AM0=0 1128 1200 1278
AM2=1, AM1=0, AM0=1 Reserved
AM2=1, AM1=1, AM0=0
AM2=1, AM1=1, AM0=1
Thermal trip point 150+ °C
Thermal hysteresis 15 °C
Over current trip point TPA3130D2 4.5 A
TPA3118D2, TPA3116D2 7.5

6.7 Typical Characteristics

fs = 400 kHz, BD Mode (unless otherwise noted)
TPA3116D2 TPA3118D2 TPA3130D2 G002_THDvFreq6V4R.pngFigure 1. Total Harmonic Distortion + Noise (BTL) vs Frequency
TPA3116D2 TPA3118D2 TPA3130D2 G004_THDvFreq24V4R.pngFigure 3. Total Harmonic Distortion + Noise (BTL) vs Frequency
TPA3116D2 TPA3118D2 TPA3130D2 G006_THDvFreq24V8R.pngFigure 5. Total Harmonic Distortion + Noise (BTL) vs Frequency
TPA3116D2 TPA3118D2 TPA3130D2 G009_THDvPo12V4R.pngFigure 7. Total Harmonic Distortion + Noise (BTL) vs Output Power
TPA3116D2 TPA3118D2 TPA3130D2 G011_THDvPo12V8R.pngFigure 9. Total Harmonic Distortion + Noise (BTL) vs Output Power
TPA3116D2 TPA3118D2 TPA3130D2 G013_PovPlim24V4R.pngFigure 11. Output Power (BTL) vs Plimit Voltage
TPA3116D2 TPA3118D2 TPA3130D2 G015_PovPVCC_8R.pngFigure 13. Maximum Output Power (BTL) vs Supply Voltage
TPA3116D2 TPA3118D2 TPA3130D2 G017_EffvPo6V12V24V8R.pngFigure 15. Power Efficiency (BTL) vs Output Power
TPA3116D2 TPA3118D2 TPA3130D2 G021_XtalkvFreq24V8R.pngFigure 17. Crosstalk vs Frequency
TPA3116D2 TPA3118D2 TPA3130D2 G023_kSVRvFreq12V8R.pngFigure 19. Supply Ripple Rejection Ratio (BTL) vs Frequency
TPA3116D2 TPA3118D2 TPA3130D2 G025_THDvPo12V2R_PBTL.pngFigure 21. Total Harmonic Distortion + Noise (PBTL) vs Output Power
TPA3116D2 TPA3118D2 TPA3130D2 G028_EffvPo6V12V24V2R_PBTL.pngFigure 23. Power Efficiency (PBTL) vs Output Power
TPA3116D2 TPA3118D2 TPA3130D2 G032_THDvPo24V3R_PBTL.pngFigure 25. Total Harmonic Distortion + Noise (PBTL) vs Output Power
TPA3116D2 TPA3118D2 TPA3130D2 G003_THDvFreq12V4R.pngFigure 2. Total Harmonic Distortion + Noise (BTL) vs Frequency
TPA3116D2 TPA3118D2 TPA3130D2 G005_THDvFreq12V8R.pngFigure 4. Total Harmonic Distortion + Noise (BTL) vs Frequency
TPA3116D2 TPA3118D2 TPA3130D2 G008_THDvPo6V4R.pngFigure 6. Total Harmonic Distortion + Noise (BTL) vs Output Power
TPA3116D2 TPA3118D2 TPA3130D2 G010_THDvPo24V4R.pngFigure 8. Total Harmonic Distortion + Noise (BTL) vs Output Power
TPA3116D2 TPA3118D2 TPA3130D2 G012_THDvPo24V8R.pngFigure 10. Total Harmonic Distortion + Noise (BTL) vs Output Power
TPA3116D2 TPA3118D2 TPA3130D2 G014_Gain_PhasevFreq12V4R.pngFigure 12. Gain/Phase (BTL) vs Frequency
TPA3116D2 TPA3118D2 TPA3130D2 G016_PovPVCC_4R_26VMax.pngFigure 14. Maximum Output Power (BTL) vs Supply Voltage
TPA3116D2 TPA3118D2 TPA3130D2 G018_EffvPo6V12V24V4R.pngFigure 16. Power Efficiency (BTL) vs Output Power
TPA3116D2 TPA3118D2 TPA3130D2 G022_XtalkvFreq12V4R.pngFigure 18. Crosstalk vs Frequency
TPA3116D2 TPA3118D2 TPA3130D2 G024_THDvFreq12V2R_PBTL.pngFigure 20. Total Harmonic Distortion + Noise (PBTL) vs Frequency
TPA3116D2 TPA3118D2 TPA3130D2 G027_PovPVCC26V2R_PBTL.pngFigure 22. Maximum Output Power (PBTL) vs Supply Voltage
TPA3116D2 TPA3118D2 TPA3130D2 G030_kSVRvFreq12V2R_PBTL.pngFigure 24. Supply Ripple Rejection Ratio (PBTL) vs Frequency
TPA3116D2 TPA3118D2 TPA3130D2 G034_PovPVCC26V3R_PBTL.pngFigure 26. Maximum Output Power (PBTL) vs Supply Voltage

7 Detailed Description

7.1 Overview

The TPA31xxD2 device is a highly efficient Class D audio amplifier with integrated 120m Ohms MOSFET that allows output currents up to 7.5 A. The high efficiency allows the amplifier to provide an excellent audio performance without the need for a bulky heat sink.

The device can be configured for either master or slave operation by using the SYNC pin. This helps to prevent audible beats noise.

7.2 Functional Block Diagram

TPA3116D2 TPA3118D2 TPA3130D2 bd_los708.gif

7.3 Feature Description

7.3.1 Gain Setting and Master and Slave

The gain of the TPA31xxD2 family is set by the voltage divider connected to the GAIN/SLV control pin. Master or Slave mode is also controlled by the same pin. An internal ADC is used to detect the 8 input states. The first four stages sets the GAIN in Master mode in gains of 20, 26, 32, 36 dB respectively, while the next four stages sets the GAIN in Slave mode in gains of 20, 26, 32, 36 dB respectively. The gain setting is latched during power-up and cannot be changed while device is powered. Table 1 lists the recommended resistor values and the state and gain:

Table 1. Gain and Master/Slave

MASTER / SLAVE MODEGAINR1 (to GND)(1)R2 (to GVDD)(1)INPUT IMPEDANCE
Master 20 dB 5.6 kΩ OPEN 60 kΩ
Master 26 dB 20 kΩ 100 kΩ 30 kΩ
Master 32 dB 39 kΩ 100 kΩ 15 kΩ
Master 36 dB 47 kΩ 75 kΩ 9 kΩ
Slave 20 dB 51 kΩ 51 kΩ 60 kΩ
Slave 26 dB 75 kΩ 47 kΩ 30 kΩ
Slave 32 dB 100 kΩ 39 kΩ 15 kΩ
Slave 36 dB 100 kΩ 16 kΩ 9 kΩ
(1) Resistor tolerance should be 5% or better.
TPA3116D2 TPA3118D2 TPA3130D2 GAIN_SETTING_MASTER_SLAVE_los708.gifFigure 27. Gain, Master/Slave

In Master mode, SYNC terminal is an output, in Slave mode, SYNC terminal is an input for a clock input. TTL logic levels with compliance to GVDD.

 
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