• Menu
  • Product
  • Email
  • PDF
  • Order now

  • 具有 IEC ESD 保护的 SN65HVD7x 3.3V 电源 RS-485

    • ZHCS823H March   2012  – March 2019 SN65HVD72 , SN65HVD75 , SN65HVD78

      UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • 具有 IEC ESD 保护的 SN65HVD7x 3.3V 电源 RS-485
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      典型应用图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Power Dissipation
    7. 7.7  Switching Characteristics: 250 kbps Device (SN65HVD72) Bit Time ≥ 4 µs
    8. 7.8  Switching Characteristics: 20 Mbps Device (SN65HVD75) Bit Time ≥50 ns
    9. 7.9  Switching Characteristics: 50 Mbps Device (SN65HVD78) Bit Time ≥20 ns
    10. 7.10 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Data Rate and Bus Length
        2. 10.2.1.2 Stub Length
        3. 10.2.1.3 Bus Loading
        4. 10.2.1.4 Receiver Failsafe
        5. 10.2.1.5 Transient Protection
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 External Transient Protection
        2. 10.2.2.2 Isolated Bus Node Design
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 器件支持
      1. 13.1.1 第三方产品免责声明
    2. 13.2 文档支持
      1. 13.2.1 相关文档
    3. 13.3 相关链接
    4. 13.4 社区资源
    5. 13.5 商标
    6. 13.6 静电放电警告
    7. 13.7 术语表
  14. 14机械、封装和可订购信息
  15. 重要声明
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

具有 IEC ESD 保护的 SN65HVD7x 3.3V 电源 RS-485

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 可提供小尺寸的 VSSOP 和 SOIC 封装，前者可节省电路板上的空间，后者可实现普遍兼容性
  • 总线 I/O 保护
    • >±15kV 人体模型 (HBM) 保护
    • >±12kV IEC 61000-4-2 接触放电
    • >±4kV IEC 61000-4-4 快速瞬态突发
  • 扩展的工业温度范围
    -40°C 至 125°C
  • 用于噪声抑制的较大接收器滞后 (80mV)
  • 低单元负载可实现超过 200 个节点的连接
  • 低功耗
    • 低待机电源电流：< 2µA
    • 运行期间 ICC 静态电流 < 1mA
  • 与 3.3V 或 5V 控制器兼容的 5V 耐压逻辑输入
  • 针对以下信号传输速率进行了优化：
    250kbps，20Mbps，50Mbps
  • 无干扰加电和断电总线输入和输出

2 应用

  • 工厂自动化
  • 电信基础设施
  • 运动控制

3 说明

这些器件具有稳健耐用的 3.3V 驱动器和接收器，并且采用小型封装，可满足工业应用 应用。这些总线引脚可耐受 ESD 事件，具有对于人体放电模型和 IEC 接触放电规范的高级别保护。

其中每一款器件都配有一个差分驱动器和一个差分接收器。这两个器件由 3.3V 单电源供电。驱动器差分输出和接收器差分输入在内部连接，构成一个适用于半双工（两线制总线）通信的总线端口。这些器件具备宽共模电压范围，因此适用于长线缆上的 应用 长线缆。这些器件额定运行温度范围为 -40°C 至 125°C。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
SN65HVD72、SN65HVD75、SN65HVD78 SOIC (8) 4.91mm × 3.90mm
VSSOP (8) 3.00mm × 3.00mm
VSON (8)
  1. 要了解所有可用封装，请参见数据表末尾的可订购产品附录。

Device Images

典型应用图

SN65HVD72 SN65HVD75 SN65HVD78 ntwrk_app_llse11.gif

4 修订历史记录

Changes from G Revision (Januarly 2019) to H Revision

  • Changed the Pin Configuration imagesGo
  • Changed Supply voltage, VCC MAX value From = 3.6 V To: 5 V in the Absolute Maximum Ratings tableGo
  • Deleted "or R pin" for VCC in the Absolute Maximum RatingsGo
  • Added reliability note to VCC in the Recommended Operating Conditions tableGo

Changes from F Revision (December 2016) to G Revision

  • Changed From: Supply voltage, VCC MAX value = 5.5 V To: Supply voltage, VCC or R pin MAX value = 3.6 V in the Absolute Maximum Ratings tableGo
  • Changed From: Input voltage at any logic pin To: Voltage at D, DE, or RE in the Absolute Maximum Ratings tableGo

Changes from E Revision (September 2016) to F Revision

  • Changed pin A From: 7 To: 6, and pin B From: 6 To: 7 in Figure 26Go

Changes from D Revision (July 2015) to E Revision

  • 添加了新特性：无干扰加电和断电总线输入和输出Go

Changes from C Revision (September 2013) to D Revision

  • Added 引脚配置和功能 部分、ESD 额定值 表、特性 说明 部分、器件功能模式、应用和实施 部分、电源相关建议 部分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信息部分Go

Changes from B Revision (June 2012) to C Revision

  • 删除了特性：> ±12kV IEC61000-4-2 空气间隙放电Go
  • Added Footnote 2 to the Absolute Maximum Ratings tableGo
  • Changed the Switching Characteristics conditions statement From: 250 kbps devices (SN65HVD70, 71, 72) bit time > 4 µs To: 250 kbps device (SN65HVD72) bit time ≥ 4 µsGo
  • Changed the Switching Characteristics conditions statement From: 250 kbps devices (SN65HVD73, 74, 75) bit time > 50 ns To: 250 kbps device (SN65HVD75) bit time ≥ 50 nsGo
  • Changed the Switching Characteristics conditions statement From: 250 kbps devices (SN65HVD76, 77, 78)bit time > 20 ns To: 250 kbps device (SN65HVD78) bit time ≥ 20 ns Go
  • Added note : RL = 54 Ω to Figure 6, Figure 7, and Figure 8Go
  • Added the DGK package to the SN65HVD72, 75, 78 Logic DiagramGo
  • Replaced the LOW-POWER STANDBY MODE sectionGo
  • Added text to the Transient Protection sectionGo

Changes from A Revision (May 2012) to B Revision

  • Added the SON-8 package and Nodes column to Device Comparison Table,Go
  • Changed the Voltage range at A or B Inputs MIN value From: –8 V To: –13 V in the Absolute Maximum Ratings tableGo
  • Added footnote for free-air temperature to the Recommended Operating Conditions tableGo
  • Changed the Bus input current (disabled driver) TYP values for HVD78 VI = 12 V From: 150 To: 240 and VI = –7 V From: –120 To: –180Go
  • Changed, Thermal InformationGo
  • Changed, Thermal CharacteristicsGo
  • Added TYP values to the Switching Characteristics tableGo
  • Added TYP values to the Switching Characteristics tableGo
  • Changed the SN65HVD72, 75, 78 Logic DiagramGo
  • Added section: LOW-POWER STANDBY MODEGo

Changes from * Revision (March 2012) to A Revision

  • Added VALUEs to the Thermal Characteristics table in the DEVICE INFORMATION section. Go
  • Changed the Switching Characteristics condition statement From: 15 kbps devices (SN65HVD73, 74, 75) bit time > 65 ns To: 20 Mbps devices (SN65HVD73, 74, 75) bit time > 50 nsGo
  • Changed the Switching Characteristics condition statement From: 50 kbps devices (SN65HVD76, 77, 78) bit time > 20 ns To: 50 Mbps devices (SN65HVD76, 77, 78) bit time > 20 nsGo
  • Added Figure 4 to Typical Characteristics. Go
  • Added Figure 5 to Typical Characteristics. Go
  • Added Figure 6 to Typical Characteristics. Go
  • Added Figure 7 to Typical Characteristics. Go
  • Added Figure 8 to Typical Characteristics. Go
  • Added Figure 9 to Typical Characteristics. Go
  • Added Application Information section to data sheet.Go

5 Device Comparison Table

PART NUMBER SIGNALING RATE NODES DUPLEX ENABLES
SN65HVD72 Up to 250 kbps 213 Half DE, RE
SN65HVD75 Up to 20 Mbps
SN65HVD78 Up to 50 Mbps 96

6 Pin Configuration and Functions

D Package
8-Pin SOIC
Top View
DGK Package
8-Pin VSSOP
Top View
DRB Package
8-Pin VSON
Top View

Pin Functions

PIN TYPE DESCRIPTION
NAME NUMBER
A 6 Bus I/O Driver output or receiver input (complementary to B)
B 7 Bus I/O Driver output or receiver input (complementary to A)
D 4 Digital input Driver data input
DE 3 Digital input Active-high driver enable
GND 5 Reference potential Local device ground
R 1 Digital output Receive data output
RE 2 Digital input Active-low receiver enable
VCC 8 Supply 3-V to 3.6-V supply

7 Specifications

7.1 Absolute Maximum Ratings

over recommended operating range (unless otherwise specified) (1)
MIN MAX UNIT
Supply voltage, VCC –0.5 5 V
Voltage at A or B inputs –13 16.5
Voltage at D, DE, or RE –0.3 5.7
Voltage input, transient pulse, A and B, through 100 Ω –100 100
Receiver output current –24 24 mA
Junction temperature, TJ 170 °C
Continuous total power dissipation See Power Dissipation
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) By inference from contact discharge results, see Application and Implementation.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±8000 V
Charged device model (CDM), per JEDEC specification JESD22-C101 or ANSI/ESDA/JEDEC JS-002, all pins(2) ±1500
JEDEC Standard 22, Test Method A115 (Machine Model), all pins ±300
IEC 61000-4-2 ESD (Air-Gap Discharge), bus pins and GND (2) ±12000
IEC 61000-4-2 ESD (Contact Discharge), bus pins and GND ±12000
IEC 61000-4-4 EFT (Fast transient or burst) bus pins and GND ±4000
IEC 60749-26 ESD (Human Body Model), bus pins and GND ±15000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC(3) Supply voltage 3 3.3 3.6 V
VI Input voltage at any bus terminal (separately or common mode)(1) –7 12 V
VIH High-level input voltage (driver, driver enable, and receiver enable inputs) 2 VCC V
VIL Low-level input voltage (driver, driver enable, and receiver enable inputs) 0 0.8 V
VID Differential input voltage –12 12 V
IO Output current, driver –60 60 mA
IO Output current, receiver –8 8 mA
RL Differential load resistance 54 60 Ω
CL Differential load capacitance 50 pF
1/tUI Signaling rate SN65HVD72 250 kbps
SN65HVD75 20 Mbps
SN65HVD78 50 Mbps
TA(2) Operating free-air temperature (See Thermal Information) –40 125 °C
TJ Junction temperature –40 150 °C
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet.
(2) Operation is specified for internal (junction) temperatures up to 150°C. Self-heating due to internal power dissipation should be considered for each application. Maximum junction temperature is internally limited by the thermal shutdown (TSD) circuit which disables the driver outputs when the junction temperature reaches 170°C.
(3) Exposure to conditions beyond the recommended operation maximum for extended periods may affect device reliability.

7.4 Thermal Information

THERMAL METRIC(1) SN65HVD72, SN65HVD75, SN65HVD78 UNIT
D (SOIC) DGK (VSSOP) DRB (VSON)
8 PINS
RθJA Junction-to-ambient thermal resistance 110.7 168.7 40 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 54.7 62.2 49.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — 3.9 °C/W
RθJB Junction-to-board thermal resistance 51.3 89.5 15.5 °C/W
ψJT Junction-to-top characterization parameter 9.2 7.4 0.6 °C/W
ψJB Junction-to-board characterization parameter 50.7 87.9 15.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

over recommended operating range (unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|VOD| Driver differential output voltage magnitude RL = 60 Ω, 375 Ω on each output to
–7 V to 12 V		 See Figure 10 1.5 2 V
RL = 54 Ω (RS-485) See Figure 11 1.5 2
RL = 100 Ω (RS-422), TJ ≥ 0°C
VCC ≥ 3.2 V 		2 2.5
Δ|VOD| Change in magnitude of driver differential output voltage RL = 54 Ω, CL = 50 pF –50 0 50 mV
VOC(SS) Steady-state common-mode output voltage Center of two 27-Ω load resistors 1 VCC/2 3 V
ΔVOC Change in differential driver output common-mode voltage Center of two 27-Ω load resistors –50 0 50 mV
VOC(PP) Peak-to-peak driver common-mode output voltage Center of two 27-Ω load resistors 200 mV
COD Differential output capacitance 15 pF
VIT+ Positive-going receiver differential input voltage threshold See (1) –70 –20 mV
VIT– Negative-going receiver differential input voltage threshold –200 –150 See (1) mV
VHYS Receiver differential input voltage threshold hysteresis (VIT+ – VIT–) 50 80 mV
VOH Receiver high-level output voltage IOH = –8 mA 2.4 VCC – 0.3 V
VOL Receiver low-level output voltage IOL = 8 mA 0.2 0.4 V
II Driver input, driver enable, and receiver enable input current –2 2 µA
IOZ Receiver output high-impedance current VO = 0 V or VCC, RE at VCC –1 1 µA
IOS Driver short-circuit output current –160 160 mA
II Bus input current (disabled driver) VCC = 3 to 3.6 V or
VCC = 0 V
DE at 0 V		 SN65HVD72 SN65HVD75 VI = 12 V 75 150 µA
VI = –7 V –100 –40
SN65HVD78 VI = 12 V 240 333
VI = –7 V –267 –180
ICC Supply current (quiescent) Driver and receiver enabled DE = VCC, RE = GND
No load 		750 950 µA
Driver enabled, receiver disabled DE = VCC, RE = VCC
No load 		300 500
Driver disabled, receiver enabled DE = GND, RE = GND
No load		 600 800
Driver and receiver disabled DE = GND, D = open
RE = VCC, No load 		0.1 2
Supply current (dynamic) See Typical Characteristics
TTSD Thermal shutdown junction temperature 170 °C
(1) Under any specific conditions, VIT+ is assured to be at least VHYS higher than VIT–.

7.6 Power Dissipation

PARAMETER TEST CONDITIONS VALUE UNIT
PD Power Dissipation
driver and receiver enabled,
VCC = 3.6 V, TJ = 150°C
50% duty cycle square-wave signal at signaling rate:
  • SN65HVD72 at 250 kbps
  • SN65HVD75 at 20 Mbps
  • SN65HVD78 at 50 Mbps
 Unterminated RL = 300 Ω
CL = 50 pF (driver)		 SN65HVD72 120 mW
SN65HVD75 160
SN65HVD78 200
RS-422 load RL = 100 Ω
CL = 50 pF (driver)		 SN65HVD72 155 mW
SN65HVD75 195
SN65HVD78 230
RS-485 load RL = 54 Ω
CL = 50 pF (driver)		 SN65HVD72 190 mW
SN65HVD75 230
SN65HVD78 260

 
Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale