TPS7A8101 低噪声、高带宽、高 PSRR、低压降 1A 线性稳压器

器件信息⁽¹⁾

Pin Functions

6.1 Absolute Maximum Ratings

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

6.5 Electrical Characteristics

6.6 Typical Characteristics

	NOTE: The Y-axis shows 1% VO per division

Figure 1. Load Regulation

VO = 0.8 V	IO = 750 mA
NOTE: The Y-axis shows 1% VO per division

Figure 3. Line Regulation

IO = 1 A

Figure 5. Dropout Voltage vs Input Voltage

IO = 500 mA

Figure 7. Dropout Voltage vs Input Voltage

VI = 3.6 V

Figure 9. Dropout Voltage vs Temperature

Figure 11. Ground Pin Current vs Load Current

VO = VI – 0.5 V

Figure 13. Current Limit vs Temperature

VI – VO = 1 V	C(IN) = 0 F	C(OUT) = 10 µF
C(NR) = C(BYPASS) = 470 nF

Figure 15. PSRR vs Frequency

VI – VO = 1 V	C(IN) = 0 F	C(OUT) = 10 µF
C(NR) = C(BYPASS) = 470 nF

Figure 17. PSRR vs Frequency

IO = 100 mA

C(IN) = 0 F

Figure 19. PSRR vs Dropout Voltage

VI – VO = 0.5 V	C(OUT) = 10 µF		C(IN) = 10 µF
	24.09 µVRMS (C(NR) = C(BYPASS) = 100 nF)
	23.54 µVRMS (C(NR) = C(BYPASS) = 470 nF)

Figure 21. Output Spectral Noise Density vs Frequency (RMS noise (100 Hz to 100 kHz))

23.54 µVRMS (IO = 100 mA)	C(IN) = 10 µF	VI – VO = 0.5 V
23.71 µVRMS (IO = 750 mA)	C(NR) = 470 nF	C(OUT) = 10 µF
22.78 µVRMS (IO = 1 A)	C(BYPASS) = 470 nF

Figure 23. Output Spectral Noise Density vs Frequency (RMS noise (100 Hz to 100 kHz))

Using the same value of C(NR) and C(BYPASS) in the X-Axis

Figure 25. Start-up Time vs Noise Reduction Capacitance

IO = 100 mA → 1 A → 100 mA

Figure 27. Load Transient Response

	RL = 33 Ω	C(NR) = 470 nF	C(BYPASS) = 470 nF
	C(OUT) = 10 µF	C(IN) = 10 µF
	(1) The internal reference requires approximately 80 ms of rampup time (see Start-Up) from the enable event; therefore, VO fully reaches the target output voltage of 3.3 V in 80 ms from start-up.

Figure 29. Power-Up and Power-Down Response

	NOTE: The Y-axis shows 1% VO per division

Figure 2. Load Regulation Under Light Loads

VO = 0.8 V	IO = 5 mA
NOTE: The Y-axis shows 1% VO per division

Figure 4. Line Regulation Under Light Loads

IO = 750 mA

Figure 6. Dropout Voltage vs Input Voltage

VI = 3.6 V

Figure 8. Dropout Voltage vs Load Current

VO = 0.8 V	IO = 750 mA

Figure 10. Ground Pin Current vs Input Voltage

V(EN) = 0.4 V

Figure 12. Shutdown Current vs Temperature

C(NR) = C(BYPASS) = 470 nF

C(OUT) = 10 µF

C(IN) = 0 F

Figure 14. PSRR vs Frequency

VI – VO = 0.5 V	C(IN) = 0 F	C(OUT) = 10 µF
C(NR) = C(BYPASS) = 470 nF

Figure 16. PSRR vs Frequency

VI – VO = 0.5 V	C(IN) = 0 F	C(OUT) = 10 µF
C(NR) = C(BYPASS) = 470 nF

Figure 18. PSRR vs Frequency

IO = 750 mA

C(IN) = 0 F

Figure 20. PSRR vs Dropout Voltage

25.89 µVRMS (VO = 1.8 V)	C(IN) = 10 µF	VI – VO = 0.5 V
23.54 µVRMS (VO = 2.5 V)	C(NR) = 470 nF	C(OUT) = 10 µF
23.54 µVRMS (VO = 3.3 V)	C(BYPASS) = 470 nF

Figure 22. Output Spectral Noise Density vs Frequency (RMS noise (100 Hz to 100 kHz))

23.54 µVRMS (CO = 10 µF)	C(IN) = 10 µF	VI – VO = 0.5 V
23.91 µVRMS (CO = 22 µF)	C(NR) = 470 nF	C(OUT) = 10 µF
22.78 µVRMS (CO = 100 µF)	C(BYPASS) = 470 nF

Figure 24. Output Spectral Noise Density vs Frequency (RMS noise (100 Hz to 100 kHz))

VI = 3.8 V → 4.8 V → 3.8 V
	IO = 500 mA

Figure 26. Line Transient Response

RL = 33 Ω	C(NR) = 470 nF	C(BYPASS) = 470 nF
C(OUT) = 10 µF	C(IN) = 10 µF

Figure 28. Enable Pulse Response, see (1) in Figure 29

7.1 Overview

The TPS7A8101 device belongs to a family of new-generation LDO regulators that use innovative circuitry to achieve wide bandwidth and high loop gain, resulting in extremely high PSRR (over a 1-MHz range) even with very low headroom (V_I – V_O). A noise-reduction capacitor (C_(NR)) at the NR pin and a bypass capacitor (C_(BYPASS)) decrease noise generated by the bandgap reference to improve PSRR, while a quick-start circuit fast-charges the noise-reduction capacitor. This family of regulators offers sub-bandgap output voltages, current limit, and thermal protection, and is fully specified from –40°C to 125°C.

7.2 Functional Block Diagram

Figure 30. Functional Block Diagram

7.3 Feature Description

7.3.3 Start-Up

Through a lower resistance, the bandgap reference can quickly charge the noise reduction capacitor (C_NR). The TPS7A8101 has a quick-start circuit to quickly charge C_NR, if present; see the . At start-up, this quick-start switch is closed, with only 33 kΩ of resistance between the bandgap reference and the NR pin. The quick-start switch opens approximately 100 ms after any device enabling event, and the resistance between the bandgap reference and the NR pin becomes higher in value (approximately 250 kΩ) to form a very good low-pass (RC) filter. This low-pass filter achieves very good noise reduction for the reference voltage.

Inrush current can be a problem in many applications. The 33-kΩ resistance during the start-up period is intentionally put there to slow down the reference voltage ramp up, thus reducing the inrush current. For example, the capacitance of connecting the recommended C_NR value of 0.47 μF along with the 33-kΩ resistance causes approximately 80-ms RC delay. Start-up time with the other C_NR values can be calculated as:

Equation 1.

Although the noise reduction effect is nearly saturated at 0.47 μF, connecting a C_NR value greater than 0.47 μF can help reduce noise slightly more; however, start-up time will be extremely long because the quick-start switch opens after approximately 100 ms. That is, if C_NR is not fully charged during this 100-ms period, C_NR finishes charging through a higher resistance of 250 kΩ, and takes much longer to fully charge.

A low leakage C_NR should be used; most ceramic capacitors are suitable.

7.4 Device Functional Modes

Driving the EN pin over 1.2 V for V_I from 2.2 V to 3.6 V or 1.35 V for V_I from 3.6 V to 6.5 V turns on the regulator. Driving the EN pin below 0.4 V causes the regulator to enter shutdown mode.

In shutdown, the current consumption of the device is reduced to 0.02 µA typically.

8.1 Application Information

The TPS7A8101 belongs to a family of new generation LDO regulators that use innovative circuitry to achieve wide bandwidth and high loop gain, resulting in extremely high PSRR (over a 1-MHz range) at very low headroom (V_IN – V_OUT). A noise reduction capacitor (C_NR) at the NR pin and a bypass capacitor (C_BYPASS) bypass noise generated by the bandgap reference to improve PSRR, while a quick-start circuit fast-charges the noise reduction capacitor. This family of regulators offers sub-bandgap output voltages, current limit, and thermal protection, and is fully specified from –40°C to 125°C.

8.2 Typical Application

Figure 31 illustrates the connections for the device.

Figure 31. Typical Application Circuit

8.2.2 Detailed Design Procedure

The voltage on the FB pin sets the output voltage and is determined by the values of R₁ and R₂. The values of R₁ and R₂ can be calculated for any voltage using the formula given in Equation 2:

Equation 2.  

Table 2 shows sample resistor values for common output voltages. In Table 2, E96 series resistors are used, and all values meet 1% of the target V_OUT, assuming resistors with zero error. For the actual design, pay attention to any resistor error factors. Using lower values for R₁ and R₂ reduces the noise injected from the FB pin.

8.2.2.1 Output Noise

In most LDOs, the bandgap is the dominant noise source. If a noise reduction capacitor (C_NR) is used with the TPS7A8101, the bandgap does not contribute significantly to noise. Instead, noise is dominated by the output resistor divider and the error amplifier input. If a bypass capacitor (C_BYPASS) across the high-side feedback resistor (R₁) is used with the TPS7A8101 in addition to C_NR, noise from these other sources can also be significantly reduced.

To maximize noise performance in a given application, use a 0.47-μF noise-reduction capacitor plus a 0.47-μF bypass capacitor.

8.2.2.2 Transient Response

As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude but increases duration of the transient response. Line transient performance can be improved by using a larger noise reduction capacitor (C_NR) and/or bypass capacitor (C_BYPASS).

8.2.3 Application Curve

Figure 32. Enable Pulse Response

The device is designed to operate from an input voltage supply range from 2.2 V to 6.5 V. The input voltage range should provide adequate headroom for the device to have a regulated output. This input supply should be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help improve the output noise performance.

10.1 Layout Guidelines

10.2 Layout Example

Figure 33. TPS7A8101 Layout Example

10.3 Thermal Protection

Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage because of overheating.

Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least 35°C above the maximum expected ambient condition of your particular application. This configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.

The internal protection circuitry of the TPS7A8101 has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS7A8101 into thermal shutdown degrades device reliability.

10.4 Power Dissipation

Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad is critical to avoiding thermal shutdown and ensuring reliable operation.

Power dissipation of the device depends on input voltage and load conditions and can be calculated using Equation 3:

Equation 3.

Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output voltage regulation.

On the SON (DRB) package, the primary conduction path for heat is through the exposed pad to the printed-circuit-board (PCB). The pad can be connected to ground or be left floating; however, it should be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device and can be calculated using Equation 4:

Equation 4.

Knowing the maximum R_θJA, the minimum amount of PCB copper area needed for appropriate heatsinking can be estimated using Figure 34.

NOTE:

θ_JA value at board size of 9 in² (that is, 3 in × 3 in) is a JEDEC standard.

Figure 34. θ_JA vs Board Size

Figure 34 shows the variation of θ_JA as a function of ground plane copper area in the board. It is intended only as a guideline to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate actual thermal performance in real application environments.

10.5 Estimating Junction Temperature

Using the thermal metrics Ψ_JT and Ψ_JB, as shown in the Thermal Information table, the junction temperature can be estimated with corresponding formulas (given in Equation 5). For backwards compatibility, an older θ_JC,Top parameter is listed as well.

Equation 5.

Where P_D is the power dissipation shown by Equation 4, T_T is the temperature at the center-top of the IC package, and T_B is the PCB temperature measured 1 mm away from the IC package on the PCB surface (as Figure 35 shows).

Figure 35. Measuring Points for T_T and T_B

For more information about measuring T_T and T_B, see the application note SBVA025, Using New Thermal Metrics, available for download at www.ti.com.

By looking at Figure 36, the new thermal metrics (Ψ_JT and Ψ_JB) have very little dependency on board size. That is, using Ψ_JT or Ψ_JB with Equation 5 is a good way to estimate T_J by simply measuring T_T or T_B, regardless of the application board size.

Figure 36. Ψ_JT and Ψ_JB vs Board Size

For a more detailed discussion of why TI does not recommend using θ_JC(top) to determine thermal characteristics, refer to application report SBVA025, Using New Thermal Metrics, available for download at www.ti.com. For further information, refer to application report SPRA953, IC Package Thermal Metrics, also available on the TI website.