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  • TPS7A8101 低噪声、高带宽、高 PSRR、低压降 1A 线性稳压器

    • ZHCS599B December   2011  – August 2015 TPS7A8101

      PRODUCTION DATA.  

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  • TPS7A8101 低噪声、高带宽、高 PSRR、低压降 1A 线性稳压器
  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Shutdown
      3. 7.3.3 Start-Up
      4. 7.3.4 Undervoltage Lock-Out (UVLO)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Recommended Component Values
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Dropout Voltage
        2. 8.2.1.2 Minimum Load
        3. 8.2.1.3 Input and Output Capacitor Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Noise
        2. 8.2.2.2 Transient Response
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
    2. 10.2 Layout Example
    3. 10.3 Thermal Protection
    4. 10.4 Power Dissipation
    5. 10.5 Estimating Junction Temperature
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 器件命名规则
    2. 11.2 文档支持
      1. 11.2.1 相关文档　
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息
  13. 重要声明
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DATA SHEET

TPS7A8101 低噪声、高带宽、高 PSRR、低压降 1A 线性稳压器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 具有使能功能的低压降 1A 稳压器
  • 可调节输出电压：0.8V 至 6V
  • 宽带宽高 PSRR：
    • 1kHz 时为 80dB
    • 100kHz 时为 60dB
    • 1MHz 时为 54dB
  • 低噪音：23.5μVRMS典型值 (100Hz 至
    100kHz)
  • 与一个 4.7μF 电容搭配工作时保持稳定
  • 出色的负载和线路瞬态响应
  • 总体精度 3%（在负载、线路、温度范围内）
  • 过流和过热保护
  • 极低压降：1A 时的典型值为 170mV
  • 封装方式：3mm x 3mm 小外形尺寸无引线 (SON)-8

2 应用范围

  • 电信基础设施
  • 音频
  • 高速接口 (I/F)（锁相环 (PLL) 和压控振荡器 (VCO)）

3 说明

TPS7A8101是一款低压差线性稳压器(LDO)，此稳压器可在噪音情况下可提供出色的性能以及输出端的电源抑制比(PSRR)。这个LDO使用一个先进的双极CMOS(BiCMOS)工艺和一个功率场效应晶体管(PMOSFET)无源器件来实现极低噪音，优良的瞬态响应，和出色的PSRR性能。

TPS7A8101 器件与 4.7μF 陶瓷输出电容搭配工作时可保持稳定，并且使用了一个精密电压基准和反馈环路，从而在所有负载、线路、过程和温度变化范围内至少实现 3% 的精度。

该器件的额定温度范围为 TJ = –40°C 至 125°C，采用带有散热焊盘的 3mm × 3mm、小外形尺寸无引线 (SON)-8 封装。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
TPS7A8101 SON (8) 3.00mm x 3.00mm
  1. 要了解所有可用封装，请见数据表末尾的可订购产品附录。

典型应用电路

TPS7A8101 pg1_fbd_bvs179.gif

4 修订历史记录

Changes from A Revision (April 2012) to B Revision

  • Added ESD 额定值表，特性 描述 部分，器件功能模式，应用和实施部分，电源相关建议部分，布局部分，器件和文档支持部分以及机械、封装和可订购信息部分Go

Changes from * Revision (December 2011) to A Revision

  • Added new footnote 2 to Thermal Information table, changed footnote 3Go

5 Pin Configuration and Functions

DRB PACKAGE
8-Pin SON With Exposed Thermal Pad
Top View
TPS7A8101 po_bvs135.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
EN 5 I Driving this pin high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. Refer to the Shutdown section for more details. EN must not be left floating and can be connected to IN if not used.
FB 3 I This pin is the input to the control-loop error amplifier and is used to set the output voltage of the device.
GND 4, pad — Ground
IN 7 I Unregulated input supply
8
NR 6 — Connect an external capacitor between this pin and ground to reduce output noise to very low levels. The capacitor also slows down the VOUT ramp (RC softstart).
OUT 1 O Regulator output. A 4.7-μF or larger capacitor of any type is required for stability.
2

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted).(1)
MIN MAX UNIT
Voltage IN –0.3 7 V
FB, NR –0.3 3.6
EN –0.3 VIN + 0.3(2)
OUT –0.3 7
Current OUT Internally Limited A
Temperature Operating virtual junction, TJ –55 150 °C
Storage, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) VEN absolute maximum rating is VIN + 0.3 V or +7 V, whichever is smaller.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VI Input voltage 2.2 6.5 V
IO Output current 0 1 A
TA Operating free air temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS7A8101 UNIT
DRV (SON)
8 PINS
RθJA Junction-to-ambient thermal resistance 47.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 53.9 °C/W
RθJB Junction-to-board thermal resistance 23.4 °C/W
ψJT Junction-to-top characterization parameter 1 °C/W
ψJB Junction-to-board characterization parameter 23.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 7.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Over the operating temperature range of TJ = –40°C to +125°C, VIN = VOUT(TYP) + 0.5 V or 2.2 V (whichever is greater), IOUT = 1 mA, VEN = 2.2 V, COUT = 4.7 μF, CNR = 0.01 μF, and CBYPASS = 0 μF, unless otherwise noted. TPS7A8101 is tested at VOUT = 0.8 V and VOUT = 6 V. Typical values are at TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range(1) 2.2 6.5 V
VNR Internal reference 0.79 0.8 0.81 V
VOUT Output voltage range 0.8 6 V
Output accuracy(2) VOUT + 0.5 V ≤ VIN ≤ 6 V, VIN ≥ 2.5 V,
100 mA ≤ IOUT ≤ 500 mA, 0°C ≤ TJ ≤ 85°C		 -2% 2%
VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.2 V,
100 mA ≤ IOUT ≤ 1 A		 –3% ±0.3% 3%
ΔVO(ΔVI) Line regulation VOUT(NOM) + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.2 V,
IOUT = 100 mA		 150 μV/V
ΔVO(ΔIL) Load regulation 100 mA ≤ IOUT ≤ 1 A 2 μV/mA
VDO Dropout voltage(3) VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.2 V,
IOUT = 500 mA, VFB = GND or VSNS = GND		 250 mV
VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.5 V,
IOUT = 750 mA, VFB = GND or VSNS = GND		 350
VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.5 V,
IOUT = 1 A, VFB = GND or VSNS = GND		 500
ILIM Output current limit VOUT = 0.85 × VOUT(NOM), VIN ≥ 3.3 V 1100 1400 2000 mA
IGND Ground pin current IOUT = 1 mA 60 100 μA
IOUT = 1 A 350
ISHDN Shutdown current (IGND) VEN ≤ 0.4 V, VIN ≥ 2.2 V, RL = 1 kΩ,
0°C ≤ TJ ≤ 85°C		 0.2 2 μA
IFB Feedback pin current VIN = 6.5 V, VFB = 0.8 V 0.02 1 μA
PSRR Power-supply rejection ratio VIN = 4.3 V, VOUT = 3.3 V,
IOUT = 750 mA		 f = 100 Hz 80 dB
f = 1 kHz 82
f = 10 kHz 78
f = 100 kHz 60
f = 1 MHz 54
Vn Output noise voltage BW = 100 Hz to 100 kHz,
VIN = 3.8 V, VOUT = 3.3 V,
IOUT = 100 mA, CNR = CBYPASS = 470 nF		 23.5 μVRMS
VEN(HI) Enable high (enabled) 2.2 V ≤ VIN ≤ 3.6 V, RL = 1 kΩ 1.2 V
3.6 V < VIN ≤ 6.5 V, RL = 1 kΩ 1.35
VEN(LO) Enable low (shutdown) RL = 1 kΩ 0 0.4 V
IEN(HI) Enable pin current, enabled VIN = VEN = 6.5 V 0.02 1 μA
tSTR Start-up time VOUT(NOM) = 3.3 V, VOUT = 0% to 90% VOUT(NOM),
RL = 3.3 kΩ, COUT = 10 μF, CNR = 470 nF		 80 ms
UVLO Undervoltage lockout VIN rising, RL = 1 kΩ 1.86 2 2.10 V
Hysteresis VIN falling, RL = 1 kΩ 75 mV
TSD Thermal shutdown temperature Shutdown, temperature increasing 160 °C
Reset, temperature decreasing 140 °C
TJ Operating junction temperature –40 125 °C
(1) Minimum VIN = VOUT + VDO or 2.2 V, whichever is greater.
(2) The TPS7A8101 does not include external resistor tolerances and it is not tested at this condition: VOUT = 0.8 V, 4.5V ≤ VIN ≤ 6.5 V, and 750 mA ≤ IOUT ≤ 1 A because the power dissipation is greater than the maximum rating of the package.
(3) VDO is not measured for fixed output voltage devices with VOUT < 1.7 V because minimum VIN = 2.2 V.

6.6 Typical Characteristics

At VOnom = 3.3 V, VI = VOnom + 0.5 V or 2.2 V (whichever is greater), IO = 100 mA, V(EN) = VI, C(IN) = 1 μF, C(OUT) = 4.7 μF, and C(NR) = 0.01 μF; all temperature values refer to TJ, unless otherwise noted.
TPS7A8101 tc_load_reg_slvsck0.gif
NOTE: The Y-axis shows 1% VO per division
Figure 1. Load Regulation
TPS7A8101 tc_line_reg_slvsck0.gif
VO = 0.8 V IO = 750 mA
NOTE: The Y-axis shows 1% VO per division
Figure 3. Line Regulation
TPS7A8101 tc_vdo-vin_1a_slvsck0.gif
IO = 1 A
Figure 5. Dropout Voltage vs Input Voltage
TPS7A8101 tc_vdo-vin_500ma_slvsck0.gif
IO = 500 mA
Figure 7. Dropout Voltage vs Input Voltage
TPS7A8101 tc_vdo-tmp_slvsck0.gif
VI = 3.6 V
Figure 9. Dropout Voltage vs Temperature
TPS7A8101 tc_ignd-iout_slvsck0.gif
Figure 11. Ground Pin Current vs Load Current
TPS7A8101 tc_ilim-tmp_slvsck0.gif
VO = VI – 0.5 V
Figure 13. Current Limit vs Temperature
TPS7A8101 D002_SLVSCK0.gif
VI – VO = 1 V C(IN) = 0 F C(OUT) = 10 µF
C(NR) = C(BYPASS) = 470 nF
Figure 15. PSRR vs Frequency
TPS7A8101 D004_SLVSCK0.gif
VI – VO = 1 V C(IN) = 0 F C(OUT) = 10 µF
C(NR) = C(BYPASS) = 470 nF
Figure 17. PSRR vs Frequency
TPS7A8101 tc_psrr-vdo_100ma_slvsck0.gif
IO = 100 mA C(IN) = 0 F
Figure 19. PSRR vs Dropout Voltage
TPS7A8101 D006_SLVSCK0.gif
VI – VO = 0.5 V C(OUT) = 10 µF C(IN) = 10 µF
24.09 µVRMS (C(NR) = C(BYPASS) = 100 nF)
23.54 µVRMS (C(NR) = C(BYPASS) = 470 nF)
Figure 21. Output Spectral Noise Density vs Frequency (RMS noise (100 Hz to 100 kHz))
TPS7A8101 D008_SLVSCK0.gif
23.54 µVRMS (IO = 100 mA) C(IN) = 10 µF VI – VO = 0.5 V
23.71 µVRMS (IO = 750 mA) C(NR) = 470 nF C(OUT) = 10 µF
22.78 µVRMS (IO = 1 A) C(BYPASS) = 470 nF
Figure 23. Output Spectral Noise Density vs Frequency (RMS noise (100 Hz to 100 kHz))
TPS7A8101 D010_SLVSCK0.gif
Using the same value of C(NR) and C(BYPASS) in the X-Axis
Figure 25. Start-up Time vs Noise Reduction Capacitance
TPS7A8101 tc_load_trans_slvsck0.gif
IO = 100 mA → 1 A → 100 mA
Figure 27. Load Transient Response
TPS7A8101 D012_SLVSCK0.gif
RL = 33 Ω C(NR) = 470 nF C(BYPASS) = 470 nF
C(OUT) = 10 µF C(IN) = 10 µF
(1) The internal reference requires approximately 80 ms of rampup time (see Start-Up) from the enable event; therefore, VO fully reaches the target output voltage of 3.3 V in 80 ms from start-up.
Figure 29. Power-Up and Power-Down Response
TPS7A8101 tc_load_reg_light_slvsck0.gif
NOTE: The Y-axis shows 1% VO per division
Figure 2. Load Regulation Under Light Loads
TPS7A8101 tc_line_reg_light_slvsck0.gif
VO = 0.8 V IO = 5 mA
NOTE: The Y-axis shows 1% VO per division
Figure 4. Line Regulation Under Light Loads
TPS7A8101 tc_vdo-vin_750ma_slvsck0.gif
IO = 750 mA
Figure 6. Dropout Voltage vs Input Voltage
TPS7A8101 tc_vdo-iout_slvsck0.gif
VI = 3.6 V
Figure 8. Dropout Voltage vs Load Current
TPS7A8101 tc_ignd-vin_slvsck0.gif
VO = 0.8 V IO = 750 mA
Figure 10. Ground Pin Current vs Input Voltage
TPS7A8101 tc_ishdn-tmp_slvsck0.gif
V(EN) = 0.4 V
Figure 12. Shutdown Current vs Temperature
TPS7A8101 D001_SLVSCK0.gif
C(NR) = C(BYPASS) = 470 nF C(OUT) = 10 µF C(IN) = 0 F
Figure 14. PSRR vs Frequency
TPS7A8101 D003_SLVSCK0.gif
VI – VO = 0.5 V C(IN) = 0 F C(OUT) = 10 µF
C(NR) = C(BYPASS) = 470 nF
Figure 16. PSRR vs Frequency
TPS7A8101 D005_SLVSCK0.gif
VI – VO = 0.5 V C(IN) = 0 F C(OUT) = 10 µF
C(NR) = C(BYPASS) = 470 nF
Figure 18. PSRR vs Frequency
TPS7A8101 tc_psrr-vdo_750ma_slvsck0.gif
IO = 750 mA C(IN) = 0 F
Figure 20. PSRR vs Dropout Voltage
TPS7A8101 D007_SLVSCK0.gif
25.89 µVRMS (VO = 1.8 V) C(IN) = 10 µF VI – VO = 0.5 V
23.54 µVRMS (VO = 2.5 V) C(NR) = 470 nF C(OUT) = 10 µF
23.54 µVRMS (VO = 3.3 V) C(BYPASS) = 470 nF
Figure 22. Output Spectral Noise Density vs Frequency (RMS noise (100 Hz to 100 kHz))
TPS7A8101 D009_SLVSCK0.gif
23.54 µVRMS (CO = 10 µF) C(IN) = 10 µF VI – VO = 0.5 V
23.91 µVRMS (CO = 22 µF) C(NR) = 470 nF C(OUT) = 10 µF
22.78 µVRMS (CO = 100 µF) C(BYPASS) = 470 nF
Figure 24. Output Spectral Noise Density vs Frequency (RMS noise (100 Hz to 100 kHz))
TPS7A8101 tc_line_trans_slvsck0.gif
VI = 3.8 V → 4.8 V → 3.8 V
IO = 500 mA
Figure 26. Line Transient Response
TPS7A8101 D011_SLVSCK0.gif
RL = 33 Ω C(NR) = 470 nF C(BYPASS) = 470 nF
C(OUT) = 10 µF C(IN) = 10 µF
Figure 28. Enable Pulse Response, see (1) in Figure 29

7 Detailed Description

7.1 Overview

The TPS7A8101 device belongs to a family of new-generation LDO regulators that use innovative circuitry to achieve wide bandwidth and high loop gain, resulting in extremely high PSRR (over a 1-MHz range) even with very low headroom (VI – VO). A noise-reduction capacitor (C(NR)) at the NR pin and a bypass capacitor (C(BYPASS)) decrease noise generated by the bandgap reference to improve PSRR, while a quick-start circuit fast-charges the noise-reduction capacitor. This family of regulators offers sub-bandgap output voltages, current limit, and thermal protection, and is fully specified from –40°C to 125°C.

7.2 Functional Block Diagram

TPS7A8101 fbd_adjust_bvs179.gif Figure 30. Functional Block Diagram

7.3 Feature Description

7.3.1 Internal Current Limit

The TPS7A8101 internal current limit helps protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, the device should not be operated in a current limit state for extended periods of time.

The PMOS pass element in the TPS7A8101 has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting may be appropriate.

7.3.2 Shutdown

The enable pin (EN) is active high and is compatible with standard and low voltage, TTL-CMOS levels. When shutdown capability is not required, EN can be connected to IN.

7.3.3 Start-Up

Through a lower resistance, the bandgap reference can quickly charge the noise reduction capacitor (CNR). The TPS7A8101 has a quick-start circuit to quickly charge CNR, if present; see the . At start-up, this quick-start switch is closed, with only 33 kΩ of resistance between the bandgap reference and the NR pin. The quick-start switch opens approximately 100 ms after any device enabling event, and the resistance between the bandgap reference and the NR pin becomes higher in value (approximately 250 kΩ) to form a very good low-pass (RC) filter. This low-pass filter achieves very good noise reduction for the reference voltage.

Inrush current can be a problem in many applications. The 33-kΩ resistance during the start-up period is intentionally put there to slow down the reference voltage ramp up, thus reducing the inrush current. For example, the capacitance of connecting the recommended CNR value of 0.47 μF along with the 33-kΩ resistance causes approximately 80-ms RC delay. Start-up time with the other CNR values can be calculated as:

Equation 1. TPS7A8101 q_tstr_bvs135.gif

Although the noise reduction effect is nearly saturated at 0.47 μF, connecting a CNR value greater than 0.47 μF can help reduce noise slightly more; however, start-up time will be extremely long because the quick-start switch opens after approximately 100 ms. That is, if CNR is not fully charged during this 100-ms period, CNR finishes charging through a higher resistance of 250 kΩ, and takes much longer to fully charge.

A low leakage CNR should be used; most ceramic capacitors are suitable.

7.3.4 Undervoltage Lock-Out (UVLO)

The TPS7A8101 uses an undervoltage lock-out circuit to keep the output shut off until the internal circuitry is operating properly. The UVLO circuit has a de-glitch feature so that it typically ignores undershoot transients on the input if they are less than 50-μs duration.

7.4 Device Functional Modes

Driving the EN pin over 1.2 V for VI from 2.2 V to 3.6 V or 1.35 V for VI from 3.6 V to 6.5 V turns on the regulator. Driving the EN pin below 0.4 V causes the regulator to enter shutdown mode.

In shutdown, the current consumption of the device is reduced to 0.02 µA typically.

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS7A8101 belongs to a family of new generation LDO regulators that use innovative circuitry to achieve wide bandwidth and high loop gain, resulting in extremely high PSRR (over a 1-MHz range) at very low headroom (VIN – VOUT). A noise reduction capacitor (CNR) at the NR pin and a bypass capacitor (CBYPASS) bypass noise generated by the bandgap reference to improve PSRR, while a quick-start circuit fast-charges the noise reduction capacitor. This family of regulators offers sub-bandgap output voltages, current limit, and thermal protection, and is fully specified from –40°C to 125°C.

8.1.1 Recommended Component Values

Table 1. Recommended Capacitor Values

SYMBOL NAME VALUE
CIN Input capacitor 10 µF
COUT Output capacitor 10 µF
CNR Noise reduction capacitor between NR and GND 470 nF
CBYPASS Noise reduction capacitor across R1 470 nF

Table 2. Recommended Feedback Resistor Values for Common Output Voltages

VOUT R1 R2
0.8 V 0 Ω (Short) 10 kΩ
1 V 2.49 kΩ 10 kΩ
1.2 V 4.99 kΩ 10 kΩ
1.5 V 8.87 kΩ 10 kΩ
1.8 V 12.5 kΩ 10 kΩ
2.5 V 21 kΩ 10 kΩ
3.3 V 30.9 kΩ 10 kΩ
5 V 52.3 kΩ 10 kΩ

8.2 Typical Application

Figure 31 illustrates the connections for the device.

TPS7A8101 ai_typ_cir_adj_bvs179.gif Figure 31. Typical Application Circuit

8.2.1 Design Requirements

8.2.1.1 Dropout Voltage

The TPS7A8101 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in its linear region of operation and the input-to-output resistance is the RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS device in dropout behaves the same way as a resistor.

As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. This effect is shown in Figure 19 and Figure 20 in the Typical Characteristics section.

8.2.1.2 Minimum Load

The TPS7A8101 is stable and well-behaved with no output load. Traditional PMOS LDO regulators suffer from lower loop gain at very light output loads. The TPS7A8101 employs an innovative low-current mode circuit to increase loop gain under very light or no-load conditions, resulting in improved output voltage regulation performance down to zero output current.

8.2.1.3 Input and Output Capacitor Requirements

Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to 1-μF low equivalent series resistance (ESR) capacitor across the input supply near the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or if the device is located several inches from the power source. If source impedance is not sufficiently low, a 0.1-μF input capacitor may be necessary to ensure stability.

The TPS7A8101 is designed to be stable with standard ceramic capacitors of capacitance values 4.7 μF or larger. This device is evaluated using a 10-μF ceramic capacitor of 10-V rating, 10% tolerance, X5R type, and 0805 size (2 mm × 1.25 mm).

X5R- and X7R-type capacitors are highly recommended because they have minimal variation in value and ESR over temperature. Maximum ESR should be less than 1 Ω.

8.2.2 Detailed Design Procedure

The voltage on the FB pin sets the output voltage and is determined by the values of R1 and R2. The values of R1 and R2 can be calculated for any voltage using the formula given in Equation 2:

Equation 2.  TPS7A8101 q_vout_bvs135.gif

Table 2 shows sample resistor values for common output voltages. In Table 2, E96 series resistors are used, and all values meet 1% of the target VOUT, assuming resistors with zero error. For the actual design, pay attention to any resistor error factors. Using lower values for R1 and R2 reduces the noise injected from the FB pin.

8.2.2.1 Output Noise

In most LDOs, the bandgap is the dominant noise source. If a noise reduction capacitor (CNR) is used with the TPS7A8101, the bandgap does not contribute significantly to noise. Instead, noise is dominated by the output resistor divider and the error amplifier input. If a bypass capacitor (CBYPASS) across the high-side feedback resistor (R1) is used with the TPS7A8101 in addition to CNR, noise from these other sources can also be significantly reduced.

To maximize noise performance in a given application, use a 0.47-μF noise-reduction capacitor plus a 0.47-μF bypass capacitor.

8.2.2.2 Transient Response

As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude but increases duration of the transient response. Line transient performance can be improved by using a larger noise reduction capacitor (CNR) and/or bypass capacitor (CBYPASS).

8.2.3 Application Curve

TPS7A8101 D011_SLVSCK0.gif
Figure 32. Enable Pulse Response

9 Power Supply Recommendations

The device is designed to operate from an input voltage supply range from 2.2 V to 6.5 V. The input voltage range should provide adequate headroom for the device to have a regulated output. This input supply should be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help improve the output noise performance.

 
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