适用于 EV 和 HEV 的 bq76PL536A-Q1 3 至 6 节锂离子电池监控器和二级保护 IC单元

7.3.1.1 General Features

The integrated 14-bit (unsigned) high-speed successive approximation register (SAR) analog-to-digital converter uses an integrated band-gap reference voltage (V_REF) for the cell and brick measurements. The ADC has a front-end multiplexer for nine inputs – six cells, two temperature sensors, and one general-purpose analog input (GPAI). The GPAI input can further be multiplexed to measure the brick voltage between the BATx pin and VSS or the voltage between the GPAI+ and GPAI– pins.

The ADC and reference are factory trimmed to compensate for gain, offset, and temperature-induced errors for all inputs. The measurement result is not allowed to roll over due to offset error at the top and bottom of the range. For example, a reading near zero does not underflow to 0x03ff due to offset error and vice-versa.

The converter returns 14 valid unsigned magnitude bits in the following format:

<00xxxxxx xxxxxxxx>

Each word is returned in big-endian format in a register pair consisting of two adjacent 8-bit registers. The MSB of the word is located in the lower-address register of the pair, that is, data for cell 1 is returned in registers 0x03 and 0x04 as 00xxxxxx xxxxxxxxb.

7.3.1.2 3-to-6 Series Cell Configuration

When fewer than 6 cells are used, the most-positive cell voltage of the series string should be connected to the BAT1/BAT2 pins, through the RC input network shown in the Typical Application section. Unused VCx inputs should be connected to the next VCx input down until an input connected to a cell is reached – that is, in a four cell stack, VC6 connects to VC5, which connects to VC4 (Figure 13).

The internal multiplexer control can be set to scan only the inputs which are connected to cells, thereby speeding up conversions slightly. The multiplexer is controlled by the ADC_CONTROL[CN2:0] bits.

Figure 13. Connecting < 6 Cells (4 Shown)

7.3.1.3 Cell Voltage Measurements

Use the following formula (all values are in decimal) to convert the returned cell measurement value to a dc voltage (in mV).

Example:

Cell_1 == 3.35 V (3350 mV);
After conversion, REG_03 == 0x22; REG_04 == 0x4d
0x22 × 0x100 + 0x4d = 0x224d (8781.)
8781 × 6250 / 16,383 = 3349.89 mV ≈ 3.35 V

7.3.1.4 GPAI or V_BAT Measurements

The bq76PL536A-Q1 features a differential input to the ADC from two external pins, GPAI+ and GPAI–. The ADC GPAI result register can be configured (via the FUNCTION_CONFIG[GPAI_SRC] to provide a measurement of the voltage on these two pins, or of the brick voltage present between the BATx pins and VC0.

In the bq76PL536A-Q1 device, the V_BAT measurement is taken from the BATx pin to the VC0 pin, and is a separate input to the ADC mux. Because this is a separate input to the ADC, certain common system faults, such as a broken cell wire, can be easily detected using the bq76PL536A-Q1 and simple firmware techniques.

The GPAI measurement can be configured to use one of two references via FUNCTION_CONFIG[GPAI_REF]. Either the internal bandgap (V_REF) or REG50 can be selected. When REG50 is selected, the ADC returns a ratio of the voltage at the inputs and REG50, removing the need for compensation of the REG50 voltage accuracy or drift when used as a source to excite the sensor. When the device is configured to measure V_BAT (FUNCTION_CONFIG[GPAI_SRC] = 1), the device selects VREF automatically and ignores the FUNCTION_CONFIG[GPAI_REF] setting.

7.3.1.5 Temperature Measurement

The bq76PL536A-Q1 can measure the voltage TS1+, TS1– and TS2+, TS2– differential inputs using the ADC. An external thermistor/resistor divider network typically drives these inputs. The TSn inputs use the REG50 output divided down and internally connected as the ADC reference during conversions. This produces a ratiometric result and eliminates the need for compensation or correction of the REG50 voltage drift when used to drive the temperature sensors. The REG50 reference allows an approximate 2.5-V full-scale input at the TSn inputs. The final reading is limited between 0 and 16,383, corresponding to an external ratio of 0 to 0.5.

Two control bits are required for the ADC to convert the TSn input voltages successfully. ADC_CONTROL[TSn] is set to cause the ADC to convert the TSn channel on the next requested conversion cycle. IO_CONTROL[TSn] is set to cause the FET switch connecting the TSn– input to VSS to close, completing the circuit of the voltage divider. The IO_CONTROL[] bits should only be set as needed to conserve power; at high temperatures, thermistor excitation current may be relatively high.

7.3.1.5.1 External Temperature Sensor Support (TS1+, TS1–, TS2+, and TS2–)

The device is intended for use with a nominal 10 kΩ at 25ºC NTC external thermistor (AT103 equivalent) such as the Panasonic ERT-J1VG103FA, a 1% device. A suitable external resistor-capacitor network should be connected to position the response of the thermistor within the range of interest. This is typically R_T= 1.47 kΩ and R_B = 1.82 kΩ (1%) as shown in Figure 14. A parallel bypass capacitor in the range 1 nF to 47 nF placed across the thermistor should be added to reduce noise coupled into the measurement system. The response time delay created by this network should be considered when enabling the respective TS input prior to conversion and setting the OT delay timer. See Figure 14 for details.

Figure 14. Thermistor Connection

7.3.1.6 ADC Band-Gap Voltage Reference

The ADC and protection subsystems use separate and independent internal voltage references. The ADC band gap (V_REF) is nominally 2.5 V. The reference is temperature-compensated and stable.

The internal reference is brought out to the VREF pin for bypassing. A high quality 10-μF capacitor should be connected between the VREF and AGND pins, in very close physical proximity to the device pins, using short track lengths to minimize the effects of track inductance on signal quality. The AGND pin should be connected to VSS. Device VSS connections should be brought to a single point close to the IC to minimize layout-induced errors. The device tab should also be connected to this point, and is a convenient common VSS location. The internal VREF should not be used externally to the device by user circuits.

7.3.1.7 Conversion Control

7.3.1.7.2 Data Ready

The bq76PL536A-Q1 signals that data is ready when the last conversion data has been stored to the associated data result register by asserting the DRDY_S pin (DRDY_H if HOST = 0) if the DRDY_N pin is also asserted
(Figure 15). DRDY_S (DRDY_H) signals are cleared on the next conversion start.

Figure 15. Data-Ready Logic

7.3.1.8 Secondary Protection

The bq76PL536A-Q1 integrates dedicated overvoltage and undervoltage fault detection for each cell and two overtemperature fault-detection inputs for each device. The protection circuits use a separate band-gap reference from the ADC system and operate independently. The protector also uses separate I/O pins from the main communications bus, and therefore is capable of signaling faults in hardware without intervention from the host CPU.

7.3.1.9 Cell Overvoltage Fault Detection (COV)

When the voltage across a cell exceeds the programmed COV threshold for a period of time greater than set in the COV timer (COVT), the COV_FAULT[] flag for that cell is set (Figure 16). The bits in COV_FAULT[] are then ORed into the FAULT[COV] flag, which is then ORed into the DEVICE_STATUS[FAULT] flag, which causes the FAULT_S (_H) pin also to be asserted. The COV flag is latched unless COVT is programmed to 0, in which case the flag follows the fault condition. Care should be taken when using this setting to avoid chatter of the fault status. To reset the FAULT flag, first remove the source of the fault (for example, the overvoltage condition) and then write a 1 to FAULT[COV], followed by a 0 to FAULT[COV]. See (Figure 16) for details.

The voltage trip point is set in the CONFIG_COV register. Set points are spaced every 50 mV. Hysteresis is provided to avoid chatter of the fault sensing. The filter delay time is set in the CONFIG_COVT[] register to prevent false alarms. A start-up deglitch circuit is applied to the timers to prevent false triggering. The deglitch time is 0–50 µs, and introduces a small error in the timing for short times. For both COVT and CUVT, this can cause an error greater than the 10% maximum specified for delays < 500 µs.

Figure 16. COV FAULT Simplified Logic Tree

7.3.1.10 Cell Undervoltage Fault Detection (CUV)

Cell undervoltage detection operates in a similar manner to the COV protection. When the voltage across a cell falls below the programmed CUV threshold (CONFIG_CUV[]) for a period of time greater than CUVT (CONFIG_CUVT[]), the CUV_FAULT[] flag for that cell is set. The bits in CUV_FAULT[] are then ORed into the FAULT[CUV] flag, which is then ORed into the DEVICE_STATUS[FAULT] flag, which causes the FAULT_S (_H) pin also to be asserted. The CUV flag is latched unless CUVT is programmed to 0, in which case the flag follows the fault condition. Care should be taken when using this setting to avoid chatter of the fault status. To reset the FAULT flag, first remove the source of the fault (for example, the overvoltage condition) and then write a 1 to FAULT[CUV], followed by a 0 to FAULT[CUV].

7.3.1.11 Overtemperature Detection

When the temperature input TS1 or TS2 exceeds the programmed OT1 or OT2 threshold (CONFIG_OT[]) for a period of time greater than OTT (CONFIG_OTT[]) the ALERT_STATUS[OT1, OT2] flag is set (Figure 17). The ALERT[] flags are then ORed into the DEVICE_STATUS[ALERT] flag, and the ALERT_S (_H) pin is also asserted. The OT flag is latched unless OTT is programmed to 0, in which case the flag follows the fault condition. Care should be taken when using this setting to avoid chatter of the fault status. To reset the FAULT flag, first remove the source of the alert (for example, the overtemperature condition) and then write a 1 to ALERT[OTn], followed by a 0 to FAULT[OTn].

Figure 17. Simplified Overtemperature Detection Schematic

As shown in Figure 17, the OT thresholds are detectable in 11 steps representing approximately 5°C divisions when a thermistor and gain/offset setting resistors are chosen using the formula in the External Temperature Sensor Support (TS1+, TS1– and TS2+, TS2–) section. A DISABLED setting is also available. This results in an adjustment range from approximately 40°C to 90°C, but the range center can be moved by modifying the R_T value. The steps are spaced in a non-linear fashion to correspond to typical thermistor response curves. Typical accuracy of a few degrees C or better can be achieved (with no additional calibration requirements) by careful selection of the thermistor and resistors.

Each input sensor can be adjusted independently via separate registers CONFIG_OT1[] and CONFIG_OT2[]. The two temperature set points share a common filter delay set in the CONFIG_OTT[] register. A setting of 0 in the CONFIG_OTT[] register causes the fault sensing to be both instantaneous and not latched. All other settings provide a latched ALERT state.

7.3.1.12 Fault and Alert Behavior

When the FAULT_N pin is asserted by the next higher bq76PL536A-Q1 in the stack, then the FAULT_S is also asserted, thereby passing the signal down the array of stacked devices if they are present. FAULT_N should always be connected to the FAULT_S of the next higher device in the stack. If no higher device exists, it should be tied to V_BAT of this bq76PL536A-Q1, either directly or via a pull-up resistor from approximately 10 kΩ to 1 MΩ. The FAULT_x pins are active-high and current flows when asserted. The ALERT_x pins behave in a similar manner. If the FAULT_N pin of the base device (HSEL = 0) becomes asserted, it asserts its FAULT_H signal to the host microcontroller. This signal chain may be used to create an interrupt to the CPU or drive other compatible logic or I/O directly. See Table 3 for further details.

7.3.1.13 Secondary Protector Built-In Self-Test Features

The secondary protector functions have built-in test for verifying the connections through the signal chain of ICs in the stack back to the host CPU. This verifies the wiring, connections, and signal path through the ICs by forcing a current through the signal path.

To implement this feature, host firmware should set the FAULT[FORCE] or ALERT[FORCE] bit in the top-most device in the stack. The device asserts the associated pin on the South interface, and it propagates down the stack, back to the base device. The base device in turn asserts the FAULT_H (ALERT_H) pin to the host, allowing the host to check for the received signal and thereby verify correct operation.

7.3.2.1 Cell Balance Control Safety Timer

The CBx outputs are cleared when the internal safety timer expires. The internal safety timer (CB_TIME) value is programmed in units of seconds or minutes (range set by CB_CTRL bit 7) with an accuracy of ±10%.

The timer begins when any CB_CTRL bit changes from 0 to 1. The timer is reset if all CB_CTRL bits are modified by the host from 1 to 0, or by expiration of the timing period. The timing begins counting the programmed period from start each time the CB_CTRL[] register is programmed from a zero to a non-zero value in the lower six bits. In the example, if the CB_TIME[] is set for 30 s, then one or more bits are set in the CB_CTRL[] register to balance the corresponding cells; then after 10 s, the user firmware sets CB_CTRL[] to 0x00, takes a measurement, and then reprograms CB_CTRL[] with the same or new bit pattern and the timer begins counting 30 s again before expiring and disabling balancing. This restart occurs each time the CB_CTRL bits are set to a non-zero value. If this is done at a greater rate than the balancing period for which timer CB_TIME[] is set, balancing is effectively never disabled – until the timer is either allowed to expire without changing the CB_CTRL[] register to a non-zero value, or the CB_CTRL[] register is set to zero by the user firmware. If the CB_CTRL[] register is not manipulated from zero to non-zero while the timer is running, the timer expires as expected. Alterations of the value from a non-zero to a different non-zero value do not restart the timer (such as, from 0x02 to 0x03, and so forth).

While the timer is running, the host may set or reset any bit in the CB_CTRL[] register at any time, and the CBx output follows the bit.

The host may re-program the timer at any time. The timer must always be programmed to allow the CBx outputs to be asserted. While the timer is non-zero, the CB_CTRL[] settings are reflected at the outputs.

During periods when the timer is actively running (not expired), then DEVICE_STATUS[CBT] is set.

7.3.3.1 Internal Voltage Regulators

The bq76PL536A-Q1 derives power from the BAT pin using several internal low dropout (LDO) voltage regulators. There are separate LDOs for internal analog circuits (5 V at LDOA), digital circuits (5 V at LDOD1 and LDOD2), and external, user circuits (5 V at REG50). The BAT pin should be connected to the most-positive cell input from cell 3, 4, 5, or 6, depending on the number of cells connected. Locate filter capacitors as close to the IC as possible. The internal LDOs and internal V_REF should not be used to power external circuitry, with the exception that LDODx should be used to source power to any external pull-up resistors.

7.3.3.2 Undervoltage Lockout and Power-On Reset

The device incorporates two comparators to detect low V_BAT conditions. The first detects low voltage where some device digital operations are still available. The second, (POR) detects a voltage below which device operation is not ensured.

7.3.3.3 Thermal Shutdown (TSD)

The bq76PL536A-Q1 contains an integrated thermal shutdown circuit whose sensor is located near the REG50 LDO and has a threshold of T_SD. When triggered, the REG50 regulator reduces its output voltage to zero, and the ADC is turned off to conserve power. The thermal shutdown circuit has a built-in hysteresis that delays recovery until the die has cooled slightly. When the thermal shutdown is active, the DEVICE_STATUS[TSD] bit is set. The IO_CONTROL[SLEEP] and ALERT[SLEEP] bits also become set to reduce power consumption.

7.3.3.4 GPIO

The bq76PL536A-Q1 includes a general-purpose input/output pin controlled by the IO_CONTROL[GPIO_OUT] bit. The state of this bit is reflected on the pin. To use the pin as an input, program GPIO_OUT to a 1, and then read the IO_CONTROL[GPIO_IN] bit. A pull-up (10 kΩ–1 MΩ, typ.) is required on this pin if used as an input. If the pull-up is not included in the design, system firmware must program a 0 in IO_CONTROL[GPIO_OUT] to prevent excess current draw from the floating input. Use of a pull-up is recommended in all designs to prevent an unintentional increase in current draw.

7.3.4.1 SPI Communications – Device to Host

Device-to-host (D2H) mode is provided on the SPI interface pins for connection to a local host microcontroller, logic, and so forth. D2H communications operate in voltage mode as a standard SPI interface for ease of connection to the outside world from the bq76PL536A-Q1 device. Standard TTL-compatible logic levels are presented. All relevant SPI timing and performance parameters are met by this interface.

The host interface operates in SPI mode 1, where CPOL = 0 and CPHA = 1. The SPI clock is normally low; data changes on rising edges, and is sampled on the falling edge. All transfers are MSB-first.

The pins of the base IC (only) in a stack should have the SCLK_H and SDI_H pins terminated with pull-ups to minimize current draw of the part if the host ever enters a state where the pins are not driven, that is, held in the high-impedance state by the host. In non-base devices, the _H pins are forced to be all outputs driven low when the HSEL pin is high. In non-base devices, all _H pins should remain unconnected.

The CS_H has a pull-up resistor of approximately 100 kΩ. SDO_H is a 3-state output and is terminated with a weak pull-up.

7.3.4.2 Device-to-Device Vertical Bus (VBUS) Interface

Device-to-device (D2D) communications makes use of a unique, current-mode interface which provides common-mode voltage isolation between successive bq76PL536A-Q1s. This vertical bus (VBUS) is found on the _N and corresponding _S pins. It provides high-speed I/O for both the SPI bus and the direct I/O pins CONV and DRDY. The current-mode interface minimizes the effects of wiring capacitance on the interface speed.

The _S (south-facing) pins connect to the next-lower device (operating at a lower potential) in the stack of bq76PL536A-Q1s. The _N (North facing) pins connect to the next-higher device. The pins cannot be swapped; _S always points South, and _N always point North. The _S and _N pins are interconnected to the pin with the same name, but opposite suffix. All pins operate within the voltages present at the BAT and VSS pins.

The number of devices in the vertical stack and other factors limit the maximum SCLK frequency. Each device imposes an approximately 30-ns delay on the round trip communications speed, that is, from SCLK rising (an input to all devices) to the SDO pin transitioning requires approximately 30 ns per device. The designer must add to this the delay caused by the PCB trace (in turn determined by the material and layout), any connectors in series with the connection, and any other wiring or cabling between devices in the system. To maximize speed, these other system components should be carefully selected to minimize delays and other detrimental effects on signal quality. Wiring and connectors should receive special attention to their transmission line characteristics.

Other factors, which should be considered, are clock duty cycle, clock jitter, temperature effects on clock and system components, user-selected drive level for the level-shift interface, and desired design margin.

The VBUS SPI interface is placed in a low-power mode when CS_H is not asserted on the base device.

The CS_N/S pins are asserted by a logic high on the vertical interface bus (logically inverted from CS_H). This creates a default VBUS CS condition of logic low, reducing current consumption to a minimum.

To reduce power consumption of the SPI interface to a minimum, the SCLK_H and SDI_H should be maintained at a logic low (de-asserted) while CS_H is asserted (low). Most SPI buses are operated this way by microcontrollers. The VBUS versions of these signals are not inverted from the host interface. The device also de-asserts by default the SDO_N/S pins to minimize power consumption.

7.3.4.3 Packet Formats

7.3.4.3.1 Data Read Packet

When the bq76PL536A-Q1 is selected (CS_S [CS_H for first device] is active and the bq76PL536A-Q1 has been addressed) and read request has been initiated, then the data is transmitted on the SDO_S pin to the SDO_N pin of the next device down the stack. This continues to the first device in the stack, where the data in from the SDO_N pin is transmitted to the host via the SDO_H pin. The device supplying the read data generates a CRC as the last byte sent. See Figure 18 and Figure 19 for additional information.

Figure 18. READ Packet Format

Figure 19. READ Packet Detail

7.3.4.3.2 Data Write Packet

When the bq76PL536A-Q1 is selected (CS_S is active and the bq76PL536A-Q1 has been addressed) and a write request has been initiated, the bq76PL536A-Q1 receives data through the SDI_S pin, which is connected to the SDO_N of the lower device. For the first device in the stack, the data is input to the SDI_H pin from the host, and transmitted up the stack on the SDI_S pin to the SDI_N pin of the next higher device. If enabled, the device checks the CRC, which it expects as the last byte sent. If the CRC is valid, no action is taken. If the CRC is invalid or missing, the device asserts the ALERT_S signal to the next lower device, which ripples down the stack to the ALERT_H pin on the lowest device. The host should then take action to clear the condition. See Figure 20 and Figure 21 for details.

Unused or undefined register bits should be written as zeroes.

Figure 20. WRITE Packet Format

Figure 21. WRITE Packet Detail

7.3.4.4 Device Addressing

Each individual device, in the series stack, requires an address to allow communication with it. Each bq76PL536A-Q1 has a CS_S and CS_N that are used in assigning addresses. Once addresses have been assigned, the normal operation of the CS_N/S lines is asserted (logic high) during communications, and the appropriate bq76PL536A-Q1 in the stack responds according to the address transmitted as part of the packet (Figure 22).

When the bq76PL536A-Q1 is reset, the DEVICE_STATUS[AR] (address request) flag is cleared, the address register is set to 0x00, and ALERT_S is set and passed down the stack. In this state, where address = 0x00, the CS_N signal is forced to a de-asserted state (CS is not passed north when an address = 0). In this manner, after a reset the host is assured that a response at address 0x00 is from the first physical device in the stack. After address assignment of the current device, the host is assured that the next response at address 0x00 is from the next physical device in the stack.

Once a valid address is assigned to the device, the CS_N signal responds normally, and follows the CS_H or CS_S signal, propagating to the next device in the stack. Valid addresses are in the range 0x01 through 0x3e. 0x00 is reserved for device discovery after reset. 0x3f is reserved as a broadcast address for all devices.

Once the address is written, the ADDRESS_CONTROL[AR] bit is set which is copied to the DEVICE_STATUS[AR] and also ALERT_S if ALERT_N is also de-asserted. This allows the CS_N pin to follow (asserted) the CS_S pin assertions. The process of addressing can now be repeated as device ‘n’ has a new address and device n+1 has the default address of 0x00, and can be changed to its correct address in the stack.

If a device loses its address through a POR or it is replaced, then this device will be the highest logical device in the stack able to be addressed (0x00), as its CS_N will be disabled and the addressing process is required for this and higher devices.

Figure 22. Address Discovery and Assignment Algorithm

7.4.1.1 SLEEP State Entry (Bit Set)

If a conversion is in progress, the device waits for it to complete, then sets DRDY true (high).

The device sets the ALERT_STATUS[SLEEP] bit, which in turn causes the ALERT pin to be asserted.

The device gates off all other sources of FAULT or ALERT except ALERT[SLEEP]. The existing state of the FAULT and ALERT registers is preserved. The host should service and reset the ALERT generated by the SLEEP bit being set to minimize SLEEP state current draw by writing a 1 to ALERT[SLEEP] followed by a 0 to ALERT[SLEEP]. The ALERT North-South signal chain can draw up to approximately 1 mA of current when active, so this ALERT source should be cleared prior to the host entering the SLEEP state of its own. This signaling is provided to notify the host that the unmonitored/unprotected state is being entered.

The REG50 LDO is shut down and the output is allowed to float. The ADC, its reference, and clocks are disabled. The COV, CUV, and OT circuits are disabled, and their band-gap reference shut off.

IO_CONTROL[TS1:TS2] bits are not modified. The host must also set these bits to zero to minimize current draw of the thermistors themselves.

SPI communications are preserved; all registers may be read or written.

7.4.1.2 SLEEP State Exit (Bit Reset)

VREG50 operation is restored.

COV, CUV, OT circuits are re-enabled.

The ADC circuitry returns to its former state. Note that there is a warm-up delay associated with the ADC enable, the same delay as specified for enabling from a cold start.

The FAULT and ALERT registers are restored to their pre-SLEEP state. If a FAULT or ALERT condition was present prior to SLEEP, the FAULT or ALERT pin is immediately asserted.

IO_CONTROL[TS1:TS2] should be set by the host if the OT function or temperature measurement functions are desired.

7.6.2.1 Read-Only (Group 1)

These registers contain the results of conversions, or device status information set by internal logic. The contents are re-initialized by a device reset as a result of either POR or the RESET command. Contents of the register are changed by either a conversion command, or when there is an internal state change (that is, a fault condition is sensed).

7.6.2.2 Read / Write (Group 2)

The Read/Write register group modifies the operations or behavior of the device, or indicates detailed status in the ALERT_STATUS[] and FAULT_STATUS[] registers (Figure 24). The contents are re-initialized by a device reset as a result of either POR or the RESET command. Contents of the register are changed either by a conversion command, or when there is an internal state change (that is, a fault condition is sensed).

Contents may also be changed by a write from the host CPU to the register. Writes may only modify a single register at a time. If CRCs are enabled, the write packet is buffered until the CRC is checked for correctness. Packets with bad CRCs are discarded without writing the value to the register, after setting the FAULT_STATUS[CRC] flag.

Unused or undefined bits in any register should be written as zeroes, and will always read back as zeroes.

Figure 24. Register Group2 Architecture

7.6.2.3 Read / Write, Initialized From EPROM (Group3)

These registers control the device configuration and functionality. The contents of the registers are initialized from EPROM-stored constants as a result of POR, RESET command, or the RELOAD_SHADOW command. This feature ensures that the secondary protector portion of the device (COV, CUV, OT) is fully functional after any reset, without host CPU involvement. See Figure 25 for a simplified view.

These registers may only be modified by using a special, sequential-write sequence to guard against accidental changes. The value loaded from EPROM at reset (or by command) may be temporarily overwritten by using the special write sequence. The temporary value is overwritten to the programmed EPROM initialization value by the next reset or command to reload. To write to a these protected registers, first write 0x35 to SHDW_CONTROL[], immediately followed by the write to the desired register. Any intervening write cancels the special sequence.

To re-initialize the entire set of Group3 registers to the EPROM defaults, write the value 0x27 to SHDW_CONTROL[].

These registers are protected further against corruption by a ninth parity bit that is automatically updated when the register is written using even parity. If the contents of the register ever become corrupted, the bad parity causes the ALERT_STATUS[PARITY] bit to become set, alerting the host CPU of the problem.

The EPROM-stored constants are programmed by writing the values to the register(s), then applying the programming voltage to the LDODx pins, then issuing the EPROM_WRITE command to register E_EN[]. All Group3 registers are programmed simultaneously, and this operation can only be performed once to the one-time-programmable (OTP) memory cells. The process is not reversible.

Figure 25. Protected Register Group3 Architecture, Simplified View

7.6.2.4 Error Checking and Correcting (ECC) EPROM

The EPROM used to initialize this group is also protected by error-check-and-correct (ECC) logic. The ECC bits provide a highly reliable storage solution in the presence of external disturbances. This feature cannot be disabled by user action. Implementation is fully self-contained and automatic and requires no special computations or provisioning by the user.

When the Group3 contents are permanently written to EPROM, an additional array of hidden ECC-OTP cells is also automatically programmed. The ECC logic implements a Hamming code that automatically corrects all single-bit errors in the EPROM array, and senses additional multi-bit errors. If any corrections are made, the DEVICE_STATUS[ECC_COR] flag bit is set. If any multi-bit errors are sensed, the ALERT_STATUS[ECC_ERR] flag is set. The corrective action or detection is performed anytime the contents of EPROM are loaded into the registers – POR, RESET, or by REFRESH command. Note: The ECC_COR and ECC_ERR bits may glitch during OTP-EPROM writes; this is normal. If this occurs, reset the tripped bit; it should remain cleared.

When a double-bit (uncorrectable) error is found, DEVICE_STATUS[ALERT] is set, the ALERT_S (ALERT_H for bottom stack device) line is activated, and the ALERT_STATUS[] register returns the ECC_ERR and/or I_FAULT bit = 1(true). The device may return erroneous measurement data, and/or fail to detect COV, CUV, or OT faults in this state.

EPROM bits are shipped from the factory set to 0 and must be programmed to the 1 state, as required.

7.6.3.1 DEVICE_STATUS Register (0x00)

The STATUS register provides information about the current state of the bq76PL536A-Q1.

7.6.3.2 GPAI (0x01, 0x02) Register

The GPAI register reports the ADC measurement of GPAI+/GPAI– in units of LSBs.

Bits 15–8 are returned at address 0x01, bits 7–0 at address 0x02.

7.6.3.3 VCELLn Register (0x03…0x0e)

The VCELLn registers report the converted data for cell n, where n = 1 to 6.

Bits 15–8 are returned at odd addresses (for example, 0x03), bits 7–0 at even addresses (for example, 0x04).

7.6.3.4 TEMPERATURE1 Register (0x0f, 0x10)

The TEMPERATURE1 register reports the converted data for TS1+ to TS1–.

Bits 15–8 are returned at odd addresses (for example, 0x0f), bits 7–0 at even addresses (for example, 0x10).

7.6.3.5 TEMPERATURE2 Register (0x11, 0x12)

The TEMPERATURE2 register reports the converted data for TS2+ to TS2–.

Bits 15–8 are returned at odd addresses (for example, 0x11), bits 7–0 at even addresses (for example, 0x12).

7.6.3.6 ALERT_STATUS Register (0x20)

The ALERT_STATUS register provides information about the source of the ALERT signal. The host must clear each alert flag by writing a 1 to the bit that is set. The exception is bit 4, which may be written 1 or 0 as needed to implement self-test of the IC stack and wiring.

7.6.3.7 FAULT_STATUS Register (0x21)

The FAULT_STATUS register provides information about the source of the FAULT signal, see Error Checking and Correcting (ECC) EPROM for more information. The host must clear each fault flag by writing a 1 to the bit that is set. The exception is bit 4, which may be written 1 or 0 as needed to implement self-test of the IC stack and wiring.

7.6.3.8 COV_FAULT Register (0x22)

7.6.3.9 CUV_FAULT Register (0x23)

7.6.3.10 PARITY_H Register (0x24) [PRESULT_A (R/O)]

The PRESULT_A register holds the parity result bits for the first eight Group3 protected registers.

7.6.3.11 PARITY_H Register (0x25) [PRESULT_B (R/O)]

The PRESULT_B register holds the parity result bits for the second eight Group3 protected registers.

7.6.3.12 ADC_CONTROL Register (0x30)

The ADC_CONTROL register controls some features of the bq76PL536A-Q1.

7.6.3.13 IO_CONTROL Register (0x31)

The IO_CONTROL register controls some features of the bq76PL536A-Q1 external I/O pins.

7.6.3.14 CB_CTRL Register (0x32)

The CB_CTRL register determines the internal cell-balance output state.

7.6.3.15 CB_TIME Register (0x33)

The CB_TIME register sets the maximum high (active) time for the cell balance outputs from 0 seconds to 63 minutes. When set to 0, no balancing can occur – balancing is effectively disabled.

7.6.3.16 ADC_CONVERT Register (0x34)

The CONVERT_CTRL register is used to start conversions.

7.6.3.17 SHDW_CTRL Register (0x3a)

The SHDW_CTRL register controls writing to Group3 protected registers. Default at RESET = 0x00.

The value 0x35 must be written to this register to allow writing to Group3 protected registers in the range 0x40–0x4f. The register always returns 0x00 on read. The register is reset to 0x00 after any successful write, including a write to non-Group3 registers. A read operation does not reset this register.

Writing the value 0x27 results in all Group3 protected registers being refreshed from OTP programmed values. The register is reset to 0x00 after the REFRESH is complete.

7.6.3.18 ADDRESS_CONTROL Register (0x3b)

The ADDRESS_CONTROL register allows the host to assign an address to the bq76PL536A-Q1 for communication. The default for this register is 0x00 at RESET.

7.6.3.19 RESET Register (0x3c)

The RESET register allows the host to reset the bq76PL536A-Q1 directly.

Writing 0xa5 causes the device to RESET. Other values are ignored.

7.6.3.20 TEST_SELECT Register (0x3d)

The TEST_SELECT places the SPI port in a special mode useful for debug.

TSEL (b7–b0) is used to place the SPI_H interface pins in a mode to support test/debug of a string of bq76PL536A-Q1 devices. 0 = normal operating mode.

When the sequence 0xa4, 0x25 ("JR") is written on subsequent write cycles, the device enters a special TEST mode useful for stack debugging. Writes to other registers between the required sequence bytes results in the partial sequence being voided; the entire sequence must be written again. POR, RESET, or writing a 0x00 to this register location exits this mode.

In this state, SPI pin SCLK and SDI become outputs and are enabled, and reflect the state of the SCLK_S, SDI_S pins of the device. SDO remains an output. This allows observation of bus traffic mid-string. The lowest device in the string should not be set to operate in this mode.

7.6.3.21 E_EN Register (0x3f)

The E_EN register controls the access to the programming of the integrated OTP EPROM.

This register should be written the value 0x91 to permit writing the USER block of EPROM. Values other than 0x00 and 0x91 are reserved and may result in undefined operation. The next read or write of any type to the device resets (closes) the write window. If a Group3 protected write occurs, the window is closed after the write.

7.6.3.22 FUNCTION_CONFIG Register (0x40)

The FUNCTION_CONFIG sets the default configuration for special features of the device.

7.6.3.23 IO_CONFIG Register (0x41)

The IO_CONFIG sets the default configuration for miscellaneous I/O features of the device.

7.6.3.24 CONFIG_COV Register (0x42)

The CONFIG_COV register determines cell-overvoltage threshold voltage.

7.6.3.25 CONFIG_COVT Register (0x43)

The CONFIG_COVT register determines cell-overvoltage detection delay time.

7.6.3.26 CONFIG_UV Register (0x44)

The CUV register determines cell-undervoltage threshold voltage.

7.6.3.27 CONFIG_CUVT Register (0x45)

The CONFIG_CUVT register determines cell-overvoltage detection delay time.

7.6.3.28 CONFIG_OT Register (0x46)

The CONFIG_OT register holds the configuration of the overtemperature thresholds for the two TS inputs.

For each respective nibble (OT1 or OT2), the value 0x0 disables this function. Other settings program a trip threshold. See the Ratiometric Sensing section for details of setting this register. Values above 0x0b are illegal and should not be used.

7.6.3.29 CONFIG_OTT Register (0x47)

The CONFIG_OTT register determines cell overtemperature detection delay time.

0x01 = 10 ms; each binary increment adds 10 ms until 0xff = 2.55 seconds.

7.6.3.30 USERx Register (0x48–0x4b) (USER1–4)

The four USER registers can be used to store user data. The part does not use these registers for any internal function. They are provided as convenient storage for user S/N, date of manufacture, and so forth.

Table 9. Design Parameters