ZHCS163C August   2011  – February 2016 ADS8528 , ADS8548 , ADS8568

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: General
    6. 7.6  Electrical Characteristics: ADS8528
    7. 7.7  Electrical Characteristics: ADS8548
    8. 7.8  Electrical Characteristics: ADS8568
    9. 7.9  Serial Interface Timing Requirements
    10. 7.10 Parallel Interface Timing Requirements (Read Access)
    11. 7.11 Parallel Interface Timing Requirements (Write Access)
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement information
    1. 8.1 Equivalent Circuits
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog
        1. 9.3.1.1 Analog Inputs
        2. 9.3.1.2 Analog-to-Digital Converter (ADC)
        3. 9.3.1.3 Conversion Clock
        4. 9.3.1.4 CONVST_x
        5. 9.3.1.5 Data Readout and BUSY/INT Signal
        6. 9.3.1.6 Sequential Operation
        7. 9.3.1.7 Reference
      2. 9.3.2 Digital
        1. 9.3.2.1 Device Configuration
        2. 9.3.2.2 Parallel Interface
        3. 9.3.2.3 Serial Interface
        4. 9.3.2.4 Output Data Format
    4. 9.4 Device Functional Modes
      1. 9.4.1 Hardware Mode
      2. 9.4.2 Software Mode
      3. 9.4.3 Daisy-Chain Mode
      4. 9.4.4 Reset and Power-Down Modes
    5. 9.5 Register Maps
      1. 9.5.1 Configuration (CONFIG) Register
        1. 9.5.1.1 CONFIG: Configuration Register (default = 000003FFh)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档　
    2. 13.2 相关链接
    3. 13.3 社区资源
    4. 13.4 商标
    5. 13.5 静电放电警告
    6. 13.6 Glossary
  14. 14机械、封装和可订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage HVDD to AGND –0.3 18 V
HVSS to AGND –18 0.3
AVDD to AGND –0.3 6
DVDD to DGND –0.3 6
Analog input voltage HVSS – 0.3 HVDD + 0.3 V
Reference input voltage with respect to AGND AGND – 0.3 AVDD + 0.3 V
Digital input voltage with respect to DGND DGND – 0.3 DVDD + 0.3 V
Ground voltage difference AGND to DGND ±0.3 V
Input current to all pins except supply ±10 mA
Maximum virtual junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
AVDD Analog supply voltage 4.5 5.0 5.5 V
DVDD Buffer I/O supply voltage 2.7 3.3 5.5 V
HVDD Input positive supply voltage 5.0 15.0 16.5 V
HVSS Input negative supply voltage –16.5 –15.0 –5.0 V
TA Operating ambient temperature range –40 25 125 °C

7.4 Thermal Information

THERMAL METRIC(1) ADS85x8 UNIT
RGC (VQFN) PM (LQFP)
64 PINS 64 PINS
RθJA Junction-to-ambient thermal resistance 22 48.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 9.0 9.4 °C/W
RθJB Junction-to-board thermal resistance 3.6 21.9 °C/W
ψJT Junction-to-top characterization parameter 0.1 0.3 °C/W
ψJB Junction-to-board characterization parameter 2.9 21.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.3 n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics: General

All minimum and maximum specifications are at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5 V (internal), VIN = ±10 V, and fDATA = max, unless otherwise noted. Typical values are at TA = 25°C, HVDD = 15 V, HVSS = –15 V, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
CHXX Bipolar full-scale range RANGE pin, RANGE bit = 0 –4 VREF 4 VREF V
RANGE pin, RANGE bit = 1 –2 VREF 2 VREF
Input capacitance Input range = ±4 VREF 10 pF
Input range = ±2 VREF 20
Input leakage current No ongoing conversion –1 1 μA
Aperture delay 5 ns
Aperture delay matching Common CONVST for all channels 100 ps
Aperture jitter 50 ps
PSRR Power-supply rejection ratio At output code FFFFh, related to HVDD and HVSS –78 dB
REFERENCE VOLTAGE OUTPUT (REFOUT)
VREF Reference voltage 2.5-V operation, REFDAC = 3FFh 2.485 2.5 2.515 V
2.5-V operation, REFDAC = 3FFh at 25°C 2.496 2.5 2.504
3.0-V operation, REFDAC = 3FFh 2.985 3.0 3.015
3.0-V operation, REFDAC = 3FFh at 25°C 2.995 3.0 3.005
dVREF/dT Reference voltage drift ±10 ppm/°C
PSRR Power-supply rejection ratio At output code FFFFh, related to AVDD –77 dB
IREFOUT Output current At dc current –2 2 mA
IREFSC Short-circuit current(1) 50 mA
tREFON Turn-on settling time 10 ms
External load capacitance At REF_xP, REF_xN pins 4.7 10 μF
At REFIO pin 100 470 nF
REFDAC Tuning range Internal reference output voltage range 0.2 VREF VREF V
REFDAC resolution 10 Bits
DNLDAC REFDAC differential nonlinearity –1 ±0.1 1 LSB
INLDAC REFDAC integral nonlinearity –2 ±0.1 2 LSB
VOSDAC REFDAC offset error VREF = 0.5 V (DAC = 0CDh) –4 ±0.65 4 LSB
REFERENCE VOLTAGE INPUT (REFIN)
VREFIN Reference input voltage 0.5 2.5 3.025 V
Input resistance 100 MΩ
Input capacitance 5 pF
Reference input current 1 μA
DIGITAL INPUTS(2) (CMOS with Schmitt-Trigger Logic Family)
High-level input voltage 0.7 DVDD DVDD + 0.3 V
Low-level input voltage DGND – 0.3 0.3 DVDD V
Input current VI = DVDD to DGND –50 50 nA
Input capacitance 5 pF
DIGITAL OUTPUTS(2)
Output capacitance 5 pF
Load capacitance 30 pF
High-impedance-state output current –50 50 nA
Logic family CMOS
VOH High-level output voltage IOH = 100 μA DVDD – 0.6 V
VOL Low-level output voltage IOH = –100 μA DGND + 0.4 V
POWER-SUPPLY REQUIREMENTS
AVDD Analog supply voltage 4.5 5.0 5.5 V
DVDD Buffer I/O supply voltage 2.7 3.3 5.5 V
HVDD Input positive supply voltage 5.0 15.0 16.5 V
HVSS Input negative supply voltage –16.5 –15.0 –5.0 V
IAVDD Analog supply current ADS8528, fDATA = maximum 37.9 50.1 mA
ADS8548, fDATA = maximum 37.3 49.3
ADS8568, fDATA = maximum 36.6 48.4
fDATA = 250 kSPS, auto-sleep mode 20.3 30.0
fDATA = 200 kSPS, auto-sleep mode 17
fDATA = 10 kSPS, normal operation 30
fDATA = 10 kSPS, auto-sleep mode 4.6
Auto-sleep mode, no ongoing conversion,
internal conversion clock		 7.0
Power-down mode 0.03
IDVDD Buffer I/O supply current fDATA = maximum 0.5 2.0 mA
fDATA = 250 kSPS 0.5 1.4
fDATA = 200 kSPS 0.5
fDATA = 10 kSPS 0.4
Auto-sleep mode, no ongoing conversion,
internal conversion clock		 0.35
Power-down mode 0.01
IHVDD Input positive supply current ADS8528, fDATA = maximum 3.0 4.2 mA
ADS8548, fDATA = maximum 2.8 3.9
ADS8568, fDATA = maximum 2.3 3.2
fDATA = 250 kSPS 1.8 2.4
fDATA = 200 kSPS 1.5
fDATA = 10 kSPS 0.4
Auto-sleep mode, no ongoing conversion,
internal conversion clock		 0.45
Power-down mode 0.01
POWER-SUPPLY REQUIREMENTS (continued)
IHVSS Input negative supply current ADS8528, fDATA = maximum 3.4 4.5 mA
ADS8548, fDATA = maximum 3.3 4.4
ADS8568, fDATA = maximum 2.7 3.6
fDATA = 250 kSPS 2.1 2.6
fDATA = 200 kSPS 1.7
fDATA = 10 kSPS 0.4
Auto-sleep mode, no ongoing conversion,
internal conversion clock		 0.35
Power-down mode 0.01
Power dissipation(3) ADS8528, fDATA = maximum 287.1 430.1 mW
ADS8548, fDATA = maximum 279.7 419.1
ADS8568, fDATA = maximum 259.7 389.4
fDATA = 250 kSPS, auto-sleep mode 161.7 255.2
fDATA = 200 kSPS, auto-sleep mode 151.2
fDATA = 10 kSPS, normal operation 163.3
fDATA = 10 kSPS, auto-sleep mode 36.3
Auto-sleep mode, no ongoing conversion,
internal conversion clock		 53.6
Power-down mode 0.6
(1) Reference output current is not limited internally.
(2) Specified by design.
(3) Maximum power dissipation values are specified with HVDD = 15 V and HVSS = –15 V.

7.6 Electrical Characteristics: ADS8528

All minimum and maximum specifications are at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5 V (internal), VIN = ±10 V, and fDATA = max, unless otherwise noted. Typical values are at TA = 25°C, HVDD = 15 V, HVSS = –15 V, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SAMPLING DYNAMICS
Conversion time Internal conversion clock 1.33 μs
fDATA Throughput rate Serial interface, all four SDOx active 480 kSPS
Parallel interface 650
DC ACCURACY
Resolution 12 Bits
No missing codes 12 Bits
INL Integral linearity error(1) –0.75 ±0.2 0.75 LSB
DNL Differential linearity error –0.5 ±0.2 0.5 LSB
Offset error –1.5 ±0.5 1.5 mV
Offset error matching –0.65 0.65 mV
Offset error drift ±3.5 μV/°C
Gain error Referenced to voltage at REFIO –0.5% ±0.25% 0.5%
Gain error matching Between channels of any pair –0.2% 0.2%
Between any two channels –0.4% 0.4%
Gain error drift Referenced to voltage at REFIO ±6 ppm/°C
AC ACCURACY
SNR Signal-to-noise ratio At fIN = 10 kHz 73 73.9 dB
SINAD Signal-to-noise ratio + distortion At fIN = 10 kHz 73 73.8 dB
THD Total harmonic distortion(2) At fIN = 10 kHz –89 –84 dB
SFDR Spurious-free dynamic range At fIN = 10 kHz 84 92 dB
Channel-to-channel isolation At fIN = 10 kHz 120 dB
BW –3-dB small-signal bandwidth In 4-VREF mode 48 MHz
In 2-VREF mode 24
(1) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as the number of LSBs or percentage of the specified full-scale range.
(2) Calculated on the first nine harmonics of the input frequency.

7.7 Electrical Characteristics: ADS8548

All minimum and maximum specifications are at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5 V (internal), VIN = ±10 V, and fDATA = max, unless otherwise noted. Typical values are at TA = 25°C, HVDD = 15 V, HVSS = –15 V, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SAMPLING DYNAMICS
Conversion time Internal conversion clock 1.45 μs
fDATA Throughput rate Serial interface, all four SDOx active 450 kSPS
Parallel interface 600
DC ACCURACY
Resolution 14 Bits
No missing codes 14 Bits
INL Integral linearity error(1) –1 ±0.5 1 LSB
DNL Differential linearity error –1 ±0.25 1 LSB
Offset error –1.5 ±0.5 1.5 mV
Offset error matching –0.65 0.65 mV
Offset error drift ±3.5 μV/°C
Gain error Referenced to voltage at REFIO –0.5% ±0.25% 0.5%
Gain error matching Between channels of any pair –0.2% 0.2%
Between any two channels –0.4% 0.4%
Gain error drift Referenced to voltage at REFIO ±6 ppm/°C
AC ACCURACY
SNR Signal-to-noise ratio At fIN = 10 kHz 84 85 dB
SINAD Signal-to-noise ratio + distortion At fIN = 10 kHz 83 84 dB
THD Total harmonic distortion(2) At fIN = 10 kHz –91 –86 dB
SFDR Spurious-free dynamic range At fIN = 10 kHz 86 92 dB
Channel-to-channel isolation At fIN = 10 kHz 120 dB
BW –3-dB small-signal bandwidth In 4-VREF mode 48 MHz
In 2-VREF mode 24
(1) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as the number of LSBs or percentage of the specified full-scale range.
(2) Calculated on the first nine harmonics of the input frequency.

7.8 Electrical Characteristics: ADS8568

All minimum and maximum specifications are at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5 V (internal), VIN = ±10 V, and fDATA = max, unless otherwise noted. Typical values are at TA = 25°C, HVDD = 15 V, HVSS = –15 V, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SAMPLING DYNAMICS
Conversion time Internal conversion clock 1.7 μs
fDATA Throughput rate Serial interface, all four SDOx active 400 kSPS
Parallel interface 510
DC ACCURACY
Resolution 16 Bits
No missing codes 16 Bits
INL Integral linearity error(1) At TA = –40°C to +85°C, VQFN package (RGC) –3 ±1.5 3 LSB
At TA = –40°C to +125°C, VQFN package (RGC) –4 ±1.5 4
At TA = –40°C to +85°C, LQFP package (PM) –4 ±1.5 4
At TA = –40°C to +125°C, LQFP package (PM) –4.5 ±1.5 4.5
DNL Differential linearity error At TA = –40°C to +85°C –1 ±0.75 1.75 LSB
At TA = –40°C to +125°C –1 ±0.75 2
Offset error –1.5 ±0.5 1.5 mV
Offset error matching –0.65 0.65 mV
Offset error drift ±3.5 μV/°C
Gain error Referenced to voltage at REFIO –0.5% ±0.25% 0.5%
Gain error matching Between channels of any pair –0.2% 0.2%
Between any two channels –0.4% 0.4%
Gain error drift Referenced to voltage at REFIO ±6 ppm/°C
AC ACCURACY
SNR Signal-to-noise ratio At fIN = 10 kHz, TA = –40°C to +85°C 90 91.5 dB
At fIN = 10 kHz, TA = –40°C to +125°C 89 91.5
SINAD Signal-to-noise ratio + distortion At fIN = 10 kHz, TA = –40°C to +85°C 87 90 dB
At fIN = 10 kHz, TA = –40°C to +125°C 86.5 90
THD Total harmonic distortion(2) At fIN = 10 kHz, TA = –40°C to +85°C –94 –90 dB
At fIN = 10 kHz, TA = –40°C to +125°C –94 –89.5
SFDR Spurious-free dynamic range At fIN = 10 kHz, TA = –40°C to +85°C 90 95 dB
At fIN = 10 kHz, TA = –40°C to +125°C 89.5 95
Channel-to-channel isolation At fIN = 10 kHz 120 dB
BW –3-dB small-signal bandwidth In 4-VREF mode 48 MHz
In 2-VREF mode 24
(1) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as the number of LSBs or percentage of the specified full-scale range.

7.9 Serial Interface Timing Requirements

over recommended operating free-air temperature range (TA), AVDD = 5 V, and DVDD = 2.7 V to 5.5 V (unless otherwise noted)(1)
MIN NOM MAX UNIT
tSCVX CONVST_x high to XCLK rising edge setup time
(CLKSEL = 1)		 6 ns
tXCLK External conversion clock period ADS8528 66.67 ns
ADS8548 72.46
ADS8568 85.11
External conversion clock frequency ADS8528 1 15.0 MHz
ADS8548 1 13.8
ADS8568 1 11.75
External conversion clock duty cycle 40% 60%
tCVL CONVST_x low time 20 ns
tACQ Acquisition time 280 ns
Clock cycles per conversion ADS85x8,
tCCLK or tXCLK		 19 20 Cycles
tCONV Conversion time ADS8528, CLKSEL = 0 1.33 μs
ADS8548, CLKSEL = 0 1.45
ADS8568, CLKSEL = 0 1.7
tDCVB CONVST_x high to BUSY high delay 25 ns
tBUFS BUSY low to FS low time ADS85x8, CLKSEL = 1 0 ns
ADS8528, CLKSEL = 0(2) 67
ADS8548, CLKSEL = 0(2) 73
ADS8568, CLKSEL = 0(2) 86
tFSCV Bus access finished to next conversion start time ADS8528 0 ns
ADS8548 20
ADS8568 40
tSCLK Serial clock period 0.022 10 μs
Serial clock frequency 0.1 45 MHz
Serial clock duty cycle 40% 60%
tDMSB FS low to MSB valid delay 12 ns
tHDO Output data to SCLK falling edge hold time 5 ns
tPDDO SCLK falling edge to new data valid propagation delay 17 ns
tDTRI FS high to SDO_x three-state delay 10 ns
tSUDI Input data to SCLK falling edge setup time 3 ns
tHDI Input data to SCLK falling edge hold time 5 ns
(1) All input signals are specified with tR = tF = 1.5 ns (10% to 90% of DVDD) and timed from a voltage level of (VIL + VIH) / 2.
(2) The device runs with an internal conversion clock. Data can be retrieved after the maximum conversion time tCONV(max), independently from the BUSY signal. When referring the data readout to the falling edge of the BUSY signal, tBUFS(min) must be taken into account (see the Data Readout and BUSY/INT Signal section).

7.10 Parallel Interface Timing Requirements (Read Access)

over recommended operating free-air temperature range (TA), AVDD = 5 V, and DVDD = 2.7 V to 5.5 V (unless otherwise noted)(1)
MIN NOM MAX UNIT
tCVL CONVST_x low time 20 ns
tACQ Acquisition time 280 ns
Clock cycles per conversion ADS85x8, tCCLK or tXCLK 19 20 Cycles
tCONV Conversion time ADS8528, CLKSEL = 0 1.33 µs
ADS8548, CLKSEL = 0 1.45
ADS8568, CLKSEL = 0 1.7
tDCVB CONVST_x high to BUSY high delay 25 ns
tBUCS BUSY low to CS low time ADS85x8, CLKSEL = 1 0 ns
ADS8528, CLKSEL = 0(3) 67
ADS8548, CLKSEL = 0(3) 73
ADS8568, CLKSEL = 0(3) 86
tCSCV Bus access finished to next conversion start time(2) ADS8528 0 ns
ADS8548 20
ADS8568 40
tCSRD CS low to RD low time 0 ns
tRDCS RD high to CS high time 0 ns
tRDL RD pulse duration 20 ns
tRDH Minimum time between two read accesses 2 ns
tPDDO RD or CS falling edge to data valid propagation delay 15 ns
tHDO Output data to RD or CS rising edge hold time 5 ns
tDTRI CS high to DB[15:0] three-state delay 10 ns
(1) All input signals are specified with tR = tF = 1.5 ns (10% to 90% of DVDD) and timed from a voltage level of (VIL + VIH) / 2.
(2) See the CS signal or RD, whichever occurs first.
(3) The device runs with an internal conversion clock. Data can be retrieved after the maximum conversion time tCONV(max), independently from the BUSY signal. When referring the data readout to the falling edge of the BUSY signal, tBUCS(min) must be taken into account (see the Data Readout and BUSY/INT Signal section).

7.11 Parallel Interface Timing Requirements (Write Access)

over recommended ambient temperature range (TA), AVDD = 5 V, and DVDD = 2.7 V to 5.5 V (unless otherwise noted)(1)
MIN NOM MAX UNIT
tCSWR CS low to WR low time 0 ns
tWRL WR low pulse duration 15 ns
tWRH Minimum time between two write accesses 10 ns
tWRCS WR high to CS high time 0 ns
tSUDI Output data to WR rising edge setup time 5 ns
tHDI Data output to WR rising edge hold time 5 ns
(1) All input signals are specified with tR = tF = 1.5 ns (10% to 90% of DVDD) and timed from a voltage level of (VIL + VIH) / 2.
ADS8528 ADS8548 ADS8568 tim_serial_bas543.gif Figure 1. Serial Operation Timing Diagram (All Four SDO_x Active)
ADS8528 ADS8548 ADS8568 tim_par_rd_bas543.gif Figure 2. Parallel Read Access Timing Diagram
ADS8528 ADS8548 ADS8568 tim_par_wr_bas543.gif Figure 3. Parallel Write Access Timing Diagram

7.12 Typical Characteristics

graphs are valid for all devices of the family, at TA = 25°C, HVDD = 15 V, HVSS = –15 V, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), VIN = ±10 V, and fDATA = maximum (unless otherwise noted)
ADS8528 ADS8548 ADS8568 G001_BAS543.png
Figure 4. Integral Nonlinearity vs Code
(ADS8528)
ADS8528 ADS8548 ADS8568 G003_BAS543.png
Figure 6. Integral Nonlinearity vs Code
(ADS8548 ±10-VIN Range)
ADS8528 ADS8548 ADS8568 G005_BAS543.png
Figure 8. Differential Nonlinearity vs Code
(ADS8548 ±10-VIN Range)
ADS8528 ADS8548 ADS8568 G007_BAS543.png
Figure 10. Integral Nonlinearity vs Code
(ADS8568 ±10-VIN Range)
ADS8528 ADS8548 ADS8568 G009_BAS543.png
Figure 12. Differential Nonlinearity vs Code
(ADS8568 ±10-VIN Range)
ADS8528 ADS8548 ADS8568 G011_BAS543.png
Figure 14. Offset Error vs Temperature
ADS8528 ADS8548 ADS8568 G013_BAS543.png
Figure 16. PSRR vs Supply Noise Frequency
ADS8528 ADS8548 ADS8568 G015_BAS543.gif
Figure 18. Code Histogram
(ADS8568, 16390 Hits)
ADS8528 ADS8548 ADS8568 G017_BAS543.png
Figure 20. SINAD vs Temperature
ADS8528 ADS8548 ADS8568 G019_BAS543.png
Figure 22. SFDR vs Temperature
ADS8528 ADS8548 ADS8568 G021_BAS543.png
Figure 24. Frequency Spectrum
(ADS8568, 2048-Point FFT, fIN = 10 kHz, ±5-VIN Range)
ADS8528 ADS8548 ADS8568 G023_BAS543.png
Figure 26. Internal Reference Voltage vs
Analog Supply Voltage (2.5-V Mode)
ADS8528 ADS8548 ADS8568 G025_BAS543.png
Figure 28. Internal Reference Voltage vs Temperature
(3.0-V Mode)
ADS8528 ADS8548 ADS8568 G027_BAS543.png
Figure 30. ADS8568 Analog Supply Current vs Data Rate
ADS8528 ADS8548 ADS8568 G029_BAS543.png
Figure 32. ADS8568 Input Supply Current vs Temperature
ADS8528 ADS8548 ADS8568 G031_BAS543.png
Figure 34. ADS8568 Input Supply Current vs Data Rate
ADS8528 ADS8548 ADS8568 G002_BAS543.png
Figure 5. Differential Nonlinearity vs Code
(ADS8528)
ADS8528 ADS8548 ADS8568 G004_BAS543.png
Figure 7. Integral Nonlinearity vs Code
(ADS8548 ±5-VIN Range)
ADS8528 ADS8548 ADS8568 G006_BAS543.png
Figure 9. Differential Nonlinearity vs Code
(ADS8548 ±5-VIN Range)
ADS8528 ADS8548 ADS8568 G008_BAS543.png
Figure 11. Integral Nonlinearity vs Code
(ADS8568 ±5-VIN Range)
ADS8528 ADS8548 ADS8568 G010_BAS543.png
Figure 13. Differential Nonlinearity vs Code
(ADS8568 ±5-VIN Range)
ADS8528 ADS8548 ADS8568 G012_BAS543.png
Figure 15. Gain Error vs Temperature
ADS8528 ADS8548 ADS8568 G014_BAS543.png
Figure 17. Conversion Time vs Temperature
ADS8528 ADS8548 ADS8568 G016_BAS543.png
Figure 19. SNR vs Temperature
ADS8528 ADS8548 ADS8568 G018_BAS543.png
Figure 21. THD vs Temperature
ADS8528 ADS8548 ADS8568 G020_BAS543.png
Figure 23. Frequency Spectrum
(ADS8568, 2048-Point FFT, fIN = 10 kHz, ±10-VIN Range)
ADS8528 ADS8548 ADS8568 G022_BAS543.png
Figure 25. Channel-to-Channel Isolation vs
Input Noise Frequency
ADS8528 ADS8548 ADS8568 G024_BAS543.png
Figure 27. Internal Reference Voltage vs Temperature
(2.5-V Mode)
ADS8528 ADS8548 ADS8568 G026_BAS543.png
Figure 29. ADS8568 Analog Supply Current vs Temperature
ADS8528 ADS8548 ADS8568 G028_BAS543.png
Figure 31. Buffer I/O Supply Current vs Temperature
ADS8528 ADS8548 ADS8568 G030_BAS543.png
Figure 33. ADS8568 Input Supply Current vs
Input Supply Voltage