ADS85x8 具备 8 个基于逐次逼近寄存器 (SAR) 的低功耗 12 位、14 位或 16 位模数转换器 (ADC),每个 ADC 都配有真正的双极输入。这些通道分组为四对,能够以高达 650kSPS 的速率同时采集信号。
这些器件允许选择并行或串行接口,并且支持菊花链连接。可编程基准允许处理幅值最高可达 ±12V 的模拟输入信号。
ADS85x8 系列采用 64 引脚超薄四方扁平无引线 (VQFN) 和薄型四方扁平 (LQFP) 封装,并且支持自动休眠模式,可最大限度地降低功耗。整个系列的额定工作温度范围为 -40℃ 至 +125℃。
器件型号 | 封装 | 封装尺寸(标称值) |
---|---|---|
ADS85x8 | VQFN (64) | 9.00mm x 9.00mm |
LQFP (64) | 10.00mm x 10.00mm |
Changes from B Revision (November 2015) to C Revision
Changes from A Revision (October 2011) to B Revision
Changes from * Revision (August 2011) to A Revision
PIN | TYPE(1) | DESCRIPTION | ||
---|---|---|---|---|
NAME | NO. | PARALLEL INTERFACE (PAR/SER = 0) | SERIAL INTERFACE (PAR/SER = 1) | |
AGND | 5, 15, 44, 51, 58, 62 | P | Analog ground; connect to the analog ground plane. | |
ASLEEP | 36 | DI | Auto-sleep enable input. When low, the device operates in normal mode. When high, the device functions in auto-sleep mode where the hold mode and the actual conversion is activated six conversion clock (tCCLK) cycles after issuing a conversion start using a CONVST_x. This mode is recommended to save power if the device runs at a lower data rate; see the Reset and Power-Down Modes section for more details. |
|
AVDD | 4, 14, 45, 52, 57, 61 | P | Analog power supply. Decouple according to the Power Supply Recommendations section. |
|
BUSY/INT | 35 | DO | When CONFIG bit C27 = 0 (BUSY/INT), this pin is a converter busy status output. This pin transitions high when a conversion is started and transitions low for a single conversion clock cycle (tCCLK) whenever a channel pair conversion is completed and stays low when the conversion of the last channel pair completes. When bit C27 = 1 (BUSY/INT in CONFIG), this pin is an interrupt output. This pin transitions high after a conversion completes and remains high until the next read access. This mode can only be used if all eight channels are sampled simultaneously (all CONVST_x tied together). The polarity of the BUSY/INT output can be changed using the C26 bit (BUSY L/H) in the Configuration register. |
|
CH_A0 | 42 | AI | Analog input of channel A0; channel A is the master channel pair that is always active. The input voltage range is controlled by the RANGE pin in hardware mode or by Configuration register (CONFIG) bit C24 (RANGE_A) in software mode. In cases where channel pairs of the device are used at different data rates, channel pair A must always run at the highest data rate. |
|
CH_A1 | 47 | AI | Analog input of channel A1; channel A is the master channel pair that is always active. The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C24 (RANGE_A) in software mode. In cases where channel pairs of the device are used at different data rates, channel pair A must always run at the highest data rate. |
|
CH_B0 | 49 | AI | Analog input of channel B0. The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C23 (RANGE_B) in software mode. | |
CH_B1 | 54 | AI | Analog input of channel B1. The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C23 (RANGE_B) in software mode. | |
CH_C0 | 64 | AI | Analog input of channel C0. The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C21 (RANGE_C) in software mode. | |
CH_C1 | 59 | AI | Analog input of channel C1. The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C21 (RANGE_C) in software mode. | |
CH_D0 | 7 | AI | Analog input of channel D0.The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C19 (RANGE_D) in software mode. This pin can be powered down using CONFIG bit C18 (PD_D) in software mode. | |
CH_D1 | 2 | AI | Analog input of channel D1.The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C19 (RANGE_D) in software mode. This pin can be powered down using CONFIG bit C18 (PD_D) in software mode. | |
CONVST_A | 37 | DI | Conversion start of channel pair A. The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_A[1:0]. This signal resets the internal channel state machine that causes the data output to start with conversion results of channel A0 with the next read access. |
|
CONVST_B | 38 | DI | Conversion start of channel pair B. The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_B[1:0]. |
|
CONVST_C | 39 | DI | Conversion start of channel pair C. The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_C[1:0]. |
|
CONVST_D | 40 | DI | Conversion start of channel pair D. The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_D[1:0]. |
|
CS/FS | 13 | DI, DI | Chip-select input. When low, the parallel interface is enabled. When high, the interface is disabled. |
Frame synchronization. The FS falling edge controls the frame transfer. |
DB0/DCIN_D | 33 | DIO, DI | Data bit 0 (LSB) input/output | When DCEN = 1 and SEL_CD = 1, this pin is the daisy-chain data input for SDO_D of the previous device in the chain. When DCEN = 0, connect to DGND. |
DB1/DCIN_C | 32 | DIO, DI | Data bit 1 input/output | When DCEN = 1 and SEL_CD = 1, this pin is the daisy-chain data input for SDO_C of the previous device in the chain. When DCEN = 0, connect to DGND. |
DB2/DCIN_B | 31 | DIO, DI | Data bit 2 input/output | When DCEN = 1 and SEL_B = 1, this pin is the daisy-chain data input for SDO_B of the previous device in the chain. When DCEN = 0, connect to DGND. |
DB3/DCIN_A | 30 | DIO, DI | Data bit 3 input/output | When DCEN = 1, this pin is the daisy-chain data input for SDO_A of the previous device in the chain. When DCEN = 0, connect to DGND. |
DB4 | 29 | DIO | Data bit 4 input/output | Connect to DGND |
DB5/SEL_CD | 28 | DIO, DI | Data bit 5 input/output | Select SDO_C and SDO_D input. When high, data from channel pair C are available on SDO_C and data from channel pair D are available on SDO_D. When low and SEL_B = 1, data from channel pairs A and C are available on SDO_A and data from channel pairs B and D are available on SDO_B. When low and SEL_B = 0, data from all eight channels are available on SDO_A. |
DB6/SEL_B | 27 | DIO, DI | Data bit 6 input/output | Select SDO_B input. When low, SDO_B is disabled and data from all eight channels are only available through SDO_A. When high and SEL_CD = 0, data from channel pairs B and D are available on SDO_B. When SEL_CD = 1, data from channel pair B are available on SDO_B. |
DB7 | 26 | DIO | Data bit 7 input/output | Must be connected to DGND |
DB8/DCEN | 23 | DIO, DI | Data bit 8 input/output | Daisy-chain enable input. When high, DB[3:0] serve as daisy-chain inputs DCIN_[A:D]. If daisy-chain mode is not used, connect to DGND. |
DB9/SDI | 22 | DIO, DI | Data bit 9 input/output | Hardware mode (HW/SW = 0): connect to DGND. Software mode (HW/SW = 1): serial data input. |
DB10/SCLK | 21 | DIO, DI | Data bit 10 input/output | Serial interface clock input. |
DB11/ REFBUFEN |
20 | DIO, DI | Data bit 11 input/output. Output is MSB for the ADS8528. |
Hardware mode (HW/SW = 0): reference buffer enable input. When low, all internal reference buffers are enabled (mandatory if internal reference is used). When high, all reference buffers are disabled. |
Software mode (HW/SW = 1): connect to DGND or DVDD. The internal reference buffers are controlled by CONFIG bit C14 (REFBUFEN). |
||||
DB12/SDO_A | 19 | DIO, DO | Data bit 12 input/output. Output is sign extension for the ADS8528. |
Data output for channel pair A. When SEL_CD = 0, data from channel pair C are also available on this output. When SEL_CD = 0 and SEL_B = 0, SDO_A functions as single data output for all eight channels. |
DB13/SDO_B | 18 | DIO, DO | Data bit 13 input/output. Output is sign extension for the ADS8528 and MSB for the ADS8548. |
When SEL_B = 1, this pin is the data output for channel pair B. When SEL_B = 0, tie this pin to DGND. When SEL_CD = 0, data from channel pair D are also available on this output. |
DB14/SDO_C | 17 | DIO, DO | Data bit 14 input/output. Output is sign extension for the ADS8528 and ADS8548. |
When SEL_CD = 1, this pin is the data output for channel pair C. When SEL_CD = 0, tie this pin to DGND. |
DB15/SDO_D | 16 | DIO, DO | Data bit 15 (MSB) input/output. Output is sign extension for the ADS8528 and ADS8548. |
When SEL_CD = 1, this pin is the data output for channel pair D. When SEL_CD = 0, tie this pin to DGND. |
DGND | 24 | P | Buffer I/O ground, connect to digital ground plane | |
DVDD | 25 | P | Buffer I/O supply, connect to digital supply. Decouple according to the Power Supply Recommendations section. |
|
HVDD | 48 | P | Positive supply voltage for the analog inputs. Decouple according to the Power Supply Recommendations section. |
|
HVSS | 1 | P | Negative supply voltage for the analog inputs. Decouple according to the Power Supply Recommendations section. |
|
HW/SW | 41 | DI | Mode selection input. When low, hardware mode is selected and the device functions according to the settings of the external pins. When high, software mode is selected and the device is configured by writing to the Configuration register (CONFIG). |
|
PAR/SER | 8 | DI | Interface mode selection input. When low, the parallel interface is selected. When high, the serial interface is enabled. |
|
RANGE/XCLK | 34 | DI/DI/DO | Hardware mode (HW/SW = 0): analog input voltage range select input. When low, the analog input voltage range is ±4 VREF. When high, the analog input voltage range is ±2 VREF. |
|
Software mode (HW/SW = 1): this pin is an external conversion clock input if CONFIG bit C29 = 1 (CLKSEL); or an internal conversion clock output if CONFIG bit C28 = 1 (CLKOUT_EN). If this pin is not used, connect to DGND. |
||||
RD | 12 | DI/DI | Read data input. When low, the parallel data output is enabled (if CS = 0). When high, the data output is disabled. |
Must be connected to DGND. |
REFAN | 46 | AI | Decoupling capacitor input for reference of channel pair A. Connect to the decoupling capacitor and AGND according to the Power Supply Recommendations section. |
|
REFAP | 43 | AI | Decoupling capacitor input for reference of channel pair A. Connect to the decoupling capacitor according to the Power Supply Recommendations section. |
|
REFBN | 53 | AI | Decoupling capacitor input for reference of channel pair B. Connect to the decoupling capacitor and AGND according to the Power Supply Recommendations section. |
|
REFBP | 50 | AI | Decoupling capacitor input for reference of channel pair B. Connect to the decoupling capacitor according to the Power Supply Recommendations section. |
|
REFCN | 60 | AI | Decoupling capacitor input for reference of channel pair C. Connect to the decoupling capacitor and AGND according to the Power Supply Recommendations section. |
|
REFCP | 63 | AI | Decoupling capacitor input for reference of channel pair C. Connect to the decoupling capacitor according to the Power Supply Recommendations section. |
|
REFDN | 3 | AI | Decoupling capacitor input for reference of channel pair D. Connect to the decoupling capacitor and AGND according to the Power Supply Recommendations section. |
|
REFDP | 6 | AI | Decoupling capacitor input for the channel pair D reference. Connect to the decoupling capacitor according to the Power Supply Recommendations section. |
|
REFEN/WR | 11 | DI/DI | Hardware mode (HW/SW = 0): internal reference enable input. When high, the internal reference is enabled (the reference buffers are also enabled). When low, the internal reference is disabled and an external reference is applied at REFIO. |
Hardware mode (HW/SW = 0): internal reference enable input. When high, the internal reference is enabled (the reference buffers are also enabled). When low, the internal reference is disabled and an external reference is applied at REFIO. |
Software mode (HW/SW = 1): write input. The parallel data input is enabled when CS and WR are low. The internal reference is enabled by CONFIG bit C15 (REFEN). |
Software mode (HW/SW = 1): connect to DGND or DVDD. The internal reference is enabled by CONFIG bit C15 (REFEN). | |||
REFIO | 56 | AIO | Reference voltage input/output. The internal reference is enabled by the REFEN/WR pin in hardware mode or by CONFIG bit C15 (REFEN) in software mode. The output value is controlled by the internal digital-to-analog converter (DAC), CONFIG bits C[9:0]. Connect to a decoupling capacitor according to the Power Supply Recommendations section. |
|
REFN | 55 | AI | Negative reference input/output pin. Connect to a decoupling capacitor and AGND according to the Power Supply Recommendations section. |
|
RESET | 10 | DI | Reset input, active high. This pin aborts any ongoing conversions and resets the internal Configuration register (CONFIG) to 000003FFh. A valid reset pulse must be at least 50 ns long. |
|
STBY | 9 | DI | Hardware mode (HW/SW = 0): standby mode input. When low, the entire device is powered down (including the internal conversion clock source and reference). When high, the device operates in normal mode. |
|
Software mode (HW/SW = 1): connect to DGND or DVDD. The standby mode can be activated using CONFIG bit C25 (STBY). |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2500 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
AVDD | Analog supply voltage | 4.5 | 5.0 | 5.5 | V |
DVDD | Buffer I/O supply voltage | 2.7 | 3.3 | 5.5 | V |
HVDD | Input positive supply voltage | 5.0 | 15.0 | 16.5 | V |
HVSS | Input negative supply voltage | –16.5 | –15.0 | –5.0 | V |
TA | Operating ambient temperature range | –40 | 25 | 125 | °C |
THERMAL METRIC(1) | ADS85x8 | UNIT | ||
---|---|---|---|---|
RGC (VQFN) | PM (LQFP) | |||
64 PINS | 64 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 22 | 48.5 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 9.0 | 9.4 | °C/W |
RθJB | Junction-to-board thermal resistance | 3.6 | 21.9 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.1 | 0.3 | °C/W |
ψJB | Junction-to-board characterization parameter | 2.9 | 21.4 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 0.3 | n/a | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ANALOG INPUT | ||||||
CHXX | Bipolar full-scale range | RANGE pin, RANGE bit = 0 | –4 VREF | 4 VREF | V | |
RANGE pin, RANGE bit = 1 | –2 VREF | 2 VREF | ||||
Input capacitance | Input range = ±4 VREF | 10 | pF | |||
Input range = ±2 VREF | 20 | |||||
Input leakage current | No ongoing conversion | –1 | 1 | μA | ||
Aperture delay | 5 | ns | ||||
Aperture delay matching | Common CONVST for all channels | 100 | ps | |||
Aperture jitter | 50 | ps | ||||
PSRR | Power-supply rejection ratio | At output code FFFFh, related to HVDD and HVSS | –78 | dB | ||
REFERENCE VOLTAGE OUTPUT (REFOUT) | ||||||
VREF | Reference voltage | 2.5-V operation, REFDAC = 3FFh | 2.485 | 2.5 | 2.515 | V |
2.5-V operation, REFDAC = 3FFh at 25°C | 2.496 | 2.5 | 2.504 | |||
3.0-V operation, REFDAC = 3FFh | 2.985 | 3.0 | 3.015 | |||
3.0-V operation, REFDAC = 3FFh at 25°C | 2.995 | 3.0 | 3.005 | |||
dVREF/dT | Reference voltage drift | ±10 | ppm/°C | |||
PSRR | Power-supply rejection ratio | At output code FFFFh, related to AVDD | –77 | dB | ||
IREFOUT | Output current | At dc current | –2 | 2 | mA | |
IREFSC | Short-circuit current(1) | 50 | mA | |||
tREFON | Turn-on settling time | 10 | ms | |||
External load capacitance | At REF_xP, REF_xN pins | 4.7 | 10 | μF | ||
At REFIO pin | 100 | 470 | nF | |||
REFDAC | Tuning range | Internal reference output voltage range | 0.2 VREF | VREF | V | |
REFDAC resolution | 10 | Bits | ||||
DNLDAC | REFDAC differential nonlinearity | –1 | ±0.1 | 1 | LSB | |
INLDAC | REFDAC integral nonlinearity | –2 | ±0.1 | 2 | LSB | |
VOSDAC | REFDAC offset error | VREF = 0.5 V (DAC = 0CDh) | –4 | ±0.65 | 4 | LSB |
REFERENCE VOLTAGE INPUT (REFIN) | ||||||
VREFIN | Reference input voltage | 0.5 | 2.5 | 3.025 | V | |
Input resistance | 100 | MΩ | ||||
Input capacitance | 5 | pF | ||||
Reference input current | 1 | μA | ||||
DIGITAL INPUTS(2) (CMOS with Schmitt-Trigger Logic Family) | ||||||
High-level input voltage | 0.7 DVDD | DVDD + 0.3 | V | |||
Low-level input voltage | DGND – 0.3 | 0.3 DVDD | V | |||
Input current | VI = DVDD to DGND | –50 | 50 | nA | ||
Input capacitance | 5 | pF | ||||
DIGITAL OUTPUTS(2) | ||||||
Output capacitance | 5 | pF | ||||
Load capacitance | 30 | pF | ||||
High-impedance-state output current | –50 | 50 | nA | |||
Logic family | CMOS | |||||
VOH | High-level output voltage | IOH = 100 μA | DVDD – 0.6 | V | ||
VOL | Low-level output voltage | IOH = –100 μA | DGND + 0.4 | V | ||
POWER-SUPPLY REQUIREMENTS | ||||||
AVDD | Analog supply voltage | 4.5 | 5.0 | 5.5 | V | |
DVDD | Buffer I/O supply voltage | 2.7 | 3.3 | 5.5 | V | |
HVDD | Input positive supply voltage | 5.0 | 15.0 | 16.5 | V | |
HVSS | Input negative supply voltage | –16.5 | –15.0 | –5.0 | V | |
IAVDD | Analog supply current | ADS8528, fDATA = maximum | 37.9 | 50.1 | mA | |
ADS8548, fDATA = maximum | 37.3 | 49.3 | ||||
ADS8568, fDATA = maximum | 36.6 | 48.4 | ||||
fDATA = 250 kSPS, auto-sleep mode | 20.3 | 30.0 | ||||
fDATA = 200 kSPS, auto-sleep mode | 17 | |||||
fDATA = 10 kSPS, normal operation | 30 | |||||
fDATA = 10 kSPS, auto-sleep mode | 4.6 | |||||
Auto-sleep mode, no ongoing conversion, internal conversion clock |
7.0 | |||||
Power-down mode | 0.03 | |||||
IDVDD | Buffer I/O supply current | fDATA = maximum | 0.5 | 2.0 | mA | |
fDATA = 250 kSPS | 0.5 | 1.4 | ||||
fDATA = 200 kSPS | 0.5 | |||||
fDATA = 10 kSPS | 0.4 | |||||
Auto-sleep mode, no ongoing conversion, internal conversion clock |
0.35 | |||||
Power-down mode | 0.01 | |||||
IHVDD | Input positive supply current | ADS8528, fDATA = maximum | 3.0 | 4.2 | mA | |
ADS8548, fDATA = maximum | 2.8 | 3.9 | ||||
ADS8568, fDATA = maximum | 2.3 | 3.2 | ||||
fDATA = 250 kSPS | 1.8 | 2.4 | ||||
fDATA = 200 kSPS | 1.5 | |||||
fDATA = 10 kSPS | 0.4 | |||||
Auto-sleep mode, no ongoing conversion, internal conversion clock |
0.45 | |||||
Power-down mode | 0.01 | |||||
POWER-SUPPLY REQUIREMENTS (continued) | ||||||
IHVSS | Input negative supply current | ADS8528, fDATA = maximum | 3.4 | 4.5 | mA | |
ADS8548, fDATA = maximum | 3.3 | 4.4 | ||||
ADS8568, fDATA = maximum | 2.7 | 3.6 | ||||
fDATA = 250 kSPS | 2.1 | 2.6 | ||||
fDATA = 200 kSPS | 1.7 | |||||
fDATA = 10 kSPS | 0.4 | |||||
Auto-sleep mode, no ongoing conversion, internal conversion clock |
0.35 | |||||
Power-down mode | 0.01 | |||||
Power dissipation(3) | ADS8528, fDATA = maximum | 287.1 | 430.1 | mW | ||
ADS8548, fDATA = maximum | 279.7 | 419.1 | ||||
ADS8568, fDATA = maximum | 259.7 | 389.4 | ||||
fDATA = 250 kSPS, auto-sleep mode | 161.7 | 255.2 | ||||
fDATA = 200 kSPS, auto-sleep mode | 151.2 | |||||
fDATA = 10 kSPS, normal operation | 163.3 | |||||
fDATA = 10 kSPS, auto-sleep mode | 36.3 | |||||
Auto-sleep mode, no ongoing conversion, internal conversion clock |
53.6 | |||||
Power-down mode | 0.6 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SAMPLING DYNAMICS | ||||||
Conversion time | Internal conversion clock | 1.33 | μs | |||
fDATA | Throughput rate | Serial interface, all four SDOx active | 480 | kSPS | ||
Parallel interface | 650 | |||||
DC ACCURACY | ||||||
Resolution | 12 | Bits | ||||
No missing codes | 12 | Bits | ||||
INL | Integral linearity error(1) | –0.75 | ±0.2 | 0.75 | LSB | |
DNL | Differential linearity error | –0.5 | ±0.2 | 0.5 | LSB | |
Offset error | –1.5 | ±0.5 | 1.5 | mV | ||
Offset error matching | –0.65 | 0.65 | mV | |||
Offset error drift | ±3.5 | μV/°C | ||||
Gain error | Referenced to voltage at REFIO | –0.5% | ±0.25% | 0.5% | ||
Gain error matching | Between channels of any pair | –0.2% | 0.2% | |||
Between any two channels | –0.4% | 0.4% | ||||
Gain error drift | Referenced to voltage at REFIO | ±6 | ppm/°C | |||
AC ACCURACY | ||||||
SNR | Signal-to-noise ratio | At fIN = 10 kHz | 73 | 73.9 | dB | |
SINAD | Signal-to-noise ratio + distortion | At fIN = 10 kHz | 73 | 73.8 | dB | |
THD | Total harmonic distortion(2) | At fIN = 10 kHz | –89 | –84 | dB | |
SFDR | Spurious-free dynamic range | At fIN = 10 kHz | 84 | 92 | dB | |
Channel-to-channel isolation | At fIN = 10 kHz | 120 | dB | |||
BW | –3-dB small-signal bandwidth | In 4-VREF mode | 48 | MHz | ||
In 2-VREF mode | 24 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SAMPLING DYNAMICS | ||||||
Conversion time | Internal conversion clock | 1.45 | μs | |||
fDATA | Throughput rate | Serial interface, all four SDOx active | 450 | kSPS | ||
Parallel interface | 600 | |||||
DC ACCURACY | ||||||
Resolution | 14 | Bits | ||||
No missing codes | 14 | Bits | ||||
INL | Integral linearity error(1) | –1 | ±0.5 | 1 | LSB | |
DNL | Differential linearity error | –1 | ±0.25 | 1 | LSB | |
Offset error | –1.5 | ±0.5 | 1.5 | mV | ||
Offset error matching | –0.65 | 0.65 | mV | |||
Offset error drift | ±3.5 | μV/°C | ||||
Gain error | Referenced to voltage at REFIO | –0.5% | ±0.25% | 0.5% | ||
Gain error matching | Between channels of any pair | –0.2% | 0.2% | |||
Between any two channels | –0.4% | 0.4% | ||||
Gain error drift | Referenced to voltage at REFIO | ±6 | ppm/°C | |||
AC ACCURACY | ||||||
SNR | Signal-to-noise ratio | At fIN = 10 kHz | 84 | 85 | dB | |
SINAD | Signal-to-noise ratio + distortion | At fIN = 10 kHz | 83 | 84 | dB | |
THD | Total harmonic distortion(2) | At fIN = 10 kHz | –91 | –86 | dB | |
SFDR | Spurious-free dynamic range | At fIN = 10 kHz | 86 | 92 | dB | |
Channel-to-channel isolation | At fIN = 10 kHz | 120 | dB | |||
BW | –3-dB small-signal bandwidth | In 4-VREF mode | 48 | MHz | ||
In 2-VREF mode | 24 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SAMPLING DYNAMICS | ||||||
Conversion time | Internal conversion clock | 1.7 | μs | |||
fDATA | Throughput rate | Serial interface, all four SDOx active | 400 | kSPS | ||
Parallel interface | 510 | |||||
DC ACCURACY | ||||||
Resolution | 16 | Bits | ||||
No missing codes | 16 | Bits | ||||
INL | Integral linearity error(1) | At TA = –40°C to +85°C, VQFN package (RGC) | –3 | ±1.5 | 3 | LSB |
At TA = –40°C to +125°C, VQFN package (RGC) | –4 | ±1.5 | 4 | |||
At TA = –40°C to +85°C, LQFP package (PM) | –4 | ±1.5 | 4 | |||
At TA = –40°C to +125°C, LQFP package (PM) | –4.5 | ±1.5 | 4.5 | |||
DNL | Differential linearity error | At TA = –40°C to +85°C | –1 | ±0.75 | 1.75 | LSB |
At TA = –40°C to +125°C | –1 | ±0.75 | 2 | |||
Offset error | –1.5 | ±0.5 | 1.5 | mV | ||
Offset error matching | –0.65 | 0.65 | mV | |||
Offset error drift | ±3.5 | μV/°C | ||||
Gain error | Referenced to voltage at REFIO | –0.5% | ±0.25% | 0.5% | ||
Gain error matching | Between channels of any pair | –0.2% | 0.2% | |||
Between any two channels | –0.4% | 0.4% | ||||
Gain error drift | Referenced to voltage at REFIO | ±6 | ppm/°C | |||
AC ACCURACY | ||||||
SNR | Signal-to-noise ratio | At fIN = 10 kHz, TA = –40°C to +85°C | 90 | 91.5 | dB | |
At fIN = 10 kHz, TA = –40°C to +125°C | 89 | 91.5 | ||||
SINAD | Signal-to-noise ratio + distortion | At fIN = 10 kHz, TA = –40°C to +85°C | 87 | 90 | dB | |
At fIN = 10 kHz, TA = –40°C to +125°C | 86.5 | 90 | ||||
THD | Total harmonic distortion(2) | At fIN = 10 kHz, TA = –40°C to +85°C | –94 | –90 | dB | |
At fIN = 10 kHz, TA = –40°C to +125°C | –94 | –89.5 | ||||
SFDR | Spurious-free dynamic range | At fIN = 10 kHz, TA = –40°C to +85°C | 90 | 95 | dB | |
At fIN = 10 kHz, TA = –40°C to +125°C | 89.5 | 95 | ||||
Channel-to-channel isolation | At fIN = 10 kHz | 120 | dB | |||
BW | –3-dB small-signal bandwidth | In 4-VREF mode | 48 | MHz | ||
In 2-VREF mode | 24 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
tSCVX | CONVST_x high to XCLK rising edge setup time (CLKSEL = 1) |
6 | ns | |||
tXCLK | External conversion clock period | ADS8528 | 66.67 | ns | ||
ADS8548 | 72.46 | |||||
ADS8568 | 85.11 | |||||
External conversion clock frequency | ADS8528 | 1 | 15.0 | MHz | ||
ADS8548 | 1 | 13.8 | ||||
ADS8568 | 1 | 11.75 | ||||
External conversion clock duty cycle | 40% | 60% | ||||
tCVL | CONVST_x low time | 20 | ns | |||
tACQ | Acquisition time | 280 | ns | |||
Clock cycles per conversion | ADS85x8, tCCLK or tXCLK |
19 | 20 | Cycles | ||
tCONV | Conversion time | ADS8528, CLKSEL = 0 | 1.33 | μs | ||
ADS8548, CLKSEL = 0 | 1.45 | |||||
ADS8568, CLKSEL = 0 | 1.7 | |||||
tDCVB | CONVST_x high to BUSY high delay | 25 | ns | |||
tBUFS | BUSY low to FS low time | ADS85x8, CLKSEL = 1 | 0 | ns | ||
ADS8528, CLKSEL = 0(2) | 67 | |||||
ADS8548, CLKSEL = 0(2) | 73 | |||||
ADS8568, CLKSEL = 0(2) | 86 | |||||
tFSCV | Bus access finished to next conversion start time | ADS8528 | 0 | ns | ||
ADS8548 | 20 | |||||
ADS8568 | 40 | |||||
tSCLK | Serial clock period | 0.022 | 10 | μs | ||
Serial clock frequency | 0.1 | 45 | MHz | |||
Serial clock duty cycle | 40% | 60% | ||||
tDMSB | FS low to MSB valid delay | 12 | ns | |||
tHDO | Output data to SCLK falling edge hold time | 5 | ns | |||
tPDDO | SCLK falling edge to new data valid propagation delay | 17 | ns | |||
tDTRI | FS high to SDO_x three-state delay | 10 | ns | |||
tSUDI | Input data to SCLK falling edge setup time | 3 | ns | |||
tHDI | Input data to SCLK falling edge hold time | 5 | ns |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
tCVL | CONVST_x low time | 20 | ns | |||
tACQ | Acquisition time | 280 | ns | |||
Clock cycles per conversion | ADS85x8, tCCLK or tXCLK | 19 | 20 | Cycles | ||
tCONV | Conversion time | ADS8528, CLKSEL = 0 | 1.33 | µs | ||
ADS8548, CLKSEL = 0 | 1.45 | |||||
ADS8568, CLKSEL = 0 | 1.7 | |||||
tDCVB | CONVST_x high to BUSY high delay | 25 | ns | |||
tBUCS | BUSY low to CS low time | ADS85x8, CLKSEL = 1 | 0 | ns | ||
ADS8528, CLKSEL = 0(3) | 67 | |||||
ADS8548, CLKSEL = 0(3) | 73 | |||||
ADS8568, CLKSEL = 0(3) | 86 | |||||
tCSCV | Bus access finished to next conversion start time(2) | ADS8528 | 0 | ns | ||
ADS8548 | 20 | |||||
ADS8568 | 40 | |||||
tCSRD | CS low to RD low time | 0 | ns | |||
tRDCS | RD high to CS high time | 0 | ns | |||
tRDL | RD pulse duration | 20 | ns | |||
tRDH | Minimum time between two read accesses | 2 | ns | |||
tPDDO | RD or CS falling edge to data valid propagation delay | 15 | ns | |||
tHDO | Output data to RD or CS rising edge hold time | 5 | ns | |||
tDTRI | CS high to DB[15:0] three-state delay | 10 | ns |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
tCSWR | CS low to WR low time | 0 | ns | ||
tWRL | WR low pulse duration | 15 | ns | ||
tWRH | Minimum time between two write accesses | 10 | ns | ||
tWRCS | WR high to CS high time | 0 | ns | ||
tSUDI | Output data to WR rising edge setup time | 5 | ns | ||
tHDI | Data output to WR rising edge hold time | 5 | ns |
The ADS85x8 series includes eight 12-, 14-, and 16-bit analog-to-digital converters (ADCs) that operate based on the successive approximation register (SAR) architecture. This architecture is designed on the charge redistribution principle that inherently includes a sample-and-hold function. The eight analog inputs are grouped into four channel pairs. These channel pairs can be sampled and converted simultaneously, preserving the relative phase information of the signals of each pair. Separate conversion start signals allow simultaneous sampling on each channel pair of four, six, or eight channels. These devices accept single-ended, bipolar analog input signals in the selectable ranges of ±4 VREF or ±2 VREF with an absolute value of up to ±12 V; see the Analog Inputs section.
The devices offer an internal 2.5-V or 3-V reference source followed by a 10-bit digital-to-analog converter (DAC) that allows the reference voltage VREF to be adjusted in 2.44-mV or 2.93-mV steps, respectively.
The ADS85x8 also offer a selectable parallel or serial interface that can be used in hardware or software mode; see the Device Configuration section for details. The Analog and Digital sections describe the functionality and control of the device in detail.
This section addresses the analog input circuit, the ADCs and control signals, and the reference design of the device.
The inputs and the converters are of single-ended bipolar type. The absolute voltage range can be selected using the RANGE pin (in hardware mode) or RANGE_x bits (in software mode) in the Configuration (CONFIG) register to either ±4 VREF or ±2 VREF. With the internal reference set to 2.5 V (VREF bit C13 = 0 in the CONFIG register), the input voltage range can be ±10 V or ±5 V. With the internal reference source set to 3 V (CONFIG bit C13 = 1), an input voltage range of ±12 V or ±6 V can be configured. The logic state of the RANGE pin is latched with the falling edge of BUSY (if CONFIG bit C26 = 0).
The input current on the analog inputs depends on the actual sample rate, input voltage, and signal source impedance. Essentially, the current into the analog inputs charges the internal capacitor array only during the sampling period (tACQ). The source of the analog input voltage must be able to charge the input capacitance of 10 pF in ±4-VREF mode or of 20 pF in ±2-VREF mode to a 12-, 14-, or 16-bit accuracy level within the acquisition time; see Figure 35. During the conversion period, there is no further input current flow and the input impedance is greater than 1 MΩ. To ensure a defined start condition, the sampling capacitors of the ADS85x8 are pre-charged to a fixed internal voltage before switching into sampling mode.
To maintain the linearity of the converter, the inputs must always remain within the specified range defined in the Electrical Characteristics table. The minimum –3-dB bandwidth of the driving operational amplifier can be calculated using Equation 1:
where
With a minimum acquisition time of tACQ = 280 ns, the required minimum bandwidth of the driving amplifier is 5.2 MHz for the ADS8528, 6.0 MHz for the ADS8548, or 6.7 MHz for the ADS8568. The required bandwidth can be lower if the application allows a longer acquisition time. A gain error occurs if a given application does not fulfill the bandwidth requirement shown in Equation 1.
A driving operational amplifier may not be required if the impedance of the signal source (RSOURCE) fulfills the requirement of Equation 2:
where
With a minimum acquisition time of tACQ = 280 ns, the maximum source impedance must be less than 2.7 kΩ for the ADS8528, 2.3 kΩ for the ADS8548, and 2.0 kΩ for the ADS8568 in ±4V-REF mode, or less than 1.2 kΩ for the ADS8528, 1.0 kΩ for the ADS8548, and 0.8 kΩ for the ADS8568 in ±2-VREF mode. The source impedance can be higher if the application allows a longer acquisition time.
The device includes eight ADCs that operate with either an internal or an external conversion clock.
The device uses either an internally-generated (CCLK) or an external (XCLK) conversion clock signal (in software mode only). In default mode, the device generates an internal clock. In this case, a complete conversion including the pre-charging of the sample capacitors takes 19 to 20 clock cycles, depending on the setup time of the incoming CONVST_x signal with relation to the CCLK rising edge.
When the CLKSEL bit is set high (CONFIG bit C29), an external conversion clock can be applied on pin 34. A complete conversion process requires 19 clock cycles in this case if the tSCVX timing requirement is fulfilled. The external clock can remain low between conversions.
If the application requires lowest power dissipation at low data rates, using the auto-sleep mode activated with pin 36 (ASLEEP) is recommended. In this case, a conversion cycle takes up to 26 clock cycles (see the Reset and Power-Down Modes section for more details).
The analog inputs of each channel pair (CH_x0, CH_x1) are held with the rising edge of the corresponding CONVST_x signal. The conversion automatically starts with the next rising edge of the conversion clock. CONVST_A is a master conversion start that resets the internal state machine and causes the data output to start with the result of channel A0. In cases where channel pairs of the device are used at different data rates, CONVST_A must always be the one used at the highest frequency.
A conversion start must not be issued during an ongoing conversion on the corresponding channel pair. However, conversions are allowed to be initiated on other input pairs; see the Sequential Operation section for more details.
If a parallel interface is used, the content of the output port depends on which CONVST_x signals are issued. Figure 36 shows examples of different scenarios with all channel pairs active.
The BUSY signal indicates if a conversion is in progress. The BUSY signal goes high with a rising edge of any CONVST_x signal and returns low again when the last channel pair completes the conversion cycle.
When operating the device with an external clock (CONFIG bit 29, CLKSEL = 1), data readout can be initiated immediately after the falling edge of the BUSY signal or after 19 complete conversion clock cycles (XCLK), respectively.
When using the device with an internal conversion clock (CONFIG bit 29, CLKSEL = 0), data can be retrieved after tCONV(max) independently from the BUSY signal. In case the data readout is referred to the falling edge of the BUSY signal, the readout sequence cannot start before tBUFS/BUCS after the falling edge, corresponding to 1 CCLK cycle (for example, 86 ns for the ADS8568).
In contrast, the INT signal goes high when a new conversion result is loaded in the output register (which occurs when the conversion completes) and remains high until the next read access, as shown in Figure 37.
The polarity of the BUSY/INT signal can be changed using CONFIG bit C26. The mode of pin 35 can be controlled using CONFIG bit C27.
The four channel pairs of the ADS8528, ADS8548, and ADS8568 can run in sequential mode, with the corresponding CONVST_x signals interleaved. In this case, the BUSY output transitions low for a single conversion clock cycle (tCCLK) whenever a channel pair completes a conversion. BUSY finally remains low when the conversion of the last channel pair completes. Figure 38 shows the behavior of the BUSY output in this mode.
NOTE:
EOC = end of conversion (internal signal).For best performance, operation with an external clock is recommended (CONFIG bit 29, CLKSEL = 1). Initiate each conversion start during the high phase of the external clock; see Figure 40.
The time between two CONVST_x pulses must be at least one conversion clock cycle. In case the skew of the CONVST_x signals is less than one conversion clock cycle, the data readout cannot be started before tCCLK after the falling edge of the BUSY signal.
The ADS85x8 provides an internal, low-drift, 2.5-V reference source. To increase the input voltage range, the reference voltage can be switched to 3-V mode using the VREF bit (CONFIG bit C13). The reference feeds a 10-bit string-DAC controlled by the REFDAC[9:0] bits in the Configuration (CONFIG) register. The buffered DAC output is connected to the REFIO pin. In this way, the voltage at this pin is programmable in 2.44-mV steps (2.92 mV in 3-V mode) and adjustable to the applications needs without additional external components. The actual output voltage can be calculated using Equation 3:
where
Table 1 lists some examples of internal reference DAC settings with a reference range set to 2.5 V. However, to ensure proper performance, the DAC output voltage must not be programmed below 0.5 V.
Decouple the buffered output of the DAC with a 100-nF capacitor (minimum); for best performance, a 470-nF capacitor is recommended. If the internal reference is placed into power-down (default), an external reference voltage can drive the REFIO pin.
VREFOUT | DECIMAL CODE | BINARY CODE | HEXADECIMAL CODE |
---|---|---|---|
0.5 V | 204 | 00 1100 1100 | CCh |
1.25 V | 511 | 01 1111 1111 | 1FFh |
2.5 V | 1023 | 11 1111 1111 | 3FFh |
The voltage at the REFIO pin is buffered with four internal amplifiers, one for each ADC pair. The output of each buffer must be decoupled with a 10-µF capacitor between the pin pairs of 3 and 6, 43 and 46, 50 and 53, and 60 and 63. The 10-µF capacitors are available as ceramic 0805-SMD components and in X5R quality.
The internal reference buffers can be powered down to decrease the power dissipation of the device. In this case, external reference drivers can be connected to the REFAP, REFBP, REFCP, and REFDP pins. With 10-µF decoupling capacitors, the minimum required bandwidth can be calculated using Equation 4:
With the minimum tCONV of 1.33 µs, the external reference buffers require a minimum bandwidth of 83 kHz.
This section describes the digital control and the timing of the device in detail.
Depending on the desired mode of operation, the ADS85x8 can be configured using the external pins or the Configuration register (CONFIG), as shown in Table 2.
INTERFACE MODE | HARDWARE MODE (HW/SW = 0) | SOFTWARE MODE (HW/SW = 1) |
---|---|---|
Parallel (PAR/SER = 0) | Configuration using pins and (optionally) Configuration register bits C30, C29, C[27:26], C22, C20, C18, C14, C13, and C[9:0] | Configuration using Configuration register bits C[31:0] only; status of pins 9, 11, 20, and 34 are disregarded (if C29 = C28 = 0) |
Serial (PAR/SER = 1) | Configuration using pins and (optionally) Configuration register bits C30, C29, C[27:26], C22, C20, C18, C13, and C[9:0] | Configuration using Configuration register bits C[31:0] only; status of pins 9, 11, 20, and 34 are disregarded (if C29 = C28 = 0) |
To use the device with the parallel interface, hold the PAR/SER pin low. The maximum achievable data throughput rate is 650 kSPS for the ADS8528, 600 kSPS for the ADS8548, and 510 kSPS for the ADS8568 in this case.
Access to the ADS85x8 is controlled as illustrated in Figure 2 and Figure 3.
The serial interface mode is selected by setting the PAR/SER pin high. In this case, each data transfer starts with the falling edge of the frame synchronization input (FS). The conversion results are presented on the serial data output pins SDO_A (always active), SDO_B, SDO_C, and SDO_D, depending on the selections made using the SEL_xx pins. Starting with the most significant bit (MSB), the output data are changed with the SCLK falling edge. The ADS8528 and ADS8548 output data maintain the LSB-aligned, 16-bit format with leading bits containing the extended sign (see Table 3). Serial data input SDI are latched with the SCLK falling edge.
The serial interface can be used with one, two, or four output ports. Port SDO_B can be enabled using pin 27 (SEL_B) and ports SDO_C and SDO_D are enabled using pin 28 (SEL_CD). If all four serial data output ports are selected, data can be read with either two 16-bit data transfers or with a single 32-bit data transfer. The data of channels CH_x0 are available first, followed by data from channels CH_x1. The maximum achievable data throughput rate is 480 kSPS for the ADS8528, 450 kSPS for the ADS8548, and 400 kSPS for the ADS8568 in this case.
If the application allows a data transfer using two ports only, the SDO_A and SDO_B outputs are used. The device outputs data from channel CH_A0 followed by CH_A1, CH_C0, and CH_C1 on SDO_A; data from channel CH_B0 followed by CH_B1, CH_D0, and CH_D1 occur on SDO_B. In this case, a data transfer of four 16-bit words, two 32-bit words, or one continuous 64-bit word is supported. The maximum achievable data throughput rate is 360 kSPS for the ADS8528, 345 kSPS for the ADS8548, and 315 kSPS for the ADS8568 in this case.
The output SDO_A is always active and exclusively used if only one serial data port is used in the application. Data are available in the following order: CH_A0, CH_A1, CH_B0, CH_B1, CH_C0, CH_C1, CH_D0, and CH_D1. Data can be read using eight 16-bit transfers, four 32-bit transfers, two 64-bit transfers, or a single 128-bit transfer. The maximum achievable data throughput rate is 235 kSPS for the ADS8528, 230 kSPS for the ADS8548 and 215 kSPS for the ADS8568 in this case. Figure 1 and Figure 39 illustrate all possible scenarios in more detail.
The data output format of the ADS85x8 is binary twos complement, as shown in Table 3. For the ADS8528 and ADS8548 (that deliver 12-bit or 14-bit conversion results, respectively), the leading bits of either the 16-bit frame (serial interface) or the output pins (DB[15:12] for the ADS8528 or DB[15:14] for the ADS8548 in parallel mode) deliver a sign extension.
DESCRIPTION | INPUT VOLTAGE VALUE | BINARY CODE HEXADECIMAL CODE | ||
---|---|---|---|---|
ADS8528 | ADSS8548 | ADS8568 | ||
Positive full-scale | 4 VREF or 2 VREF | 0000 0111 1111 1111 07FFh | 0001 1111 1111 1111 1FFFh | 0111 1111 1111 1111 7FFFh |
Midscale 0.5 LSB | VREF / (2 × resolution) | 0000 0000 0000 0000 0000h | 0000 0000 0000 0000 0000h | 0000 0000 0000 0000 0000h |
Midscale –0.5 LSB | –VREF / (2 × resolution) | 1111 1111 1111 1111 FFFFh | 1111 1111 1111 1111 FFFFh | 1111 1111 1111 1111 FFFFh |
Negative full-scale | –4 VREF or –2 VREF | 1111 1000 0000 0000 F800h | 1110 0000 0000 0000 E000h | 1000 0000 0000 0000 8000h |
With the HW/SW input (pin 41) set low, the device functions are controlled via the pins and, optionally, Configuration register bits C30, C29, C[27:26], C22, C20, C18, C14 (in parallel interface mode only), C13, and C[9:0].
The device can generally be used in hardware mode but can be switched to software mode to initialize or adjust the Configuration register settings (for example, the internal reference DAC) and back to hardware mode thereafter.
When the HW/SW input is set high, the device operates in software mode with functionality set only by the Configuration register bits (corresponding pin settings are ignored).
If the parallel interface is used, an update of all Configuration register settings is performed by issuing two 16-bit write accesses on pins DB[15:0] (to avoid losing data, the entire sequence must be finished before starting a new conversion). Do not hold CS low during these two accesses. To enable the actual update of the register settings, the first bit (C31) must be set to 1 during the access.
If the serial interface is used, the update of the register contents can be performed continuously (combined read/write access). Optionally, to reduce the data transfer on the SDI line and the electromagnetic interference (EMI) of the system, the SDI input can be pulled low when a register update is not required. Figure 40 illustrates the different Configuration register update options.
The serial interface of the ADS85x8 supports a daisy-chain feature that allows cascading of multiple devices to minimize the board space requirements and simplify routing of the data and control lines. In this case, the DB3/DCIN_A, DB2/DCIN_B, DB1/DCIN_C, and DB0/DCIN_D pins are used as serial data inputs for channels A, B, C, and D, respectively. Figure 41 shows an example of a daisy-chain connection of three devices sharing a common CONVST line to allow simultaneous sampling of 24 analog channels along with the corresponding timing diagram.
To activate the daisy-chain mode, the DCEN pin must be pulled high. However, the DCEN of the first device in the chain must remain low.
In applications where not all channel pairs are used, declaring the device with disabled channel pairs to be the first in the daisy-chain is recommended.
The device supports two reset mechanisms: a power-on reset (POR) and a pin-controlled reset (RESET) that can be issued using pin 10. Both the POR and RESET function as a master reset that causes any ongoing conversion to be interrupted, the Configuration register content to be set to the default value, and all channels to be switched into sample mode.
When the device is powered up, POR sets the device in default mode when AVDD reaches 1.2 V. In normal operation, glitches on the AVDD supply below this threshold trigger a device reset.
The entire device, except for the digital interface, can be powered down by pulling the STBY pin low (pin 9). Data can be retrieved when in standby mode because the digital interface section remains active. To power the device on again, the STBY pin must be brought high. The device is ready to start a new conversion after the 10 ms required to activate and settle the internal circuitry. This user-controlled approach can be used in applications that require lower data throughput rates at lowest power dissipation. The content of CONFIG is not changed during standby mode and is not required to perform a reset after returning to normal operation.
Although standby mode affects the entire device, each device channel pair (except channel pair A, which is the master channel pair and is always active) can also be individually switched off by setting the Configuration register bits C22, C20, and C18 (PD_x). If a certain channel pair is powered-down in this manner, the output register is disabled as shown in Figure 42. When reactivated, the relevant channel pair requires 10 ms to fully settle before starting a new conversion.
NOTE:
Boxed areas indicate the minimum required frame to acquire all new conversion results. The read access can be interrupted, thereafter.Auto-sleep mode is enabled by pulling pin 36 (ASLEEP) high. If auto-sleep mode is enabled, the ADS85x8 automatically reduce the current requirement to 7 mA (IAVDD) after finishing a conversion; thus, the end of conversion actually activates this power-down mode. Triggering a new conversion by applying a positive CONVST_x edge starts the wake-up sequence to put the device back into normal operation. At the beginning, all required building blocks power-up and the sampling switches close again. This sequence takes six to seven conversion clock cycles of either the internal or external clock. During this time, the sampling capacitance must be recharged to the input signal with the required 12-bit, 14-bit, or 16-bit accuracy level. The bandwidth requirements of the driving operational amplifier described in the Analog Inputs section must be fulfilled. At the end of the sequence, the new sample is taken and the conversion starts automatically, as shown in Figure 43. Therefore, a complete conversion process takes 25 to 26 conversion clock cycles; thus, the maximum throughput rate in auto-sleep mode is reduced to a maximum of 400 kSPS for the ADS8528, 375 kSPS for the ADS8548, and 330 kSPS for the ADS8568 in serial interface mode. In parallel mode, the maximum data rates are 510 kSPS for the ADS8528, 470 kSPS for the ADS8548, and 400 kSPS for the ADS8568. If enabled, the internal reference remains active during auto-sleep mode. Table 4 compares the analog current requirements of the device in different modes.
OPERATIONAL MODE | ANALOG CURRENT (IAVDD) | ENABLED, DISABLED BY | ACTIVATED BY | NORMAL OPERATION TO POWER-DOWN DELAY | RESUMED BY | POWER-UP TO NORMAL OPERATION DELAY | POWER-UP TO NEXT CONVERSION START TIME |
---|---|---|---|---|---|---|---|
Normal operation | 12.5 mA/ch pair at maximum data rate | Power on | CONVST_x | — | — | — | — |
Power off | |||||||
Auto-sleep | 1.75 mA/ch pair | ASLEEP = 1 | Each end of conversion | At BUSY falling edge | CONVST_x | Immediate | 7 × tCCLK max |
ASLEEP = 0 | |||||||
Power-down of channel pair X | 16 µA (channel pair X) |
HW/SW = 1 | PD_x = 1 (CONFIG bit) | Immediate | PD_x = 0 (CONFIG bit) | Immediate after completing CONFIG update | 10 ms |
HW/SW = 0 | |||||||
Power-down (entire device) | 30 µA | Power on | STBY = 0 | Immediate | STBY = 1 | Immediate | 10 ms |
Power off |
The Configuration register settings can only be changed in software mode and are not affected when switching to hardware mode thereafter. The register values are independent from input pin settings. Changes are active with the second WR rising edge in parallel interface mode or with the 32nd SCLK falling edge of the access where the register content is updated in serial mode. The CONFIG content is defined in CONFIG: Configuration Register (default = 000003FFh).
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
WRITE_EN | READ_EN | CLKSEL | CLKOUT | BUSY/INT | BUSY POL | STBY | RANGE_A |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RANGE_B | PD_B | RANGE_C | PD_C | RANGE_D | PD_D | Don't care | Don't care |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
REFEN | REFBUF | VREF | Don't care | Don't care | Don't care | D9 | D8 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
Bit 31 | WRITE_EN: Register update enable |
This bit is not active in hardware mode. 0 = Register content update disabled (default) 1 = Register content update enabled |
|
Bit 30 | READ_EN: Register read-out access enable |
This bit is not active in hardware mode. 0 = Normal operation (conversion results available on SDO_A) 1 = Configuration register contents output on SDO_A with next two accesses (READ_EN automatically resets to 0 thereafter) |
|
Bit 29 | CLKSEL: Conversion clock selector |
This bit is active in hardware mode. 0 = Normal operation with internal conversion clock; mandatory in hardware mode (default) 1 = External conversion clock applied through pin 34 (XCLK) is used (conversion takes 19 clock cycles) |
|
Bit 28 | CLKOUT: Internal conversion clock output enable |
This bit is not active in hardware mode. 0 = Normal operation (default) 1 = Internal conversion clock is available at pin 34 |
|
Bit 27 | BUSY/INT: Busy/interrupt selector |
This bit is active in hardware mode. 0 = BUSY/INT pin is in BUSY mode (default) 1 = BUSY/INT pin is in interrupt mode (INT); can only be used if all eight channels are sampled simultaneously (all CONVST_x tied together) |
|
Bit 26 | BUSY POL: BUSY/INT polarity selector |
This bit is active in hardware mode. 0 = BUSY/INT active high (default) 1 = BUSY/INT active low |
|
Bit 25 | STBY: Power-down enable |
This bit is not active in hardware mode. 0 = Normal operation (default) 1 = Entire device is powered down (including the internal clock and reference) |
|
Bit 24 | RANGE_A: Input voltage range selector for channel pair A |
This bit is not active in hardware mode. 0 = Input voltage range: 4 VREF (default) 1 = Input voltage range: 2 VREF |
|
Bit 23 | RANGE_B: Input voltage range selector for channel pair B |
This bit is not active in hardware mode. 0 = Input voltage range: 4 VREF (default) 1 = Input voltage range: 2 VREF |
|
Bit 22 | PD_B: Power-down enable for channel pair B |
This bit is active in hardware mode. 0 = Normal operation (default) 1 = Channel pair B is powered down |
|
Bit 21 | RANGE_C: Input voltage range selector for channel pair C |
This bit is not active in hardware mode. 0 = Input voltage range: 4 VREF (default) 1 = Input voltage range: 2 VREF |
|
Bit 20 | PD_C: Power-down enable for channel pair C |
This bit is active in hardware mode. 0 = Normal operation (default) 1 = Channel pair C is powered down |
|
Bit 19 | RANGE_D: Input voltage range selector for channel pair D |
This bit is not active in hardware mode. 0 = Input voltage range: 4 VREF (default) 1 = Input voltage range: 2 VREF |
|
Bit 18 | PD_D: Power-down enable for channel pair D |
This bit is active in hardware mode. 0 = Normal operation (default) 1 = Channel pair D is powered down |
|
Bits 17-16 | Not used (default = 0) |
Bit 15 | REF_EN: Internal reference enable |
This bit is not active in hardware mode. 0 = Internal reference source disabled (default) 1 = Internal reference source enabled |
|
Bit 14 | REFBUF: Internal reference buffers disable |
This bit is active in hardware mode if the parallel interface is used. 0 = Internal reference buffers enabled (default) 1 = Internal reference buffers disabled |
|
Bit 13 | VREF: Internal reference voltage selector |
This bit is active in hardware mode. 0 = Internal reference voltage set to 2.5 V (default) 1 = Internal reference voltage set to 3.0 V |
|
Bits 12-10 | Not used (default = 0) |
Bits 9-0 | D[9:0]: REFDAC setting bits |
These bits are active in hardware mode. These bits correspond to the settings of the internal reference DACs (compare to the Reference section). Bit 9 is the MSB of the DAC. Default value is 3FFh (2.5 V, typ). |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The ADS85x8 enables high-precision measurement of up to eight analog signals simultaneously. The Typical Application section summarizes some of the typical use cases for the ADS85x8 and the main steps and components used around the analog-to-digital converter (ADC).
The accurate measurement of electrical variables in a power grid is extremely critical because this measurement helps determine the operating status and running quality of the grid. Such accurate measurements also help diagnose problems with the power network, thereby enabling prompt solutions and minimizing down time. The key electrical variables measured in 3-phase power systems are the three line voltages, the neutral voltage at the load, the three line currents, and the neutral return current; see Figure 45. These variables enable metrology and power automation systems to determine the amplitude, frequency, and phase information in order to perform harmonic analysis, power factor calculations, and power quality assessment, among others.
To begin the design process, a few parameters must be decided upon. The designer must know the following:
Figure 46 shows the topology chosen to meet the design requirements.
NOTE
A feedback capacitor CF is included in order to provide a low-pass filter characteristic and attenuate signals outside the band of interest.
The potential transformers and current transformers used in the system depicted in Figure 45 provide the eight inputs required. These transformers have a ±10-V output range. Although the PT and CT elements provide isolation from the power system, the value of RIN is selected as 100 kΩ in order to provide an additional, high-impedance safety element in the current path leading up to the input of the ADC. Moreover, selecting a low-frequency gain of –1 V/V (as shown in Equation 5) provides a ±10-V output that can be fed into the ADS8568; therefore, the value of RF is selected as 100 kΩ too.
The primary goal of the acquisition system depicted in Figure 45 is to measure up to 20 harmonics in a 60-Hz power network. With this goal in mind, the analog front-end must have sufficient bandwidth to measure signals up to 1260 Hz as shown in Equation 6.
Based on the bandwidth from in Equation 6, the ADS8568 is set to simultaneously sample all six channels at 15.36 kSPS, thus providing enough samples to clearly resolve even the highest harmonic required.
The passband of the configuration shown in Figure 46 is determined by the –3-dB frequency according to Equation 7. The value of CF is selected as 820 pF because CF is a standard capacitance value available in 0603 size (surface-mount component) and such values, combined with that of RF, result in sufficient bandwidth to accommodate the required 20 harmonics (at 60 Hz).
The value of R1 is selected as the parallel combination of RIN and RF to prevent the input bias current of the operational amplifier from generating an offset error.
The value of component C1 is chosen as 0.1 µF to provide a low-impedance path for noise signals that can be picked up by R1, thus improving the EMI robustness and noise performance of the system.
The OPA2277 is chosen for its low input offset voltage, low drift, bipolar swing, sufficient gain-bandwidth product, and low quiescent current. For additional information on the procedure to select SAR ADC input drivers, see the TIPD151 verified design guide, 16-Bit 100-KSPS 4-Channel Multiplexed Data Acquisition System Design Guide.
The charge injection damping circuit is composed by R2 (49.9 Ω) and C2 (370 pF); these components reject high-frequency noise and meet the settling requirements of the ADS8568 input.
Figure 47 shows the reference block used in this design.
For more information on the design of charge injection damping circuits and reference driving circuits for SAR ADCs, see the TIPD149 verified design reference guide, Power-Optimized 16-Bit 1-MSPS Data Acquisition Block for Lowest Distortion and Noise.
Figure 48 shows the frequency spectrum of the data acquired by the ADS8568 for a sinusoidal, 20-VPP input at 60 Hz.
The ac performance parameters are: