TIDUF27A February 2025 – March 2025 AMC131M03 , MSPM0G1507
Due to the need to distribute two synchronous clocks to four ADCs, two LMK1C1104 clock buffers are added. The first buffer derives the four synchronous CLKIN1–4 signals with 8.192MHz from the M0_CLKOUT output, while the second buffer takes in the SPI clock from the SPI peripheral and outputs four SCLK1–4 signals to drive each of the ADCs separately.