This reference design is a fully functional development board powering an NXP™ i.MX 6ULL application processor from a TPS6521815 PMIC. The hardware design consists of DDR3L SDRAM (512 MB), 32-MB Serial NOR Flash, 8-GB eMMC 5.0 iNAND, SD Card interface v3.0, dual-channel 100Base-T Ethernet, 5-channel USB hub with Type-A ports, micro-AB USB OTG, mountable LCD screen, and expansion connector for additional inputs and outputs. This design is intended to be used as a reference for data concentrator projects in grid communications or for any project using the i.MX 6ULL, i.MX 6ULZ, or i.MX 6UltraLite processor that requires evaluation of alternative power solutions.
TIDA-050043 | Design Folder |
TPS6521815 | Product Folder |
TPS22964C | Product Folder |
TPS2054B | Product Folder |
INA3221 | Product Folder |
DP83849I | Product Folder |
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An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other important disclaimers and information. |
TIDA-050043 is first-and-foremost a reference design for powering the NXP i.MX 6ULL processor from the TPS6521815 PMIC. To show that the PMIC can power the processor, it made the most sense to build a data concentrator design that can also be used as a full evaluation kit (EVK) board with a variety of peripheral devices to assist with development of various end equipments. As a result, there are a variety of wired connections available, as well as multiple BOOT options. The end result of adding all the peripherals, especially a 5-port USB hub, is that some external load switches have been added to provide more voltage rails to deliver 5-V USB from the input to the USB hub. Finally, to ensure the entire board is operational, we developed and tested software using the open-source embedded Linux Yocto SDK to get started working with this design.
PARAMETER | SPECIFICATIONS | DETAILS |
---|---|---|
Processor | i.MX 6ULL, ARM Cortex-A7 Applications Processor, MCIMX6Y2CVM08AB | Section 2.2.1 |
PMIC | TPS6521815 user-programmable PMIC with automatic sequencing and DVFS | Section 2.3.1 |
Memory | 4-Gb DDR3L (512 MB), 256-Mb QSPI NOR-Flash (32 MB), 8GB eMMC 5.0, SD v3.0 interface | Section 2.2.2 |
Ethernet | Dual-port ethernet interface - TI DP83849I PHY and 0845-2R1T-E4 RJ45 jack from Bel Fuse | Section 2.3.2 |
Debug method (USB-to-UART) | FTDI FT230X is required to implement USB to serial UART conversion | Section 2.2.3 |
USB ports | 5x USB Type-A ports (USB2517I-JZX hub IC) and 1x micro-AB port for USB OTG (Amphenol 10104111-0001LF) | Section 2.2.4 |
LCD display | RGB TFT 40-pin connector (Molex 54132-4062) for LCD display (Newhaven Display NHD-2.4-240320CF-CTXI#-F), compatible with touch-screen controller (TI TSC2046IPWR) | Section 2.2.5 |
JTAG header | JTAG connection to i.MX 6ULL processor with 50-mil pitch, 10-pin header | Section 2.2.6 |
USB2ANY header | Debug method for PMIC separate from processor I2C bus. Provided by USB2ANY (standard 100-mil pitch, 10-pin header) | Section 2.2.7 |
Current monitoring | 2x TI INA3221 devices are used to monitor current through 6 rails in the system | Section 2.3.3 |
Operation with Coin Cell | Coin cell for i.MX 6ULL SNVS input. Using DCDC6 of TPS6521815 PMIC, system always powers SNVS before full power-up sequence begins. | Section 2.3.4 |
Tactile inputs, visual feedback | Push-buttons and status LEDs connected to GPIOs of the processor to assist with debugging software | Section 2.2.8 |
This design is intended to show the ability of the TPS6521815 PMIC to provide power to the i.MX 6ULL processor and all of the peripheral ICs in a variety of designs. To verify this, we had to populate all of these other ICs on the design, starting with the processor. All other devices necessary to build an operational data concentrator or general-purpose evaluation kit are included in this section. The PMIC and other TI devices used in this design are described in Section 2.3.
The main component of this design is the NXP i.MX 6ULL processor. It is a single-core Arm®Cortex®-A7 16-bit processor. Dynamic voltage and frequency scaling (DVFS) is a highlight of the processor, wherein the processor can change the core voltage with respect to the processing power required. The multimedia performance of the processor is enhanced by a multilevel cache system, an ARM NEON media processor engine (MPE) co-processor, a programmable smart DMA (SDMA) controller, an asynchronous audio sample rate converter, an electrophoretic display (EPD) controller, and a pixel processing pipeline (PXP) to support 2D image processing, including color-space conversion, scaling, alpha-blending and rotation. DDR3L, eMMC, SD, QSPI, UART, and I2C are the processor interfaces we are using in this design.
DESCRIPTION | MFG. | PART NUMBER |
---|---|---|
iMX6ULL, ARM Cortex-A7 Application Processor, 792MHz, MAPBGA-289 | NXP | MCIMX6Y2CVM08AB |
This project makes use of i.MX 6ULL processor’s four different external memory interfaces using 4-Gb DDR3L (512 MB), 256-Mb QSPI NOR-Flash (32 MB), 8-GB eMMC 5.0, and SD v3.0.