SWRZ111A November   2021  – January 2022 CC2652P7

 

  1.   Trademarks
  2. 1Advisories Matrix
  3. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support-Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  4. 3Advisories
    1.     Radio_01
    2.     Radio_02
    3.     Power_03
    4.     PKA_01
    5.     PKA_02
    6.     I2C_01
    7.     I2S_01
    8.     CPU_01
    9.     CPU_02
    10.     CPU_03
    11.     CPU_Sys_01
    12.     Sys_01
    13. 3.1 Sys_05
    14.     SYSCTRL_01
    15.     IOC_01
    16.     ADC_01
    17.     ADC_02
    18.     ADC_03
  5. 4Revision History

I2C_01

I2C module master status bit is set late

Revisions Affected:

Revision B

Details:

The I2C.MSTAT[0] bit is not set immediately after writing to the I2C.MCTRL register. This can lead an I2C master to believe it is no longer busy and continuing to write data.

Workaround:

Add four NOPs between writing to the MCTRL register and polling the MSTAT register.

The workaround is implemented in the TI-provided I2C Master driver (I2CCC26XX.c) and in the I2C driver Library APIs (driverlib/i2c.c).

The workaround is available in the SimpleLink™ CC13xx and CC26xx Software Development Kit (SDK).