SWRZ077C January   2018  – December 2020 CC1352R

 

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Advisories Matrix

Table 1-1 lists all advisories, modules affected, and the applicable silicon revisions.

Table 1-1 Advisories Matrix
MODULEDESCRIPTIONSILICON REVISIONS AFFECTED
E
RadioAdvisory Radio_01 — Proprietary radio modes: spurious emissions can affect regulatory complianceYes
PowerAdvisory Power_03 — Increased voltage ripple at low supply voltages when DC/DC converter is enabledYes
PKAAdvisory PKA_01 — Public key accelerator (PKA) interrupt line is always high when module is enabled and PKA is idleYes
PKAAdvisory PKA_02 — Public key accelerator (PKA) RAM is not byte accessibleYes
I2CAdvisory I2C_01 — I2C module master status bit is set lateYes
I2SAdvisory I2S_01 — I2S bus faults are not reportedYes
CPUAdvisory CPU_01Arm® Errata #838869: Store immediate overlapping exception return operation might vector to incorrect interruptYes
CPUAdvisory CPU_02Arm® Errata #752770: Interrupted loads to SP can cause erroneous behaviorYes
CPUAdvisory CPU_03Arm® Errata #776924 VDIV or VSQRT instructions might not complete correctly when very short ISRs are usedYes
CPU, SystemAdvisory CPU_Sys_01 — The SysTick calibration value (register field CPU_SCS.STCR.TENMS) used to set up 10-ms periodic ticks is incorrect when the system CPU is running off divided down 48-MHz clockYes
SystemAdvisory Sys_01 — Device might boot into ROM serial bootloader when waking up from shutdownYes
System ControllerAdvisory SYSCTRL_01 — Resets occurring in a specific 2-MHz period during initial power up are incorrectly reportedYes
IO ControllerAdvisory IOC_01 — Limited number of DIOs available for the bootloader backdoorYes
SRAMAdvisory SRAM_01 — Reserved addresses within SRAM_MMR region alias into SRAM arrayYes
General-Purpose TimerAdvisory GPTM_01 — An incorrect value might be written to the general-purpose (GP) timers MMRs (memory mapped registers) when simultaneously accessing the PKA (public key accelerator) engine and/or the AES (advanced encryption standard) engine from a different masterYes
ADCAdvisory ADC_01 — Periodic ADC trigger at 200 kHz rate can be ignored when XOSC_HF is turned on or offYes
ADCAdvisory ADC_02 — ADC samples can be delayed by 2 or 14 clock cycles (24 MHz) when XOSC_HF is turned on or off, resulting in sample jitterYes
ADCAdvisory ADC_03 — Software can hang when reading the ADC FIFO if a single manual ADC trigger is generated immediately after the ADC is enabledYes
ADCAdvisory ADC_04 — Misbehaving ADC FIFO status flags in the AUX_ANAIF:ADCFIFOSTAT register (OVERFLOW, FULL, ALMOST_FULL, and EMPTY)Yes
ADCAdvisory ADC_05 — Writing any value to AUX_ANAIF:ADCTRIG.START will create an ADC triggerYes