There are two CLB tiles in this solution, one controlling the SPI timing, the other calculates the RX CRC on the fly. The SPI timing CLB tile would be compatible with the one in the T-Format solution, and therefore no change is required. However, the RX CRC CLB tile would require changes since the field format and the CRC polynomial is different. The following describes the CLB implementation for CRC calculation. For the rest of the CLB functions, one may refer to the T-Format design guide.

The RX CRC is calculated using the counter block in Linear Feedback Shift Register (LFSR) mode. The RX bits are shifted in the LFSR upon each SPI clock, and the CRC result can be read from the LFSR once the last bit is shifted in. Figure 2-3 marks the bits that should be shifted into the LFSR. The CLB logic implements a bit mask filter to select the specific bits that need to be shifted into the LFSR for CRC calculation, the mask is generated based on the below two rules:

• The middle 16 bits of every 18 bits
• The first n bits

where n is the total frame length excluding the CRC fields and the delimiter at the end. The signal used to mask the CRC bits are named as CRC_MASK and DATA_VALID.

Since the mask rules are different to T-Fomat, the CLB logic for SHIFT_EN signal generation is changed as well. Two counters and one FSM are used to generate the SHIFT_EN signal. Figure 2-4 shows the block diagram of the CLB tile for CRC calculations. The block diagrams are mostly identical to the T-Format implementation, except for SHIFT_EN signal generation logic, which includes COUNTER0, COUNTER1 and FSM2 and LUT1.

The above logics are implemented using the TI CLB Tool Chain (Rev. B, see References [2]). For the usage of the tool chain, one may refer to CLB Tool User's Guide (Rev. B). A quick way to verify the logic is through simulation, which is part of the tool chain. Figure 2-5 shows an example simulation of the CRC calculation. The response from encoder is input as “Boundary input 4” in the waveforms. As the response data comes in, the SHIFT_EN signal is generated as “Counter2_mode0”. This signal marks the bits included in the CRC calculation. The response data is shifted into the LFSR, which is marked as “counter_2”, upon every pulse of the SHIFT_EN signal. As the last SHIFT_EN pulse comes in, the LFSR holds a value of 0x1576608F, where the final 8 bits, 0x8F, represent the desired CRC result.