2 Wear-Out Mechanisms

Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful lifetime of TI embedded processors under power when used in electronic systems. It discusses the stages of reliability, the useful life period, and complementary metal-oxide semiconductor (CMOS) wear-out mechanisms. The primary wear-out mechanism discussed in the application note was electro-migration.

As each semiconductor process node is unique, some wear-out mechanism may affect the estimated lifetime of the devices in different ways.

For the device family, the following CMOS wear-out mechanisms were evaluated to extend the estimated operational lifetime of the device:

• Electro-Migration
• Gate Oxide Integrity
• Negative Bias Temperature Instability
• Channel Hot Carrier

The guidelines detailed in the next section were generated as a result of that evaluation.