SPNS183C September   2012  – June 2015

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 PGE QFP Package Pinout (144-Pin)
    2. 4.2 ZWT BGA Package Ball-Map (337 Ball Grid Array)
    3. 4.3 Terminal Functions
      1. 4.3.1 PGE Package
        1. 4.3.1.1  Multibuffered Analog-to-Digital Converters (MibADC)
        2. 4.3.1.2  Enhanced High-End Timer Modules (N2HET)
        3. 4.3.1.3  Enhanced Capture Modules (eCAP)
        4. 4.3.1.4  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        5. 4.3.1.5  Enhanced Pulse-Width Modulator Modules (ePWM)
        6. 4.3.1.6  General-Purpose Input / Output (GPIO)
        7. 4.3.1.7  Controller Area Network Controllers (DCAN)
        8. 4.3.1.8  Local Interconnect Network Interface Module (LIN)
        9. 4.3.1.9  Standard Serial Communication Interface (SCI)
        10. 4.3.1.10 Inter-Integrated Circuit Interface Module (I2C)
        11. 4.3.1.11 Standard Serial Peripheral Interface (SPI)
        12. 4.3.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        13. 4.3.1.13 Ethernet Controller
        14. 4.3.1.14 System Module Interface
        15. 4.3.1.15 Clock Inputs and Outputs
        16. 4.3.1.16 Test and Debug Modules Interface
        17. 4.3.1.17 Flash Supply and Test Pads
        18. 4.3.1.18 Supply for Core Logic: 1.2V nominal
        19. 4.3.1.19 Supply for I/O Cells: 3.3V nominal
        20. 4.3.1.20 Ground Reference for All Supplies Except VCCAD
      2. 4.3.2 ZWT Package
        1. 4.3.2.1  Multibuffered Analog-to-Digital Converters (MibADC)
        2. 4.3.2.2  Enhanced High-End Timer Modules (N2HET)
        3. 4.3.2.3  Enhanced Capture Modules (eCAP)
        4. 4.3.2.4  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        5. 4.3.2.5  Enhanced Pulse-Width Modulator Modules (ePWM)
        6. 4.3.2.6  General-Purpose Input / Output (GPIO)
        7. 4.3.2.7  Controller Area Network Controllers (DCAN)
        8. 4.3.2.8  Local Interconnect Network Interface Module (LIN)
        9. 4.3.2.9  Standard Serial Communication Interface (SCI)
        10. 4.3.2.10 Inter-Integrated Circuit Interface Module (I2C)
        11. 4.3.2.11 Standard Serial Peripheral Interface (SPI)
        12. 4.3.2.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        13. 4.3.2.13 Ethernet Controller
        14. 4.3.2.14 External Memory Interface (EMIF)
        15. 4.3.2.15 System Module Interface
        16. 4.3.2.16 Clock Inputs and Outputs
        17. 4.3.2.17 Test and Debug Modules Interface
        18. 4.3.2.18 Flash Supply and Test Pads
        19. 4.3.2.19 Reserved
        20. 4.3.2.20 No Connects
        21. 4.3.2.21 Supply for Core Logic: 1.2V nominal
        22. 4.3.2.22 Supply for I/O Cells: 3.3V nominal
        23. 4.3.2.23 Ground Reference for All Supplies Except VCCAD
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings Over Operating Free-Air Temperature Range
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Device Recommended Operating Conditions
    5. 5.5  Switching Characteristics Over Recommended Operating Conditions for Clock Domains
    6. 5.6  Wait States Required
    7. 5.7  Power Consumption Over Recommended Operating Conditions
    8. 5.8  Input/Output Electrical Characteristics Over Recommended Operating Conditions
    9. 5.9  Thermal Resistance Characteristics
    10. 5.10 Output Buffer Drive Strengths
    11. 5.11 Input Timings
    12. 5.12 Output Timings
    13. 5.13 Low-EMI Output Buffers
  6. 6System Information and Electrical Specifications
    1. 6.1  Device Power Domains
    2. 6.2  Voltage Monitor Characteristics
      1. 6.2.1 Important Considerations
      2. 6.2.2 Voltage Monitor Operation
      3. 6.2.3 Supply Filtering
    3. 6.3  Power Sequencing and Power On Reset
      1. 6.3.1 Power-Up Sequence
      2. 6.3.2 Power-Down Sequence
      3. 6.3.3 Power-On Reset: nPORRST
        1. 6.3.3.1 nPORRST Electrical and Timing Requirements
    4. 6.4  Warm Reset (nRST)
      1. 6.4.1 Causes of Warm Reset
      2. 6.4.2 nRST Timing Requirements
    5. 6.5  ARM Cortex-R4F CPU Information
      1. 6.5.1 Summary of ARM Cortex-R4F CPU Features
      2. 6.5.2 ARM Cortex-R4F CPU Features Enabled by Software
      3. 6.5.3 Dual Core Implementation
      4. 6.5.4 Duplicate clock tree after GCLK
      5. 6.5.5 ARM Cortex-R4F CPU Compare Module (CCM-R4) for Safety
      6. 6.5.6 CPU Self-Test
        1. 6.5.6.1 Application Sequence for CPU Self-Test
        2. 6.5.6.2 CPU Self-Test Clock Configuration
        3. 6.5.6.3 CPU Self-Test Coverage
    6. 6.6  Clocks
      1. 6.6.1 Clock Sources
        1. 6.6.1.1 Main Oscillator
          1. 6.6.1.1.1 Timing Requirements for Main Oscillator
        2. 6.6.1.2 Low Power Oscillator
          1. 6.6.1.2.1 Features
        3. 6.6.1.3 Phase Locked Loop (PLL) Clock Modules
          1. 6.6.1.3.1 Block Diagram
          2. 6.6.1.3.2 PLL Timing Specifications
        4. 6.6.1.4 External Clock Inputs
      2. 6.6.2 Clock Domains
        1. 6.6.2.1 Clock Domain Descriptions
        2. 6.6.2.2 Mapping of Clock Domains to Device Modules
        3. 6.6.2.3 Special Clock Source Selection Scheme for VCLKA4_DIVR_EMAC
      3. 6.6.3 Clock Test Mode
    7. 6.7  Clock Monitoring
      1. 6.7.1 Clock Monitor Timings
      2. 6.7.2 External Clock (ECLK) Output Functionality
      3. 6.7.3 Dual Clock Comparators
        1. 6.7.3.1 Features
        2. 6.7.3.2 Mapping of DCC Clock Source Inputs
    8. 6.8  Glitch Filters
    9. 6.9  Device Memory Map
      1. 6.9.1 Memory Map Diagram
      2. 6.9.2 Memory Map Table
      3. 6.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts
      4. 6.9.4 Master/Slave Access Privileges
      5. 6.9.5 Special Notes on Accesses to Certain Slaves
      6. 6.9.6 Parameter Overlay Module (POM) Considerations
    10. 6.10 Flash Memory
      1. 6.10.1 Flash Memory Configuration
      2. 6.10.2 Main Features of Flash Module
      3. 6.10.3 ECC Protection for Flash Accesses
      4. 6.10.4 Flash Access Speeds
      5. 6.10.5 Program Flash
      6. 6.10.6 Data Flash
    11. 6.11 Tightly Coupled RAM Interface Module
      1. 6.11.1 Features
      2. 6.11.2 TCRAM ECC Support
    12. 6.12 Parity Protection for Accesses to Peripheral RAMs
    13. 6.13 On-Chip SRAM Initialization and Testing
      1. 6.13.1 On-Chip SRAM Self-Test Using PBIST
        1. 6.13.1.1 Features
        2. 6.13.1.2 PBIST RAM Groups
      2. 6.13.2 On-Chip SRAM Auto Initialization
    14. 6.14 External Memory Interface (EMIF)
      1. 6.14.1 Features
      2. 6.14.2 Electrical and Timing Specifications
        1. 6.14.2.1 Asynchronous RAM
        2. 6.14.2.2 Synchronous Timing
    15. 6.15 Vectored Interrupt Manager
      1. 6.15.1 VIM Features
      2. 6.15.2 Interrupt Request Assignments
    16. 6.16 DMA Controller
      1. 6.16.1 DMA Features
      2. 6.16.2 Default DMA Request Map
    17. 6.17 Real Time Interrupt Module
      1. 6.17.1 Features
      2. 6.17.2 Block Diagrams
      3. 6.17.3 Clock Source Options
      4. 6.17.4 Network Time Synchronization Inputs
    18. 6.18 Error Signaling Module
      1. 6.18.1 Features
      2. 6.18.2 ESM Channel Assignments
    19. 6.19 Reset / Abort / Error Sources
    20. 6.20 Digital Windowed Watchdog
    21. 6.21 Debug Subsystem
      1. 6.21.1 Block Diagram
      2. 6.21.2 Debug Components Memory Map
      3. 6.21.3 JTAG Identification Code
      4. 6.21.4 Debug ROM
      5. 6.21.5 JTAG Scan Interface Timings
      6. 6.21.6 Advanced JTAG Security Module
      7. 6.21.7 Boundary Scan Chain
  7. 7Peripheral Information and Electrical Specifications
    1. 7.1  Enhanced Translator PWM Modules (ePWM)
      1. 7.1.1 ePWM Clocking and Reset
      2. 7.1.2 Synchronization of ePWMx Time Base Counters
      3. 7.1.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
      4. 7.1.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 7.1.5 ePWM Synchronization with External Devices
      6. 7.1.6 ePWM Trip Zones
        1. 7.1.6.1 Trip Zones TZ1n, TZ2n, TZ3n
        2. 7.1.6.2 Trip Zone TZ4n
        3. 7.1.6.3 Trip Zone TZ5n
        4. 7.1.6.4 Trip Zone TZ6n
      7. 7.1.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
      8. 7.1.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Timings
    2. 7.2  Enhanced Capture Modules (eCAP)
      1. 7.2.1 Clock Enable Control for eCAPx Modules
      2. 7.2.2 PWM Output Capability of eCAPx
      3. 7.2.3 Input Connection to eCAPx Modules
      4. 7.2.4 Enhanced Capture Module (eCAP) Timings
    3. 7.3  Enhanced Quadrature Encoder (eQEP)
      1. 7.3.1 Clock Enable Control for eQEPx Modules
      2. 7.3.2 Using eQEPx Phase Error to Trip ePWMx Outputs
      3. 7.3.3 Input Connections to eQEPx Modules
      4. 7.3.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing
    4. 7.4  Multibuffered 12bit Analog-to-Digital Converter
      1. 7.4.1 Features
      2. 7.4.2 Event Trigger Options
        1. 7.4.2.1 MIBADC1 Event Trigger Hookup
        2. 7.4.2.2 MIBADC2 Event Trigger Hookup
        3. 7.4.2.3 Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules
      3. 7.4.3 ADC Electrical and Timing Specifications
      4. 7.4.4 Performance (Accuracy) Specifications
        1. 7.4.4.1 MibADC Nonlinearity Errors
        2. 7.4.4.2 MibADC Total Error
    5. 7.5  General-Purpose Input/Output
      1. 7.5.1 Features
    6. 7.6  Enhanced High-End Timer (N2HET)
      1. 7.6.1 Features
      2. 7.6.2 N2HET RAM Organization
      3. 7.6.3 Input Timing Specifications
      4. 7.6.4 N2HET1-N2HET2 Synchronization
      5. 7.6.5 N2HET Checking
        1. 7.6.5.1 Internal Monitoring
        2. 7.6.5.2 Output Monitoring using Dual Clock Comparator (DCC)
      6. 7.6.6 Disabling N2HET Outputs
      7. 7.6.7 High-End Timer Transfer Unit (HTU)
        1. 7.6.7.1 Features
        2. 7.6.7.2 Trigger Connections
    7. 7.7  Controller Area Network (DCAN)
      1. 7.7.1 Features
      2. 7.7.2 Electrical and Timing Specifications
    8. 7.8  Local Interconnect Network Interface (LIN)
      1. 7.8.1 LIN Features
    9. 7.9  Serial Communication Interface (SCI)
      1. 7.9.1 Features
    10. 7.10 Inter-Integrated Circuit (I2C)
      1. 7.10.1 Features
      2. 7.10.2 I2C I/O Timing Specifications
    11. 7.11 Multibuffered / Standard Serial Peripheral Interface
      1. 7.11.1 Features
      2. 7.11.2 MibSPI Transmit and Receive RAM Organization
      3. 7.11.3 MibSPI Transmit Trigger Events
        1. 7.11.3.1 MIBSPI1 Event Trigger Hookup
        2. 7.11.3.2 MIBSPI3 Event Trigger Hookup
        3. 7.11.3.3 MIBSPI5 Event Trigger Hookup
      4. 7.11.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.11.5 SPI Slave Mode I/O Timings
    12. 7.12 Ethernet Media Access Controller
      1. 7.12.1 Ethernet MII Electrical and Timing Specifications
      2. 7.12.2 Ethernet RMII Electrical and Timing Specifications
      3. 7.12.3 Management Data Input/Output (MDIO)
  8. 8Device and Documentation Support
    1. 8.1 Device and Development-Support Tool Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation from Texas Instruments
      2. 8.2.2 Related Links
      3. 8.2.3 Community Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
    6. 8.6 Device Identification
      1. 8.6.1 Device Identification Code Register
      2. 8.6.2 Die Identification Registers
    7. 8.7 Module Certifications
      1. 8.7.1 DCAN Certification
      2. 8.7.2 LIN Certification
        1. 8.7.2.1 LIN Master Mode
        2. 8.7.2.2 LIN Slave Mode - Fixed Baud Rate
        3. 8.7.2.3 LIN Slave Mode - Adaptive Baud Rate
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Packaging Information

6 System Information and Electrical Specifications

6.1 Device Power Domains

The device core logic is split up into multiple power domains to optimize the Self-Test Clock Configuration power for a given application use case. There are 6 power domains in total: PD1, PD2, PD3, PD5, RAM_PD1, and RAM_PD2. Refer to Section 1.4 for more information.

PD1 is an "always-ON" power domain, which cannot be turned off. Each of the other power domains can be turned OFF one time during device initialization as per the application requirement. Refer to the Power Management Module (PMM) chapter of RM46x Technical Reference Manual (SPNU514) for more details.

NOTE

The clocks to a module must be turned off before powering down the core domain that contains the module.

NOTE

The logic in the modules that are powered down loses its power completely. Any access to modules that are powered down results in an abort being generated. When power is restored, the modules power-up to their default states (after normal power-up). No register or memory contents are preserved in the core domains that are turned off.

6.2 Voltage Monitor Characteristics

A voltage monitor is implemented on this device. The purpose of this voltage monitor is to eliminate the requirement for a specific sequence when powering up the core and I/O voltage supplies.

6.2.1 Important Considerations

  • The voltage monitor does not eliminate the need of a voltage supervisor circuit to ensure that the device is held in reset when the voltage supplies are out of range.
  • The voltage monitor only monitors the core supply (VCC) and the I/O supply (VCCIO). The other supplies are not monitored by the VMON. For example, if the VCCAD or VCCP are supplied from a source different from that for VCCIO, then there is no internal voltage monitor for the VCCAD and VCCP supplies.

6.2.2 Voltage Monitor Operation

The voltage monitor generates the Power Good MCU signal (PGMCU) as well as the I/Os Power Good IO signal (PGIO) on the device. During power-up or power-down, the PGMCU and PGIO are driven low when the core or I/O supplies are lower than the specified minimum monitoring thresholds. The PGIO and PGMCU being low isolates the core logic as well as the I/O controls during the power-up or power-down of the supplies. This allows the core and I/O supplies to be powered up or down in any order.

When the voltage monitor detects a low voltage on the I/O supply, it will assert a power-on reset. When the voltage monitor detects an out-of-range voltage on the core supply, it asynchronously makes all output pins high impedance, and asserts a power-on reset. The voltage monitor is disabled when the device enters a low power mode.

The VMON also incorporates a glitch filter for the nPORRST input. Refer to Section 6.3.3.1 for the timing information on this glitch filter.

Table 6-1 Voltage Monitoring Specifications

PARAMETER MIN TYP MAX UNIT
VMON Voltage monitoring thresholds VCC low - VCC level below this threshold is detected as too low. 0.75 0.9 1.13 V
VCC high - VCC level above this threshold is detected as too high. 1.40 1.7 2.1
VCCIO low - VCCIO level below this threshold is detected as too low. 1.85 2.4 2.9

6.2.3 Supply Filtering

The VMON has the capability to filter glitches on the VCC and VCCIO supplies.

The following table shows the characteristics of the supply filtering. Glitches in the supply larger than the maximum specification cannot be filtered.

Table 6-2 VMON Supply Glitch Filtering Capability

Parameter MIN MAX
Width of glitch on VCC that can be filtered 250 ns 1 µs
Width of glitch on VCCIO that can be filtered 250 ns 1 µs

6.3 Power Sequencing and Power On Reset

6.3.1 Power-Up Sequence

There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The power-up sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (see Table 6-4 for more details), core voltage rising above the minimum core supply threshold and the release of power-on reset. The high frequency oscillator will start up first and its amplitude will grow to an acceptable level. The oscillator start up time is dependent on the type of oscillator and is provided by the oscillator vendor. The different supplies to the device can be powered up in any order.

The device goes through the following sequential phases during power up.

Table 6-3 Power-Up Phases

Oscillator start-up and validity check 1032 oscillator cycles
eFuse autoload 1160 oscillator cycles
Flash pump power-up 688 oscillator cycles
Flash bank power-up 617 oscillator cycles
Total 3497 oscillator cycles

The CPU reset is released at the end of the above sequence and fetches the first instruction from address 0x00000000.

6.3.2 Power-Down Sequence

The different supplies to the device can be powered down in any order.

6.3.3 Power-On Reset: nPORRST

This is the power-on reset. This reset must be asserted by an external circuitry whenever the I/O or core supplies are outside the specified recommended range. This signal has a glitch filter on it. It also has an internal pulldown.

6.3.3.1 nPORRST Electrical and Timing Requirements

Table 6-4 Electrical Requirements for nPORRST

NO Parameter MIN MAX Unit
VCCPORL VCC low supply level when nPORRST must be active during power-up 0.5 V
VCCPORH VCC high supply level when nPORRST must remain active during power-up and become active during power down 1.14 V
VCCIOPORL VCCIO / VCCP low supply level when nPORRST must be active during power-up 1.1 V
VCCIOPORH VCCIO / VCCP high supply level when nPORRST must remain active during power-up and become active during power down 3.0 V
VIL(PORRST) Low-level input voltage of nPORRST VCCIO > 2.5V 0.2 * VCCIO V
Low-level input voltage of nPORRST VCCIO < 2.5V 0.5 V
3 tsu(PORRST) Setup time, nPORRST active before VCCIO and VCCP > VCCIOPORL during power-up 0 ms
6 th(PORRST) Hold time, nPORRST active after VCC > VCCPORH 1 ms
7 tsu(PORRST) Setup time, nPORRST active before VCC < VCCPORH during power down 2 µs
8 th(PORRST) Hold time, nPORRST active after VCCIO and VCCP > VCCIOPORH 1 ms
9 th(PORRST) Hold time, nPORRST active after VCC < VCCPORL 0 ms
tf(nPORRST)

Filter time nPORRST pin;

pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset.

475 2000 ns
RM46L440 RM46L840 nporrst_timing_pns160.gifFigure 6-1 nPORRST Timing Diagram

6.4 Warm Reset (nRST)

This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the output buffer is implemented as an open drain (drives low only). To ensure an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.

This terminal has a glitch filter. It also has an internal pullup.

6.4.1 Causes of Warm Reset

Table 6-5 Causes of Warm Reset

DEVICE EVENT SYSTEM STATUS FLAG
Power-Up Reset Exception Status Register, bit 15
Oscillator fail Global Status Register, bit 0
PLL slip Global Status Register, bits 8 and 9
Watchdog exception / Debugger reset Exception Status Register, bit 13
Software Reset Exception Status Register, bit 4
External Reset Exception Status Register, bit 3

6.4.2 nRST Timing Requirements

Table 6-6 nRST Timing Requirements

PARAMETER MIN MAX UNIT
tv(RST) Valid time, nRST active after nPORRST inactive 2256 tc(OSC)(1) ns
Valid time, nRST active (all other System reset conditions) 32 tc(VCLK)
tf(nRST)

Filter time nRST pin;

pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset

475 2000 ns
(1) Assumes the oscillator has started up and stabilized before nPORRST is released ..

6.5 ARM Cortex-R4F CPU Information

6.5.1 Summary of ARM Cortex-R4F CPU Features

The features of the ARM Cortex-R4F CPU include:

  • An integer unit with integral Embedded ICE-RT logic.
  • High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI) for Level two (L2) master and slave interfaces.
  • Floating Point Coprocessor
  • Dynamic branch prediction with a global history buffer, and a 4-entry return stack
  • Low interrupt latency.
  • Non-maskable interrupt.
  • A Harvard Level one (L1) memory system with:
    • Tightly-Coupled Memory (TCM) interfaces with support for error correction or parity checking memories
    • ARMv7-R architecture Memory Protection Unit (MPU) with 12 regions
  • Dual core logic for fault detection in safety-critical applications.
  • An L2 memory interface:
    • Single 64-bit master AXI interface
    • 64-bit slave AXI interface to TCM RAM blocks
  • A debug interface to a CoreSight Debug Access Port (DAP).
  • Six Hardware Breakpoints
  • Two Watchpoints
  • A Performance Monitoring Unit (PMU).
  • A Vectored Interrupt Controller (VIC) port.

For more information on the ARM Cortex-R4F CPU, see www.arm.com.

6.5.2 ARM Cortex-R4F CPU Features Enabled by Software

The following CPU features are disabled on reset and must be enabled by the application if required.

  • ECC On Tightly-Coupled Memory (TCM) Accesses
  • Hardware Vectored Interrupt (VIC) Port
  • Floating Point Coprocessor
  • Memory Protection Unit (MPU)

6.5.3 Dual Core Implementation

The device has two Cortex-R4F cores, where the output signals of both CPUs are compared in the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by 2 clock cycles as shown in Figure 6-3.

The CPUs have a diverse CPU placement given by following requirements:

  • different orientation; for example, CPU1 = "north" orientation, CPU2 = "flip west" orientation
  • dedicated guard ring for each CPU
RM46L440 RM46L840 dual_cpu_orient.gifFigure 6-2 Dual - CPU Orientation

6.5.4 Duplicate clock tree after GCLK

The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the 2nd CPU running at the same frequency and in phase to the clock of CPU1. See Figure 6-3.

6.5.5 ARM Cortex-R4F CPU Compare Module (CCM-R4) for Safety

This device has two ARM Cortex-R4F CPU cores, where the output signals of both CPUs are compared in the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed in a different way as shown in the figure below.

RM46L440 RM46L840 dual_core_implementation_pns160.gifFigure 6-3 Dual Core Implementation

To avoid an erroneous CCM-R4 compare error, the application software must initialize the registers of both CPUs before the registers are used, including function calls where the register values are pushed onto the stack.

6.5.6 CPU Self-Test

The CPU STC (Self-Test Controller) is used to test the two Cortex-R4F CPU Cores using the Deterministic Logic BIST Controller as the test engine.

The main features of the self-test controller are:

  • Ability to divide the complete test run into independent test intervals
  • Capable of running the complete test as well as running few intervals at a time
  • Ability to continue from the last executed interval (test set) as well as ability to restart from the beginning (First test set)
  • Complete isolation of the self-tested CPU core from rest of the system during the self-test run
  • Ability to capture the Failure interval number
  • Timeout counter for the CPU self-test run as a fail-safe feature

6.5.6.1 Application Sequence for CPU Self-Test

  1. Configure clock domain frequencies.
  2. Select number of test intervals to be run.
  3. Configure the timeout period for the self-test run.
  4. Enable self-test.
  5. Wait for CPU reset.
  6. In the reset handler, read CPU self-test status to identify any failures.
  7. Retrieve CPU state if required.

For more information see RM46x Technical Reference Manual (SPNU514).

6.5.6.2 CPU Self-Test Clock Configuration

The maximum clock rate for the self-test is 100MHz. The STCCLK is divided down from the CPU clock. This divider is configured by the STCCLKDIV register at address 0xFFFFE108.

For more information see RM46x Technical Reference Manual (SPNU514).

6.5.6.3 CPU Self-Test Coverage

Table 6-7 shows CPU test coverage achieved for each self-test interval. It also lists the cumulative test cycles. The test time can be calculated by multiplying the number of test cycles with the STC clock period.

Table 6-7 CPU Self-Test Coverage

INTERVALS TEST COVERAGE, % TEST CYCLES
0 0 0
1 62.13 1365
2 70.09 2730
3 74.49 4095
4 77.28 5460
5 79.28 6825
6 80.90 8190
7 82.02 9555
8 83.10 10920
9 84.08 12285
10 84.87 13650
11 85.59 15015
12 86.11 16380
13 86.67 17745
14 87.16 19110
15 87.61 20475
16 87.98 21840
17 88.38 23205
18 88.69 24570
19 88.98 25935
20 89.28 27300
21 89.50 28665
22 89.76 30030
23 90.01 31395
24 90.21 32760

6.6 Clocks

6.6.1 Clock Sources

The table below lists the available clock sources on the device. Each of the clock sources can be enabled or disabled using the CSDISx registers in the system module. The clock source number in the table corresponds to the control bit in the CSDISx register for that clock source.

The table also shows the default state of each clock source.

Table 6-8 Available Clock Sources

Clock Source # Name Description Default State
0 OSCIN Main Oscillator Enabled
1 PLL1 Output From PLL1 Disabled
2 Reserved Reserved Disabled
3 EXTCLKIN1 External Clock Input #1 Disabled
4 LFLPO Low Frequency Output of Internal Reference Oscillator Enabled
5 HFLPO High Frequency Output of Internal Reference Oscillator Enabled
6 PLL2 Output From PLL2 Disabled
7 EXTCLKIN2 External Clock Input #2 Disabled

6.6.1.1 Main Oscillator

The oscillator is enabled by connecting the appropriate fundamental resonator/crystal and load capacitors across the external OSCIN and OSCOUT pins as shown in Figure 6-4. The oscillator is a single stage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and low power modes.

TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature/voltage extremes.

An external oscillator source can be used by connecting a 3.3 V clock signal to the OSCIN pin and leaving the OSCOUT pin unconnected (open) as shown in the figure below.

RM46L440 RM46L840 clock_connection_pns160.gifFigure 6-4 Recommended Crystal/Clock Connection

6.6.1.1.1 Timing Requirements for Main Oscillator

Table 6-9 Timing Requirements for Main Oscillator

Parameter MIN Type MAX Unit
tc(OSC) Cycle time, OSCIN (when using a sine-wave input) 50 200 ns
tc(OSC_SQR) Cycle time, OSCIN, (when input to the OSCIN is a square wave ) 50 200 ns
tw(OSCIL) Pulse duration, OSCIN low (when input to the OSCIN is a square wave) 15 ns
tw(OSCIH) Pulse duration, OSCIN high (when input to the OSCIN is a square wave) 15 ns

6.6.1.2 Low Power Oscillator

The Low Power Oscillator (LPO) is comprised of two oscillators — HF LPO and LF LPO, in a single macro.

6.6.1.2.1 Features

The main features of the LPO are:

  • Supplies a clock at extremely low power for power-saving modes. This is connected as clock source # 4 of the Global Clock Module.
  • Supplies a high-frequency clock for non-timing-critical systems. This is connected as clock source # 5 of the Global Clock Module.
  • Provides a comparison clock for the crystal oscillator failure detection circuit.

RM46L440 RM46L840 LPO_Block_Diagram_pns185.gifFigure 6-5 LPO Block Diagram

Figure 6-5 shows a block diagram of the internal reference oscillator. This is a low power oscillator (LPO) and provides two clock sources: one nominally 80KHz and one nominally 10MHz.

Table 6-10 LPO Specifications

Parameter MIN Typical MAX Unit
Clock Detection oscillator fail frequency - lower threshold, using untrimmed LPO output 1.375 2.4 4.875 MHz
oscillator fail frequency - higher threshold, using untrimmed LPO output 22 38.4 78 MHz
LPO - HF oscillator (fHFLPO) untrimmed frequency 5.5 9 19.5 MHz
trimmed frequency 8 9.6 11 MHz
startup time from STANDBY (LPO BIAS_EN High for at least 900µs) 10 µs
cold startup time 900 µs
LPO - LF oscillator untrimmed frequency 36 85 180 kHz
startup time from STANDBY (LPO BIAS_EN High for at least 900µs) 100 µs
cold startup time 2000 µs

6.6.1.3 Phase Locked Loop (PLL) Clock Modules

The PLL is used to multiply the input frequency to some higher frequency.

The main features of the PLL are:

  • Frequency modulation can be optionally superimposed on the synthesized frequency of PLL1. The frequency modulation capability of PLL2 is permanently disabled.
  • Configurable frequency multipliers and dividers.
  • Built-in PLL Slip monitoring circuit.
  • Option to reset the device on a PLL slip detection.

6.6.1.3.1 Block Diagram

Figure 6-6 shows a high-level block diagram of the two PLL macros on this microcontroller. PLLCTL1 and PLLCTL2 are used to configure the multiplier and dividers for the PLL1. PLLCTL3 is used to configure the multiplier and dividers for PLL2.

RM46L440 RM46L840 FMzPLLx_block_diagram_pns160.gifFigure 6-6 PLLx Block Diagram

6.6.1.3.2 PLL Timing Specifications

Table 6-11 PLL Timing Specifications

PARAMETER MIN MAX UNIT
fINTCLK PLL1 Reference Clock frequency 1 f(OSC_SQR) MHz
fpost_ODCLK Post-ODCLK – PLL1 Post-divider input clock frequency 400 MHz
fVCOCLK VCOCLK – PLL1 Output Divider (OD) input clock frequency 150 550 MHz
fINTCLK2 PLL2 Reference Clock frequency 1 f(OSC_SQR) MHz
fpost_ODCLK2 Post-ODCLK – PLL2 Post-divider input clock frequency 400 MHz
fVCOCLK2 VCOCLK – PLL2 Output Divider (OD) input clock frequency 150 550 MHz

6.6.1.4 External Clock Inputs

The device supports up to two external clock inputs. This clock input must be a square wave input. The electrical and timing requirements for these clock inputs are specified below. The external clock sources are not checked for validity. They are assumed valid when enabled.

Table 6-12 External Clock Timing and Electrical Specifications

Parameter Description Min Max Unit
fEXTCLKx External clock input frequency 80 MHz
tw(EXTCLKIN)H EXTCLK high-pulse duration 6 ns
tw(EXTCLKIN)L EXTCLK low-pulse duration 6 ns
viL(EXTCLKIN) Low-level input voltage -0.3 0.8 V
viH(EXTCLKIN) High-level input voltage 2 VCCIO + 0.3 V

6.6.2 Clock Domains

6.6.2.1 Clock Domain Descriptions

The table below lists the device clock domains and their default clock sources. The table also shows the system module control register that is used to select an available clock source for each clock domain.

Table 6-13 Clock Domain Descriptions

Clock Domain Name Default Clock Source Clock Source Selection Register Description
HCLK OSCIN GHVSRC
  • Is disabled through the CDDISx registers bit 1
  • Used for all system modules including DMA, ESM
GCLK OSCIN GHVSRC
  • Always the same frequency as HCLK
  • In phase with HCLK
  • Is disabled separately from HCLK through the CDDISx registers bit 0
  • Can be divided by 1up to 8 when running CPU self-test (LBIST) using the CLKDIV field of the STCCLKDIV register at address 0xFFFFE108
GCLK2 OSCIN GHVSRC
  • Always the same frequency as GCLK
  • 2 cycles delayed from GCLK
  • Is disabled along with GCLK
  • Gets divided by the same divider setting as that for GCLK when running CPU self-test (LBIST)
VCLK OSCIN GHVSRC
  • Divided down from HCLK
  • Can be HCLK/1, HCLK/2, ... or HCLK/16
  • Is disabled separately from HCLK through the CDDISx registers bit 2
VCLK2 OSCIN GHVSRC
  • Divided down from HCLK
  • Can be HCLK/1, HCLK/2, ... or HCLK/16
  • Frequency must be an integer multiple of VCLK frequency
  • Is disabled separately from HCLK through the CDDISx registers bit 3
VCLK3 OSCIN GHVSRC
  • Divided down from HCLK
  • Can be HCLK/1, HCLK/2, ... or HCLK/16
  • Is disabled separately from HCLK through the CDDISx registers bit 8
VCLK4 OSCIN GHVSRC
  • Divided down from HCLK
  • Can be HCLK/1, HCLK/2, ... or HCLK/16
  • Is disabled separately from HCLK through the CDDISx registers bit 9
VCLKA1 VCLK VCLKASRC
  • Defaults to VCLK as the source
  • Is disabled through the CDDISx registers bit 4
VCLKA2 VCLK VCLKASRC
  • Defaults to VCLK as the source
  • Is disabled through the CDDISx registers bit 5
VCLKA3_S VCLK VCLKACON1
  • Defaults to VCLK as the source
  • Frequency can be as fast as HCLK frequency.
  • Is disabled through the CDDISx registers bit 10
VCLKA3_DIVR VCLK VCLKACON1
  • Divided down from the VCLKA3_S using the VCLKA3R field of the VCLKACON1 register at address 0xFFFFE140
  • Frequency can be VCLKA3_S/1, VCLKA3_S/2, ..., or VCLKA3_S/8
  • Default frequency is VCLKA3_S/2
  • Is disabled separately through the VCLKACON1 register VCLKA3_DIV_CDDIS bit only if the VCLKA3_S clock is not disabled
VCLKA4_S VCLK VCLKACON1
  • Defaults to VCLK as the source
  • Frequency can be as fast as HCLK frequency
  • Is disabled through the CDDISx registers bit 11
VCLKA4_DIVR VCLK VCLKACON1
  • Divided down from the VCLKA4_S using the VCLKA4R field of the VCLKACON1 register at address 0xFFFFE140
  • Frequency can be VCLKA4_S/1, VCLKA4_S/2, ..., or VCLKA4_S/8
  • Default frequency is VCLKA4_S/2
  • Is disabled separately through the VCLKACON1 register VCLKA4_DIV_CDDIS bit only if the VCLKA4_S clock is not disabled
RTICLK VCLK RCLKSRC
  • Defaults to VCLK as the source
  • If a clock source other than VCLK is selected for RTICLK, then the RTICLK frequency must be less than or equal to VCLK/3
    • Application can ensure this by programming the RTI1DIV field of the RCLKSRC register, if necessary
  • Is disabled through the CDDISx registers bit 6

6.6.2.2 Mapping of Clock Domains to Device Modules

Each clock domain has a dedicated functionality as shown in the figures below.

RM46L440 RM46L840 dev_clock_domains_f4_spns185.gifFigure 6-7 Device Clock Domains

6.6.2.3 Special Clock Source Selection Scheme for VCLKA4_DIVR_EMAC

Some applications may need to use both the of Ethernet interfaces. The MII interface requires VCLKA4_DIVR_EMAC to be 25MHz and the RMII requires VCLKA4_DIVR_EMAC to be 50MHz.

These different frequencies are supported by adding special dedicated clock source selection options for the VCLKA4_DIVR_EMAC clock domain. This logic is shown in .

RM46L440 RM46L840 VCLKA4_DIVR_EMAC_option_spns192.gifFigure 6-8 VCLKA4_DIVR Source Selection Options

The PLL2 post_ODCLK is brought out as a separate output from the PLL wrapper module. There are two additional dividers implemented at the device-level to divide this PLL2 post_ODCLK by 8 and by 16.

As shown in , the VCLKA4_SRC configured through the system module VCLKACON1 control register is used to determine the clock source for the VCLKA4_S and VCLKA4_DIVR. An additional multiplexor is implemented to select between the VCLKA4_DIVR and the two additional clock sources – PLL2 post_ODCLK/8 and post_ODCLK/16.

The selection is done as shown in the following table.

Table 6-14 VCLKA4_DIVR_EMAC Clock Source Selection

VCLKA4_SRC from VCLKACON1[19–16] Clock Source for VCLKA4_DIVR_EMAC
0x0 OSCIN / VCLKA4R
0x1 PLL1CLK / VCLKA4R
0x2 Reserved
0x3 EXTCLKIN1 / VCLKA4R
0x4 LF LPO / VCLKA4R
0x5 HF LPO / VCLKA4R
0x6 PLL2CLK / VCLKA4R
0x7 EXTCLKIN2 / VCLKA4R

6.6.3 Clock Test Mode

The TMS570 platform architecture defines a special mode that allows various clock signals to be brought out on to the ECLK pin and N2HET1[12] device outputs. This mode is called the Clock Test mode. It is very useful for debugging purposes and can be configured through the CLKTEST register in the system module.

Table 6-15 Clock Test Mode Options

SEL_ECP_PIN
=
CLKTEST[3-0]
SIGNAL ON ECLK SEL_GIO_PIN
=
CLKTEST[11-8]
SIGNAL ON N2HET1[12]
0000 Oscillator 0000 Oscillator Valid Status
0001 Main PLL free-running clock output 0001 Main PLL Valid status
0010 Reserved 0010 Reserved
0011 EXTCLKIN1 0011 Reserved
0100 LFLPO 0100 Reserved
0101 HFLPO 0101 HFLPO Valid status
0110 Secondary PLL free-running clock output 0110 Secondary PLL Valid Status
0111 EXTCLKIN2 0111 Reserved
1000 GCLK 1000 LFLPO
1001 RTI Base 1001 Oscillator Valid status
1010 Reserved 1010 Oscillator Valid status
1011 VCLKA1 1011 Oscillator Valid status
1100 Reserved 1100 Oscillator Valid status
1101 VCLKA3_DIVR 1101 VCLKA3_S
1110 VCLKA4_DIVR 1110 VCLKA4_S
1111 Reserved 1111 Oscillator Valid status

6.7 Clock Monitoring

The LPO Clock Detect (LPOCLKDET) module consists of a clock monitor (CLKDET) and an internal low power oscillator (LPO).

The LPO provides two different clock sources – a low frequency (LFLPO) and a high frequency (HFLPO).

The CLKDET is a supervisor circuit for an externally supplied clock signal (OSCIN). In case the OSCIN frequency falls out of a frequency window, the CLKDET flags this condition in the global status register (GLBSTAT bit 0: OSC FAIL) and switches all clock domains sourced by OSCIN to the HFLPO clock (limp mode clock).

The valid OSCIN frequency range is defined as: fHFLPO / 4 < fOSCIN < fHFLPO * 4.

6.7.1 Clock Monitor Timings

For more information on LPO and Clock detection, refer to Table 6-10.

RM46L440 RM46L840 LPO_Clk_Detection_pns160.gifFigure 6-9 LPO and Clock Detection, Untrimmed HFLPO

6.7.2 External Clock (ECLK) Output Functionality

The ECLK pin can be configured to output a pre-scaled clock signal indicative of an internal device clock. This output can be externally monitored as a safety diagnostic.

6.7.3 Dual Clock Comparators

The Dual Clock Comparator (DCC) module determines the accuracy of selectable clock sources by counting the pulses of two independent clock sources (counter 0 and counter 1). If one clock is out of spec, an error signal is generated. For example, the DCC1 can be configured to use HFLPO as the reference clock (for counter 0) and VCLK as the "clock under test" (for counter 1). This configuration allows the DCC1 to monitor the PLL output clock when VCLK is using the PLL output as its source.

An additional use of this module is to measure the frequency of a selectable clock source, using the input clock as a reference, by counting the pulses of two independent clock sources. Counter 0 generates a fixed-width counting window after a preprogrammed number of pulses. Counter 1 generates a fixed-width pulse (1 cycle) after a pre-programmed number of pulses. This pulse sets as an error signal if counter 1 does not reach 0 within the counting window generated by counter 0.

6.7.3.1 Features

  • Takes two different clock sources as input to two independent counter blocks.
  • One of the clock sources is the known-good, or reference clock; the second clock source is the "clock under test."
  • Each counter block is programmable with initial, or seed values.
  • The counter blocks start counting down from their seed values at the same time; a mismatch from the expected frequency for the clock under test generates an error signal which is used to interrupt the CPU.

6.7.3.2 Mapping of DCC Clock Source Inputs

Table 6-16 DCC1 Counter 0 Clock Sources

CLOCK SOURCE [3:0] CLOCK NAME
others oscillator (OSCIN)
0x5 high frequency LPO
0xA test clock (TCK)

Table 6-17 DCC1 Counter 1 Clock Sources

KEY [3:0] CLOCK SOURCE [3:0] CLOCK NAME
others - N2HET1[31]
0x0 Main PLL free-running clock output
0x1 PLL #2 free-running clock output
0x2 low frequency LPO
0xA 0x3 high frequency LPO
0x4 reserved
0x5 EXTCLKIN1
0x6 EXTCLKIN2
0x7 reserved
0x8 - 0xF VCLK

Table 6-18 DCC2 Counter 0 Clock Sources

CLOCK SOURCE [3:0] CLOCK NAME
others oscillator (OSCIN)
0xA test clock (TCK)

Table 6-19 DCC2 Counter 1 Clock Sources

KEY [3:0] CLOCK SOURCE [3:0] CLOCK NAME
others - N2HET2[0]
0xA 00x0 - 0x7 Reserved
0x8 - 0xF VCLK

6.8 Glitch Filters

A glitch filter is present on the following signals.

Table 6-20 Glitch Filter Timing Specifications

Pin Parameter MIN MAX Unit
nPORRST tf(nPORRST)

Filter time nPORRST pin;

pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset(1)

475 2000 ns
nRST tf(nRST)

Filter time nRST pin;

pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset

475 2000 ns
TEST tf(TEST)

Filter time TEST pin;

pulses less than MIN will be filtered out, pulses greater than MAX will pass through

475 2000 ns
(1) The glitch filter design on the nPORRST signal is designed such that no size pulse will reset any part of the microcontroller (flash pump, I/O pins, etc.) without also generating a valid reset signal to the CPU.

6.9 Device Memory Map

6.9.1 Memory Map Diagram

The figures below show the device memory maps.

RM46L440 RM46L840 memory_map_spns185.gifFigure 6-10 Memory Map (RM46L840)
RM46L440 RM46L840 memory_map_f7f8_1MB128KB_spns185.gifFigure 6-11 Memory Map (RM46L440)

The Flash memory is mirrored to support ECC logic testing. The base address of the mirrored Flash image is 0x2000 0000.

6.9.2 Memory Map Table

Table 6-21 Device Memory Map

MODULE NAME FRAME CHIP SELECT FRAME ADDRESS RANGE FRAME SIZE ACTUAL SIZE RESPNSE FOR ACCESS TO UNIMPLEMENTED LOCATIONS IN FRAME
START END
Memories tightly coupled to the ARM Cortex-R4F CPU
TCM Flash CS0 0x0000_0000 0x00FF_FFFF 16MB 1.25MB
(1)
Abort
TCM RAM + RAM ECC CSRAM0 0x0800_0000 0x0BFF_FFFF 64MB 192KB(1)
Mirrored Flash Flash mirror frame 0x2000_0000 0x20FF_FFFF 16MB 1.25MB
(1)
External Memory Accesses
EMIF Chip Select 2 (asynchronous) EMIF select 2 0x6000_0000 0x63FF_FFFF 64MB 32KB Access to "Reserved" space will generate Abort
EMIF Chip Select 3 (asynchronous) EMIF select 3 0x6400_0000 0x67FF_FFFF 64MB 32KB
EMIF Chip Select 4 (asynchronous) EMIF select 4 0x6800_0000 0x6BFF_FFFF 64MB 32KB
EMIF Chip Select 0 (synchronous) EMIF select 0 0x8000_0000 0x87FF_FFFF 128MB 128MB
Flash Module Bus2 Interface
Customer OTP, TCM Flash Banks 0xF000_0000 0xF000_1FFF 8KB 4KB Abort
Customer OTP,
Bank 7
0xF000_E000 0xF000_FFFF 8KB 2KB
Customer OTP–ECC, TCM Flash Banks 0xF004_0000 0xF004_03FF 1KB 512B
Customer OTP–ECC,
Bank 7
0xF004_1C00 0xF004_1FFF 1KB 256B
TI OTP, TCM Flash Banks 0xF008_0000 0xF008_1FFF 8KB 4KB
TI OTP,
Bank 7
0xF008_E000 0xF008_FFFF 8KB 2KB
TI OTP–ECC, TCM Flash Banks 0xF00C_0000 0xF00C_03FF 1KB 512B
TI OTP–ECC,
Bank 7
0xF00C_1C00 0xF00C_1FFF 1KB 256B
Bank 7 – ECC 0xF010_0000 0xF013_FFFF 256KB 8KB
Bank 7 0xF020_0000 0xF03F_FFFF 2MB 64KB
Flash Data Space ECC 0xF040_0000 0xF04F_FFFF 1MB 160KB
Ethernet and EMIF slave interfaces
CPPI Memory Slave (Ethernet RAM) 0xFC52_0000 0xFC52_1FFF 8KB 8KB Abort
CPGMAC Slave (Ethernet Slave) 0xFCF7_8000 0xFCF7_87FF 2KB 2KB No error
CPGMACSS Wrapper (Ethernet Wrapper) 0xFCF7_8800 0xFCF7_88FF 256B 256B No error
Ethernet MDIO Interface 0xFCF7_8900 0xFCF7_89FF 256B 256B No error
EMIF Registers 0xFCFF_E800 0xFCFF_E8FF 256B 256B Abort
SCR5: Enhanced Timer Peripherals
ePWM1 0xFCF7_8C00 0xFCF7_8CFF 256B 256B Abort
ePWM2 0xFCF7_8D00 0xFCF7_8DFF 256B 256B Abort
ePWM3 0xFCF7_8E00 0xFCF7_8EFF 256B 256B Abort
ePWM4 0xFCF7_8F00 0xFCF7_8FFF 256B 256B Abort
ePWM5 0xFCF7_9000 0xFCF7_90FF 256B 256B Abort
ePWM6 0xFCF7_9100 0xFCF7_91FF 256B 256B Abort
ePWM7 0xFCF7_9200 0xFCF7_92FF 256B 256B Abort
eCAP1 0xFCF7_9300 0xFCF7_93FF 256B 256B Abort
eCAP2 0xFCF7_9400 0xFCF7_94FF 256B 256B Abort
eCAP3 0xFCF7_9500 0xFCF7_95FF 256B 256B Abort
eCAP4 0xFCF7_9600 0xFCF7_96FF 256B 256B Abort
eCAP5 0xFCF7_9700 0xFCF7_97FF 256B 256B Abort
eCAP6 0xFCF7_9800 0xFCF7_98FF 256B 256B Abort
eQEP1 0xFCF7_9900 0xFCF7_99FF 256B 256B Abort
eQEP2 0xFCF7_9A00 0xFCF7_9AFF 256B 256B Abort
Cyclic Redundancy Checker (CRC) Module Registers
CRC CRC frame 0xFE00_0000 0xFEFF_FFFF 16MB 512B Accesses above 0x200 generate abort.
Peripheral Memories
MIBSPI5 RAM PCS[5] 0xFF0A_0000 0xFF0B_FFFF 128KB 2KB Abort for accesses above 2KB
MIBSPI3 RAM PCS[6] 0xFF0C_0000 0xFF0D_FFFF 128KB 2KB Abort for accesses above 2KB
MIBSPI1 RAM PCS[7] 0xFF0E_0000 0xFF0F_FFFF 128KB 2KB Abort for accesses above 2KB
DCAN3 RAM PCS[13] 0xFF1A_0000 0xFF1B_FFFF 128KB 2KB Wrap around for accesses to unimplemented address offsets lower than 0x7FF. Abort generated for accesses beyond offset 0x800.
DCAN2 RAM PCS[14] 0xFF1C_0000 0xFF1D_FFFF 128KB 2KB Wrap around for accesses to unimplemented address offsets lower than 0x7FF. Abort generated for accesses beyond offset 0x800.
DCAN1 RAM PCS[15] 0xFF1E_0000 0xFF1F_FFFF 128KB 2KB Wrap around for accesses to unimplemented address offsets lower than 0x7FF. Abort generated for accesses beyond offset 0x800.
MIBADC2 RAM PCS[29] 0xFF3A_0000 0xFF3B_FFFF 128KB 8KB Wrap around for accesses to unimplemented address offsets lower than 0x1FFF. Abort generated for accesses beyond 0x1FFF.
MIBADC2 Look-Up Table 384B Look-Up Table for ADC2 wrapper. Starts at address offset 0x2000 and ends at address offset 0x217F. Wrap around for accesses between offsets 0x0180 and 0x3FFF. Abort generated for accesses beyond offset 0x4000.
MIBADC1 RAM PCS[31] 0xFF3E_0000 0xFF3F_FFFF 128KB 8KB Wrap around for accesses to unimplemented address offsets lower than 0x1FFF. Abort generated for accesses beyond 0x1FFF.
MibADC1 Look-Up Table 384B Look-Up Table for ADC1 wrapper. Starts at address offset 0x2000 and ends at address offset 0x217F. Wrap around for accesses between offsets 0x0180 and 0x3FFF. Abort generated for accesses beyond offset 0x4000.
N2HET2 RAM PCS[34] 0xFF44_0000 0xFF45_FFFF 128KB 16KB Wrap around for accesses to unimplemented address offsets lower than 0x3FFF. Abort generated for accesses beyond 0x3FFF.
N2HET1 RAM PCS[35] 0xFF46_0000 0xFF47_FFFF 128KB 16KB Wrap around for accesses to unimplemented address offsets lower than 0x3FFF. Abort generated for accesses beyond 0x3FFF.
HTU2 RAM PCS[38] 0xFF4C_0000 0xFF4D_FFFF 128KB 1KB Abort
HTU1 RAM PCS[39] 0xFF4E_0000 0xFF4F_FFFF 128KB 1KB Abort
Debug Components
CoreSight Debug ROM CSCS0 0xFFA0_0000 0xFFA0_0FFF 4KB 4KB Reads return zeros, writes have no effect
Cortex-R4F Debug CSCS1 0xFFA0_1000 0xFFA0_1FFF 4KB 4KB Reads return zeros, writes have no effect
POM CSCS4 0xFFA0_4000 0xFFA0_4FFF 4KB 4KB Abort
Peripheral Control Registers
HTU1 PS[22] 0xFFF7_A400 0xFFF7_A4FF 256B 256B Reads return zeros, writes have no effect
HTU2 PS[22] 0xFFF7_A500 0xFFF7_A5FF 256B 256B Reads return zeros, writes have no effect
N2HET1 PS[17] 0xFFF7_B800 0xFFF7_B8FF 256B 256B Reads return zeros, writes have no effect
N2HET2 PS[17] 0xFFF7_B900 0xFFF7_B9FF 256B 256B Reads return zeros, writes have no effect
GIO PS[16] 0xFFF7_BC00 0xFFF7_BDFF 512B 256B Reads return zeros, writes have no effect
MIBADC1 PS[15] 0xFFF7_C000 0xFFF7_C1FF 512B 512B Reads return zeros, writes have no effect
MIBADC2 PS[15] 0xFFF7_C200 0xFFF7_C3FF 512B 512B Reads return zeros, writes have no effect
I2C PS[10] 0xFFF7_D400 0xFFF7_D4FF 256B 256B Reads return zeros, writes have no effect
DCAN1 PS[8] 0xFFF7_DC00 0xFFF7_DDFF 512B 512B Reads return zeros, writes have no effect
DCAN2 PS[8] 0xFFF7_DE00 0xFFF7_DFFF 512B 512B Reads return zeros, writes have no effect
DCAN3 PS[7] 0xFFF7_E000 0xFFF7_E1FF 512B 512B Reads return zeros, writes have no effect
LIN PS[6] 0xFFF7_E400 0xFFF7_E4FF 256B 256B Reads return zeros, writes have no effect
SCI PS[6] 0xFFF7_E500 0xFFF7_E5FF 256B 256B Reads return zeros, writes have no effect
MibSPI1 PS[2] 0xFFF7_F400 0xFFF7_F5FF 512B 512B Reads return zeros, writes have no effect
SPI2 PS[2] 0xFFF7_F600 0xFFF7_F7FF 512B 512B Reads return zeros, writes have no effect
MibSPI3 PS[1] 0xFFF7_F800 0xFFF7_F9FF 512B 512B Reads return zeros, writes have no effect
SPI4 PS[1] 0xFFF7_FA00 0xFFF7_FBFF 512B 512B Reads return zeros, writes have no effect
MibSPI5 PS[0] 0xFFF7_FC00 0xFFF7_FDFF 512B 512B Reads return zeros, writes have no effect
System Modules Control Registers and Memories
DMA RAM PPCS0 0xFFF8_0000 0xFFF8_0FFF 4KB 4KB Abort
VIM RAM PPCS2 0xFFF8_2000 0xFFF8_2FFF 4KB 1KB Wrap around for accesses to unimplemented address offsets between 1KB and 4KB.
Flash Module PPCS7 0xFFF8_7000 0xFFF8_7FFF 4KB 4KB Abort
eFuse Controller PPCS12 0xFFF8_C000 0xFFF8_CFFF 4KB 4KB Abort
Power Management Module (PMM) PPSE0 0xFFFF_0000 0xFFFF_01FF 512B 512B Abort
PCR registers PPS0 0xFFFF_E000 0xFFFF_E0FF 256B 256B Reads return zeros, writes have no effect
System Module - Frame 2 (see SPNU514) PPS0 0xFFFF_E100 0xFFFF_E1FF 256B 256B Reads return zeros, writes have no effect
PBIST PPS1 0xFFFF_E400 0xFFFF_E5FF 512B 512B Reads return zeros, writes have no effect
STC PPS1 0xFFFF_E600 0xFFFF_E6FF 256B 256B Generates address error interrupt, if enabled
IOMM Multiplexing Control Module PPS2 0xFFFF_EA00 0xFFFF_EBFF 512B 512B Reads return zeros, writes have no effect
DCC1 PPS3 0xFFFF_EC00 0xFFFF_ECFF 256B 256B Reads return zeros, writes have no effect
DMA PPS4 0xFFFF_F000 0xFFFF_F3FF 1KB 1KB Reads return zeros, writes have no effect
DCC2 PPS5 0xFFFF_F400 0xFFFF_F4FF 256B 256B Reads return zeros, writes have no effect
ESM PPS5 0xFFFF_F500 0xFFFF_F5FF 256B 256B Reads return zeros, writes have no effect
CCMR4 PPS5 0xFFFF_F600 0xFFFF_F6FF 256B 256B Reads return zeros, writes have no effect
RAM ECC even PPS6 0xFFFF_F800 0xFFFF_F8FF 256B 256B Reads return zeros, writes have no effect
RAM ECC odd PPS6 0xFFFF_F900 0xFFFF_F9FF 256B 256B Reads return zeros, writes have no effect
RTI + DWWD PPS7 0xFFFF_FC00 0xFFFF_FCFF 256B 256B Reads return zeros, writes have no effect
VIM Parity PPS7 0xFFFF_FD00 0xFFFF_FDFF 256B 256B Reads return zeros, writes have no effect
VIM PPS7 0xFFFF_FE00 0xFFFF_FEFF 256B 256B Reads return zeros, writes have no effect
System Module - Frame 1 (see SPNU514) PPS7 0xFFFF_FF00 0xFFFF_FFFF 256B 256B Reads return zeros, writes have no effect
(1) The RM46L440 device has only 1MB of flash and 128KB of RAM

6.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts

Any CPU write access to a Normal or Device type memory, which generates a fault, will generate an imprecise abort. The imprecise abort exception is disabled by default and must be enabled for the CPU to handle this exception. The imprecise abort handling is enabled by clearing the "A" bit in the CPU’s program status register (CPSR).

6.9.4 Master/Slave Access Privileges

The table below lists the access permissions for each bus master on the device. A bus master is a module that can initiate a read or a write transaction on the device.

Each slave module on the main interconnect is listed in the table. A "Yes" indicates that the module listed in the "MASTERS" column can access that slave module.

Table 6-22 Master / Slave Access Matrix

MASTERS ACCESS MODE SLAVES ON MAIN SCR
Flash Module Bus2 Interface:
OTP, ECC, Bank 7
Non-CPU Accesses to Program Flash and CPU Data RAM CRC EMIF, Ethernet Slave Interfaces Peripheral Control Registers, All Peripheral Memories, And All System Module Control Registers And Memories
CPU READ User/Privilege Yes Yes Yes Yes Yes
CPU WRITE User/Privilege No Yes Yes Yes Yes
DMA User Yes Yes Yes Yes Yes
POM User Yes Yes Yes Yes Yes
DAP Privilege Yes Yes Yes Yes Yes
HTU1 Privilege No Yes Yes Yes Yes
HTU2 Privilege No Yes Yes Yes Yes
EMAC User No Yes No Yes No

6.9.5 Special Notes on Accesses to Certain Slaves

Write accesses to the Power Domain Management Module (PMM) control registers are limited to the CPU (master id = 1). The other masters can only read from these registers.

A debugger can also write to the PMM registers. The master-id check is disabled in debug mode.

The device contains dedicated logic to generate a bus error response on any access to a module that is in a power domain that has been turned OFF.

6.9.6 Parameter Overlay Module (POM) Considerations

  • The POM can map onto up to 8MB of the internal or external memory space. The starting address and the size of the memory overlay are configurable through the POM control registers. Care must be taken to ensure that the overlay is mapped on to available memory.
  • ECC must be disabled by software through CP15 in case POM overlay is enabled; otherwise ECC errors will be generated.
  • POM overlay must not be enabled when the flash and internal RAM memories are swapped through the MEM SWAP field of the Bus Matrix Module Control Register 1 (BMMCR1).
  • When POM is used to overlay the flash on to internal or external RAM, there is a bus contention possibility when another master accesses the TCM flash. This results in a system hang.
    • The POM implements a timeout feature to detect this exact scenario. The timeout needs to be enabled whenever POM overlay is enabled.
    • The timeout can be enabled by writing 1010 to the Enable TimeOut (ETO) field of the POM Global Control register (POMGLBCTRL, address = 0xFFA04000).
    • In case a read request by the POM cannot be completed within 32 HCLK cycles, the timeout (TO) flag is set in the POM Flag register (POMFLG, address = 0xFFA0400C). Also, an abort is generated to the CPU. This can be a prefetch abort for an instruction fetch or a data abort for a data fetch.
    • The prefetch- and data-abort handlers must be modified to check if the TO flag in the POM is set. If so, then the application can assume that the timeout is caused by a bus contention between the POM transaction and another master accessing the same memory region. The abort handlers need to clear the TO flag, so that any further aborts are not misinterpreted as having been caused due to a timeout from the POM.

6.10 Flash Memory

6.10.1 Flash Memory Configuration

Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense amplifiers, and control logic.

Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical construction constraints.

Flash Pump: A charge pump which generates all the voltages required for reading, programming, or erasing the flash banks.

Flash Module: Interface circuitry required between the host CPU and the flash banks and pump module.

Table 6-23 Flash Memory Banks and Sectors

Memory Arrays (or Banks) Sector No. Segment Low Address High Address
BANK0 (1.25MBytes)(1) 0 16K Bytes 0x0000_0000 0x0000_3FFF
1 16K Bytes 0x0000_4000 0x0000_7FFF
2 16K Bytes 0x0000_8000 0x0000_BFFF
3 16K Bytes 0x0000_C000 0x0000_FFFF
4 16K Bytes 0x0001_0000 0x0001_3FFF
5 16K Bytes 0x0001_4000 0x0001_7FFF
6 32K Bytes 0x0001_8000 0x0001_FFFF
7 128K Bytes 0x0002_0000 0x0003_FFFF
8 128K Bytes 0x0004_0000 0x0005_FFFF
9 128K Bytes 0x0006_0000 0x0007_FFFF
10 128K Bytes 0x0008_0000 0x0009_FFFF
11 128K Bytes 0x000A_0000 0x000B_FFFF
12 128K Bytes 0x000C_0000 0x000D_FFFF
13 128K Bytes 0x000E_0000 0x000F_FFFF
14(4) 128K Bytes 0x0010_0000 0x0011_FFFF
15(4) 128K Bytes 0x0012_0000 0x0013_FFFF
BANK7 (64KBytes) for EEPROM emulation(2)(3) 0 16K Bytes 0xF020_0000 0xF020_3FFF
1 16K Bytes 0xF020_4000 0xF020_7FFF
2 16K Bytes 0xF020_8000 0xF020_BFFF
3 16K Bytes 0xF020_C000 0xF020_FFFF
(1) The Flash banks are 144-bit wide bank with ECC support.
(2) The flash bank7 can be programmed while executing code from flash bank0.
(3) Code execution is not allowed from flash bank7.
(4) Sectors 14 and 15 are not accessible or included in the RM46L440 configuration.

6.10.2 Main Features of Flash Module

  • Support for multiple flash banks for program and/or data storage
  • Simultaneous read access on a bank while performing program or erase operation on any other bank
  • Integrated state machines to automate flash erase and program operations
  • Pipelined mode operation to improve instruction access interface bandwidth
  • Support for Single Error Correction Double Error Detection (SECDED) block inside Cortex-R4F CPU
    • Error address is captured for host system debugging
  • Support for a rich set of diagnostic features

6.10.3 ECC Protection for Flash Accesses

All accesses to the program flash memory are protected by Single Error Correction Double Error Detection (SECDED) logic embedded inside the CPU. The flash module provides 8 bits of ECC code for 64 bits of instructions or data fetched from the flash memory. The CPU calculates the expected ECC code based on the 64 bits received and compares it with the ECC code returned by the flash module. A single-bit error is corrected and flagged by the CPU, while a multibit error is only flagged. The CPU signals an ECC error through its Event bus. This signaling mechanism is not enabled by default and must be enabled by setting the "X" bit of the Performance Monitor Control Register, c9.

MRC p15,#0,r1,c9,c12,#0 ;Enabling Event monitor statesORR r1, r1, #0x00000010MCR p15,#0,r1,c9,c12,#0 ;Set 4th bit (‘X’) of PMNC registerMRC p15,#0,r1,c9,c12,#0

The application must also explicitly enable the CPU's ECC checking for accesses on the CPU's ATCM and BTCM interfaces. These are connected to the program flash and data RAM respectively. ECC checking for these interfaces can be done by setting the B1TCMPCEN, B0TCMPCEN and ATCMPCEN bits of the System Control coprocessor's Auxiliary Control Register, c1.

MRC p15, #0, r1, c1, c0, #1ORR r1, r1, #0x0e000000 ;Enable ECC checking for ATCM and BTCMsDMBMCR p15, #0, r1, c1, c0, #1

6.10.4 Flash Access Speeds

For information on flash memory access speeds and the relevant wait states required, refer to Section 5.6.

6.10.5 Program Flash

Table 6-24 Timing Requirements for Program Flash

Parameter MIN NOM MAX Unit
tprog(144bit) Wide Word (144bit) programming time 40 300 µs
tprog(Total) 1.25MByte programming time(1) -40°C to 105°C 13 s
0°C to 60°C, for first 25 cycles 3.3 6.6 s
terase(bank0) Sector/Bank erase time(2) -40°C to 105°C 0.03 4 s
0°C to 60°C, for first 25 cycles 16 100 ms
twec Write/erase cycles with 15 year Data Retention requirement -40°C to 105°C 1000 cycles
(1) This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes programming 144 bits at a time at the maximum specified operating frequency.
(2) During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase a sector.

6.10.6 Data Flash

Table 6-25 Timing Requirements for Data Flash

Parameter MIN NOM MAX Unit
tprog(144bit) Wide Word (144bit) programming time 40 300 µs
tprog(Total) EEPROM Emulation (bank 7) 64KByte programming time(1) -40°C to 105°C 660 ms
0°C to 60°C, for first 25 cycles 165 330 ms
terase(bank7) EEPROM Emulation (bank 7) Sector/Bank erase time (2) -40°C to 105°C 0.2 8 s
0°C to 60°C, for first 25 cycles 14 100 ms
twec Write/erase cycles with 15 year Data Retention requirement -40°C to 105°C 100000 cycles
(1) This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes programming 144 bits at a time at the maximum specified operating frequency.
(2) During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase a sector.

6.11 Tightly Coupled RAM Interface Module

Figure 6-12 illustrates the connection of the Tightly Coupled RAM (TCRAM) to the Cortex-R4F CPU.

RM46L440 RM46L840 tcram_fbd_spns185.gifFigure 6-12 TCRAM Block Diagram

6.11.1 Features

The features of the Tightly Coupled RAM (TCRAM) Module are:

  • Acts as slave to the BTCM interface of the Cortex-R4F CPU
  • Supports the internal ECC scheme of the CPU by providing 64-bit data and 8-bit ECC code
  • Monitors CPU Event Bus and generates single or multibit error interrupts
  • Stores addresses for single and multibit errors
  • Supports RAM trace module
  • Provides CPU address bus integrity checking by supporting parity checking on the address bus
  • Performs redundant address decoding for the RAM bank chip select and ECC select generation logic
  • Provides enhanced safety for the RAM addressing by implementing two 36-bit-wide byte-interleaved RAM banks and generating independent RAM access control signals to the two banks
  • Supports auto-initialization of the RAM banks along with the ECC bits
  • No support for bit-wise RAM accesses

6.11.2 TCRAM ECC Support

The TCRAM interface passes on the ECC code for each data read by the Cortex-R4F CPU from the RAM. It also stores the contents of the CPU ECC port in the ECC RAM when the CPU does a write to the RAM. The TCRAM interface monitors the CPU event bus and provides registers for indicating single/multibit errors and also for identifying the address that caused the single or multibit error. The event signaling and the ECC checking for the RAM accesses must be enabled inside the CPU.

For more information see RM46x Technical Reference Manual (SPNU514).

6.12 Parity Protection for Accesses to Peripheral RAMs

Accesses to some peripheral RAMs are protected by odd/even parity checking. During a read access the parity is calculated based on the data read from the peripheral RAM and compared with the good parity value stored in the parity RAM for that peripheral. If any word fails the parity check, the module generates a parity error signal that is mapped to the Error Signaling Module. The module also captures the peripheral RAM address that caused the parity error.

The parity protection for peripheral RAMs is not enabled by default and must be enabled by the application. Each individual peripheral contains control registers to enable the parity protection for accesses to its RAM.

NOTE

The CPU read access gets the actual data from the peripheral. The application can choose to generate an interrupt whenever a peripheral RAM parity error is detected.

6.13 On-Chip SRAM Initialization and Testing

6.13.1 On-Chip SRAM Self-Test Using PBIST

6.13.1.1 Features

  • Extensive instruction set to support various memory test algorithms
  • ROM-based algorithms allow application to run TI production-level memory tests
  • Independent testing of all on-chip SRAM

6.13.1.2 PBIST RAM Groups

Table 6-26 PBIST RAM Grouping

Memory RAM Group Test Clock MEM Type Test Pattern (Algorithm)
triple read
slow read
triple read
fast read
March 13N(1)
two port (cycles)
March 13N(1)
single port (cycles)
ALGO MASK 0x1 ALGO MASK 0x2 ALGO MASK 0x4 ALGO MASK 0x8
PBIST_ROM 1 ROM CLK ROM 24578 8194
STC_ROM 2 ROM CLK ROM 19586 6530
DCAN1 3 VCLK Dual Port 25200
DCAN2 4 VCLK Dual Port 25200
DCAN3 5 VCLK Dual Port 25200
ESRAM1(2) 6 HCLK Single Port 266280
MIBSPI1 7 VCLK Dual Port 33440
MIBSPI3 8 VCLK Dual Port 33440
MIBSPI5 9 VCLK Dual Port 33440
VIM 10 VCLK Dual Port 12560
MIBADC1 11 VCLK Dual Port 4200
DMA 12 HCLK Dual Port 18960
N2HET1 13 VCLK Dual Port 31680
HTU1 14 VCLK Dual Port 6480
MIBADC2 18 VCLK Dual Port 4200
N2HET2 19 VCLK Dual Port 31680
HTU2 20 VCLK Dual Port 6480
ESRAM5(3) 21 HCLK Single Port 266280
ESRAM6(4) 22 HCLK Single Port 266280
ETHERNET 23 VCLK3 Dual Port 8700
24 6360
25 Single Port 133160
(1) There are several memory testing algorithms stored in the PBIST ROM. However, TI recommends the March13N algorithm for application testing.
(2) ESRAM1: Address 0x08000000 - 0x0800FFFF
(3) ESRAM5: Address 0x08010000 - 0x0801FFFF
(4) ESRAM6: Address 0x08020000 - 0x0802FFFF, not available on the RM46L440 device.

The PBIST ROM clock frequency is limited to 100MHz, if 100MHz < HCLK <= HCLKmax, or HCLK, if HCLK <= 100MHz.

The PBIST ROM clock is divided down from HCLK. The divider is selected by programming the ROM_DIV field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58.

6.13.2 On-Chip SRAM Auto Initialization

This microcontroller allows some of the on-chip memories to be initialized through the Memory Hardware Initialization mechanism in the System module. This hardware mechanism allows an application to program the memory arrays with error detection capability to a known state based on their error detection scheme (odd/even parity or ECC).

The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects the memories that are to be initialized.

For more information on these registers see RM46x Technical Reference Manual (SPNU514).

The mapping of the different on-chip memories to the specific bits of the MSINENA registers is shown in Table 6-27.

Table 6-27 Memory Initialization

CONNECTING MODULE ADDRESS RANGE MSINENA REGISTER BIT #
BASE ADDRESS ENDING ADDRESS
RAM (PD#1) 0x08000000 0x0800FFFF 0(2)
RAM (RAM_PD#1) 0x08010000 0x0801FFFF 0(2)
RAM (RAM_PD#2)(1) 0x08020000 0x0802FFFF 0(2)
MIBSPI5 RAM 0xFF0A0000 0xFF0BFFFF 12(3)
MIBSPI3 RAM 0xFF0C0000 0xFF0DFFFF 11(3)
MIBSPI1 RAM 0xFF0E0000 0xFF0FFFFF 7(3)
DCAN3 RAM 0xFF1A0000 0xFF1BFFFF 10
DCAN2 RAM 0xFF1C0000 0xFF1DFFFF 6
DCAN1 RAM 0xFF1E0000 0xFF1FFFFF 5
MIBADC2 RAM 0xFF3A0000 0xFF3BFFFF 14
MIBADC1 RAM 0xFF3E0000 0xFF3FFFFF 8
N2HET2 RAM 0xFF440000 0xFF45FFFF 15
N2HET1 RAM 0xFF460000 0xFF47FFFF 3
HTU2 RAM 0xFF4C0000 0xFF4DFFFF 16
HTU1 RAM 0xFF4E0000 0xFF4FFFFF 4
DMA RAM 0xFFF80000 0xFFF80FFF 1
VIM RAM 0xFFF82000 0xFFF82FFF 2
Ethernet RAM (CPPI Memory Slave) 0xFC520000 0xFC521FFF n/a
(1) Not available in the RM46L440 configuration.
(2) The TCM RAM interface module has separate control bits to select the RAM power domain that is to be auto-initialized.
(3) The MibSPIx modules perform an initialization of the transmit and receive RAMs as soon as the module is released from its local reset.. This is independent of whether the application chooses to initialize the MibSPIx RAMs using the system module auto-initialization method. The MibSPIx module must be first brought out of its local reset in order to use the system module auto-initialization method.

6.14 External Memory Interface (EMIF)

6.14.1 Features

The EMIF includes many features to enhance the ease and flexibility of connecting to external asynchronous memories or SDRAM devices. The EMIF features includes support for:

  • 3 addressable chip select for asynchronous memories of up to 32KB each
  • 1 addressable chip select space for SDRAMs up to 128MB
  • 8 or 16-bit data bus width
  • Programmable cycle timings such as setup, strobe, and hold times as well as turnaround time
  • Select strobe mode
  • Extended Wait mode
  • Data bus parking

6.14.2 Electrical and Timing Specifications

6.14.2.1 Asynchronous RAM

RM46L440 RM46L840 emif_async_memory_read_timing_spns165.gifFigure 6-13 Asynchronous Memory Read Timing
RM46L440 RM46L840 emif_nwait_read_spns165.gifFigure 6-14 EMIFnWAIT Read Timing Requirements
RM46L440 RM46L840 emif_async_memory_write_timing_spns165.gifFigure 6-15 Asynchronous Memory Write Timing
RM46L440 RM46L840 emif_nwait_write_spns165.gifFigure 6-16 EMIFnWAIT Write Timing Requirements

Table 6-28 EMIF Asynchronous Memory Timing Requirements(1)

NO. Value Unit
MIN NOM MAX
Reads and Writes
E EMIF clock period 10 ns
2 tw(EM_WAIT) Pulse duration, EMIF_nWAIT assertion and deassertion 2E ns
Reads
12 tsu(EMDV-EMOEH) Setup time, EMIF_DATA[15:0] valid before EMIFnOE high 9 ns
13 th(EMOEH-EMDIV) Hold time, EMIF_DATA[15:0] valid after EMIF_nOE high 0 ns
14 tsu(EMOEL-EMWAIT) Setup Time, EMIF_nWAIT asserted before end of Strobe Phase(2) 4E+9 ns
Writes
28 tsu(EMWEL-EMWAIT) Setup Time, EMIF_nWAIT asserted before end of Strobe Phase(2) 4E+14 ns
(1) E = EMIF_CLK period in ns.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMIFnWAIT must be asserted to add extended wait states. Figure 6-14 and Figure 6-16 describe EMIF transactions that include extended wait states inserted during the STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles.

Table 6-29 EMIF Asynchronous Memory Switching Characteristics(1)(2)(3)

NO PARAMETER Value UNIT
MIN NOM MAX
Reads and Writes
1 td(TURNAROUND) Turnaround time (TA)*E - 4 (TA)*E (TA)*E + 3 ns
Reads
3 tc(EMRCYCLE) EMIF read cycle time (EW = 0) (RS+RST+RH)*E -3 (RS+RST+RH)*E (RS+RST+RH)*E + 3 ns
EMIF read cycle time (EW = 1) (RS+RST+RH+(EWC*16))*E -3 (RS+RST+RH+(EWC*16))*E (RS+RST+RH+(EWC*16))*E + 3 ns
4 tsu(EMCEL-EMOEL) Output setup time, EMIF_nCS[4:2] low to EMIF_nOE low (SS = 0) (RS)*E-6 (RS)*E (RS)*E+3 ns
Output setup time, EMIF_nCS[4:2] low to EMIF_nOE low (SS = 1) -6 0 +3 ns
5 th(EMOEH-EMCEH) Output hold time, EMIF_nOE high to EMIF_nCS[4:2] high (SS = 0) (RH)*E -3 (RH)*E (RH)*E + 5 ns
Output hold time, EMIF_nOE high to EMIF_nCS[4:2] high (SS = 1) -3 0 +5 ns
6 tsu(EMBAV-EMOEL) Output setup time, EMIF_BA[1:0] valid to EMIF_nOE low (RS)*E-6 (RS)*E (RS)*E+3 ns
7 th(EMOEH-EMBAIV) Output hold time, EMIF_nOE high to EMIF_BA[1:0] invalid (RH)*E-3 (RH)*E (RH)*E+5 ns
8 tsu(EMAV-EMOEL) Output setup time, EMIF_ADDR[12:0] valid to EMIFnOE low (RS)*E-6 (RS)*E (RS)*E+3 ns
9 th(EMOEH-EMAIV) Output hold time, EMIF_nOE high to EMIF_ADDR[12:0] invalid (RH)*E-3 (RH)*E (RH)*E+5 ns
10 tw(EMOEL) EMIF_nOE active low width (EW = 0) (RST)*E-3 (RST)*E (RST)*E+3 ns
EMIF_nOE active low width (EW = 1) (RST+(EWC*16)) *E-3 (RST+(EWC*16))*E (RST+(EWC*16)) *E+3 ns
11 td(EMWAITH-EMOEH) Delay time from EMIF_nWAIT deasserted to EMIF_nOE high 3E+9 4E 4E+20 ns
29 tsu(EMDQMV-EMOEL) Output setup time, EMIF_nDQM[1:0] valid to EMIF_nOE low (RS)*E-6 (RS)*E (RS)*E+3 ns
30 th(EMOEH-EMDQMIV) Output hold time, EMIF_nOE high to EMIF_nDQM[1:0] invalid (RH)*E-3 (RH)*E (RH)*E+5 ns
Writes
15 tc(EMWCYCLE) EMIF write cycle time (EW = 0) (WS+WST+WH)* E-3 (WS+WST+WH)*E (WS+WST+WH)* E+3 ns
EMIF write cycle time (EW = 1) (WS+WST+WH+( EWC*16))*E -3 (WS+WST+WH+(E WC*16))*E (WS+WST+WH+( EWC*16))*E + 3 ns
16 tsu(EMCEL-EMWEL) Output setup time, EMIF_nCS[4:2] low to EMIF_nWE low (SS = 0) (WS)*E -3 (WS)*E (WS)*E + 3 ns
Output setup time, EMIF_nCS[4:2] low to EMIF_nWE low (SS = 1) -3 0 +3 ns
17 th(EMWEH-EMCEH) Output hold time, EMIF_nWE high to EMIF_nCS[4:2] high (SS = 0) (WH)*E-3 (WH)*E (WH)*E+3 ns
Output hold time, EMIF_nWE high to EMIF_CS[4:2] high (SS = 1) -3 0 +3 ns
18 tsu(EMDQMV-EMWEL) Output setup time, EMIF_BA[1:0] valid to EMIF_nWE low (WS)*E-3 (WS)*E (WS)*E+3 ns
19 th(EMWEH-EMDQMIV) Output hold time, EMIF_nWE high to EMIF_BA[1:0] invalid (WH)*E-3 (WH)*E (WH)*E+3 ns
20 tsu(EMBAV-EMWEL) Output setup time, EMIF_BA[1:0] valid to EMIF_nWE low (WS)*E-3 (WS)*E (WS)*E+3 ns
21 th(EMWEH-EMBAIV) Output hold time, EMIF_nWE high to EMIF_BA[1:0] invalid (WH)*E-3 (WH)*E (WH)*E+3 ns
22 tsu(EMAV-EMWEL) Output setup time, EMIF_ADDR[12:0] valid to EMIF_nWE low (WS)*E-3 (WS)*E (WS)*E+3 ns
23 th(EMWEH-EMAIV) Output hold time, EMIF_nWE high to EMIF_ADDR[12:0] invalid (WH)*E-3 (WH)*E (WH)*E+3 ns
24 tw(EMWEL) EMIF_nWE active low width (EW = 0) (WST)*E-3 (WST)*E (WST)*E+3 ns
EMIF_nWE active low width (EW = 1) (WST+(EWC*16)) *E-3 (WST+(EWC*16))*E (WST+(EWC*16)) *E+3 ns
25 td(EMWAITH-EMWEH) Delay time from EMIF_nWAIT deasserted to EMIF_nWE high 3E+11 4E 4E+24 ns
26 tsu(EMDV-EMWEL) Output setup time, EMIF_DATA[15:0] valid to EMIF_nWE low (WS)*E-3 (WS)*E (WS)*E+3 ns
27 th(EMWEH-EMDIV) Output hold time, EMIF_nWE high to EMIF_DATA[15:0] invalid (WH)*E-3 (WH)*E (WH)*E+3 ns
31 tsu(EMDQMV-EMWEL) Output setup time, EMIF_nDQM[1:0] valid to EMIF_nWE low (WH)*E-3 (WH)*E (WH)*E+3 ns
32 th(EMWEH-EMDQMIV) Output hold time, EMIF_nWE high to EMIF_nDQM[1:0] invalid (WH)*E-3 (WH)*E (WH)*E+3 ns
(1) TA = Turnaround, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These parameters are programmed through the Asynchronous Bank and Asynchronous Wait Cycle Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–1], RH[8–1], WS[16–1], WST[64–1], WH[8–1], and MEWC[1–256]. See the RM46x Technical Reference Manual (SPNU514) for more information.
(2) E = EMIF_CLK period in ns.
(3) EWC = external wait cycles determined by EMIF_nWAIT input signal. EWC supports the following range of values. EWC[256–1]. Note that the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See the RM46x Technical Reference Manual (SPNU514) for more information.

6.14.2.2 Synchronous Timing

RM46L440 RM46L840 emif_sdram_read_pns160.gifFigure 6-17 Basic SDRAM Read Operation
RM46L440 RM46L840 emif_sdram_write_pns160.gifFigure 6-18 Basic SDRAM Write Operation

Table 6-30 EMIF Synchronous Memory Timing Requirements

NO. Parameter MIN MAX Unit
19 tsu(EMIFDV-EM_CLKH) Input setup time, read data valid on EMIF_DATA[15:0] before EMIF_CLK rising 2 ns
20 th(CLKH-DIV) Input hold time, read data valid on EMIF_DATA[15:0] after EMIF_CLK rising 2 ns

Table 6-31 EMIF Synchronous Memory Switching Characteristics

NO. Parameter MIN MAX Unit
1 tc(CLK) Cycle time, EMIF clock EMIF_CLK 20 ns
2 tw(CLK) Pulse width, EMIF clock EMIF_CLK high or low 5 ns
3 td(CLKH-CSV) Delay time, EMIF_CLK rising to EMIF_nCS[0] valid 13 ns
4 toh(CLKH-CSIV) Output hold time, EMIF_CLK rising to EMIF_nCS[0] invalid 1 ns
5 td(CLKH-DQMV) Delay time, EMIF_CLK rising to EMIF_nDQM[1:0] valid 13 ns
6 toh(CLKH-DQMIV) Output hold time, EMIF_CLK rising to EMIF_nDQM[1:0] invalid 1 ns
7 td(CLKH-AV) Delay time, EMIF_CLK rising to EMIF_ADDR[12:0] and EMIFBA[1:0] valid 13 ns
8 toh(CLKH-AIV) Output hold time, EMIF_CLK rising to EMIF_ADDR[12:0] and EMIF_BA[1:0] invalid 1 ns
9 td(CLKH-DV) Delay time, EMIF_CLK rising to EMIF_DATA[15:0] valid 13 ns
10 toh(CLKH-DIV) Output hold time, EMIF_CLK rising to EMIF_DATA[15:0] invalid 1 ns
11 td(CLKH-RASV) Delay time, EMIF_CLK rising to EMIF_nRAS valid 13 ns
12 toh(CLKH-RASIV) Output hold time, EMIF_CLK rising to EMIF_nRAS invalid 1 ns
13 td(CLKH-CASV) Delay time, EMIF_CLK rising to EMIF_nCAS valid 13 ns
14 toh(CLKH-CASIV) Output hold time, EMIF_CLK rising to EMIF_nCAS invalid 1 ns
15 td(CLKH-WEV) Delay time, EMIF_CLK rising to EMIF_nWE valid 13 ns
16 toh(CLKH-WEIV) Output hold time, EMIF_CLK rising to EMIF_nWE invalid 1 ns
17 tdis(CLKH-DHZ) Delay time, EMIF_CLK rising to EMIF_DATA[15:0] tri-stated 7 ns
18 tena(CLKH-DLZ) Output hold time, EMIF_CLK rising to EMIF_DATA[15:0] driving 1 ns

6.15 Vectored Interrupt Manager

The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling the many interrupt sources present on this device. Interrupts are caused by events outside of the normal flow of program execution. Normally, these events require a timely response from the central processing unit (CPU); therefore, when an interrupt occurs, the CPU switches execution from the normal program flow to an interrupt service routine (ISR).

6.15.1 VIM Features

The VIM module has the following features:

  • Supports 128 interrupt channels.
    • Provides programmable priority and enable for interrupt request lines.
  • Provides a direct hardware dispatch mechanism for fastest IRQ dispatch.
  • Provides two software dispatch mechanisms when the CPU VIC port is not used.
    • Index interrupt
    • Register vectored interrupt
  • Parity protected vector interrupt table against soft errors.

6.15.2 Interrupt Request Assignments

Table 6-32 Interrupt Request Assignments

Modules Interrupt Sources Default VIM Interrupt Channel
ESM ESM High level interrupt (NMI) 0
Reserved Reserved 1
RTI RTI compare interrupt 0 2
RTI RTI compare interrupt 1 3
RTI RTI compare interrupt 2 4
RTI RTI compare interrupt 3 5
RTI RTI overflow interrupt 0 6
RTI RTI overflow interrupt 1 7
RTI RTI timebase interrupt 8
GIO GIO interrupt A 9
N2HET1 N2HET1 level 0 interrupt 10
HTU1 HTU1 level 0 interrupt 11
MIBSPI1 MIBSPI1 level 0 interrupt 12
LIN LIN level 0 interrupt 13
MIBADC1 MIBADC1 event group interrupt 14
MIBADC1 MIBADC1 sw group 1 interrupt 15
DCAN1 DCAN1 level 0 interrupt 16
SPI2 SPI2 level 0 interrupt 17
Reserved Reserved 18
CRC CRC Interrupt 19
ESM ESM Low level interrupt 20
SYSTEM Software interrupt (SSI) 21
CPU PMU Interrupt 22
GIO GIO interrupt B 23
N2HET1 N2HET1 level 1 interrupt 24
HTU1 HTU1 level 1 interrupt 25
MIBSPI1 MIBSPI1 level 1 interrupt 26
LIN LIN level 1 interrupt 27
MIBADC1 MIBADC1 sw group 2 interrupt 28
DCAN1 DCAN1 level 1 interrupt 29
SPI2 SPI2 level 1 interrupt 30
MIBADC1 MIBADC1 magnitude compare interrupt 31
Reserved Reserved 32
DMA FTCA interrupt 33
DMA LFSA interrupt 34
DCAN2 DCAN2 level 0 interrupt 35
Reserved Reserved 36
MIBSPI3 MIBSPI3 level 0 interrupt 37
MIBSPI3 MIBSPI3 level 1 interrupt 38
DMA HBCA interrupt 39
DMA BTCA interrupt 40
EMIF AEMIFINT3 41
DCAN2 DCAN2 level 1 interrupt 42
Reserved Reserved 43
DCAN1 DCAN1 IF3 interrupt 44
DCAN3 DCAN3 level 0 interrupt 45
DCAN2 DCAN2 IF3 interrupt 46
FPU FPU interrupt 47
Reserved Reserved 48
SPI4 SPI4 level 0 interrupt 49
MIBADC2 MibADC2 event group interrupt 50
MIBADC2 MibADC2 sw group1 interrupt 51
Reserved Reserved 52
MIBSPI5 MIBSPI5 level 0 interrupt 53
SPI4 SPI4 level 1 interrupt 54
DCAN3 DCAN3 level 1 interrupt 55
MIBSPI5 MIBSPI5 level 1 interrupt 56
MIBADC2 MibADC2 sw group2 interrupt 57
Reserved Reserved 58
MIBADC2 MibADC2 magnitude compare interrupt 59
DCAN3 DCAN3 IF3 interrupt 60
FMC FSM_DONE interrupt 61
Reserved Reserved 62
N2HET2 N2HET2 level 0 interrupt 63
SCI SCI level 0 interrupt 64
HTU2 HTU2 level 0 interrupt 65
I2C I2C level 0 interrupt 66
Reserved Reserved 67-72
N2HET2 N2HET2 level 1 interrupt 73
SCI SCI level 1 interrupt 74
HTU2 HTU2 level 1 interrupt 75
Ethernet C0_MISC_PULSE 76
Ethernet C0_TX_PULSE 77
Ethernet C0_THRESH_PULSE 78
Ethernet C0_RX_PULSE 79
HWAG1 HWA_INT_REQ_H 80
HWAG2 HWA_INT_REQ_H 81
DCC1 DCC done interrupt 82
DCC2 DCC2 done interrupt 83
Reserved Reserved 84
PBIST Controller PBIST Done Interrupt 85
Reserved Reserved 86-87
HWAG1 HWA_INT_REQ_L 88
HWAG2 HWA_INT_REQ_L 89
ePWM1INTn ePWM1 Interrupt 90
ePWM1TZINTn ePWM1 Trip Zone Interrupt 91
ePWM2INTn ePWM2 Interrupt 92
ePWM2TZINTn ePWM2 Trip Zone Interrupt 93
ePWM3INTn ePWM3 Interrupt 94
ePWM3TZINTn ePWM3 Trip Zone Interrupt 95
ePWM4INTn ePWM4 Interrupt 96
ePWM4TZINTn ePWM4 Trip Zone Interrupt 97
ePWM5INTn ePWM5 Interrupt 98
ePWM5TZINTn ePWM5 Trip Zone Interrupt 99
ePWM6INTn ePWM6 Interrupt 100
ePWM6TZINTn ePWM6 Trip Zone Interrupt 101
ePWM7INTn ePWM7 Interrupt 102
ePWM7TZINTn ePWM7 Trip Zone Interrupt 103
eCAP1INTn eCAP1 Interrupt 104
eCAP2INTn eCAP2 Interrupt 105
eCAP3INTn eCAP3 Interrupt 106
eCAP4INTn eCAP4 Interrupt 107
eCAP5INTn eCAP5 Interrupt 108
eCAP6INTn eCAP6 Interrupt 109
eQEP1INTn eQEP1 Interrupt 110
eQEP2INTn eQEP2 Interrupt 111
Reserved Reserved 112-127

NOTE

Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR entry; therefore only request channels 0..126 can be used and are offset by 1 address in the VIM RAM.

NOTE

The EMIF_nWAIT signal has a pull-up on it. The EMIF module generates a "Wait Rise" interrupt whenever it detects a rising edge on the EMIF_nWAIT signal. This interrupt condition is indicated as soon as the device is powered up. This can be ignored if the EMIF_nWAIT signal is not used in the application. If the EMIF_nWAIT signal is actually used in the application, then the external slave memory must always drive the EMIF_nWAIT signal such that an interrupt is not caused due to the default pull-up on this signal.

NOTE

The lower-order interrupt channels are higher priority channels than the higher-order interrupt channels.

NOTE

The application can change the mapping of interrupt sources to the interrupt channels through the interrupt channel control registers (CHANCTRLx) inside the VIM module.

6.16 DMA Controller

The DMA controller is used to transfer data between two locations in the memory map in the background of CPU operations. Typically, the DMA is used to:

  • Transfer blocks of data between external and internal data memories
  • Restructure portions of internal data memory
  • Continually service a peripheral

6.16.1 DMA Features

  • CPU independent data transfer
  • One 64-bit master port that interfaces to the TMS570 Memory System.
  • FIFO buffer(4 entries deep and each 64bit wide)
  • Channel control information is stored in RAM protected by parity
  • 16 channels with individual enable
  • Channel chaining capability
  • 32 peripheral DMA requests
  • Hardware and Software DMA requests
  • 8, 16, 32 or 64-bit transactions supported
  • Multiple addressing modes for source/destination (fixed, increment, offset)
  • Auto-initiation
  • Power-management mode
  • Memory Protection with four configurable memory regions

6.16.2 Default DMA Request Map

The DMA module on this microcontroller has 16 channels and up to 32 hardware DMA requests. The module contains DREQASIx registers which are used to map the DMA requests to the DMA channels. By default, channel 0 is mapped to request 0, channel 1 to request 1, and so on.

Some DMA requests have multiple sources, as shown in Table 6-33. The application must ensure that only one of these DMA request sources is enabled at any time.

Table 6-33 DMA Request Line Connection

Modules DMA Request Sources DMA Request
MIBSPI1 MIBSPI1[1](1) DMAREQ[0]
MIBSPI1 MIBSPI1[0](2) DMAREQ[1]
SPI2 SPI2 receive DMAREQ[2]
SPI2 SPI2 transmit DMAREQ[3]
MIBSPI1 / MIBSPI3 / DCAN2 MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3 DMAREQ[4]
MIBSPI1 / MIBSPI3 / DCAN2 MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2 DMAREQ[5]
DCAN1 / MIBSPI5 DCAN1 IF2 / MIBSPI5[2] DMAREQ[6]
MIBADC1 / MIBSPI5 MIBADC1 event / MIBSPI5[3] DMAREQ[7]
MIBSPI1 / MIBSPI3 / DCAN1 MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1 DMAREQ[8]
MIBSPI1 / MIBSPI3 / DCAN2 MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1 DMAREQ[9]
MIBADC1 / I2C / MIBSPI5 MIBADC1 G1 / I2C receive / MIBSPI5[4] DMAREQ[10]
MIBADC1 / I2C / MIBSPI5 MIBADC1 G2 / I2C transmit / MIBSPI5[5] DMAREQ[11]
RTI / MIBSPI1 / MIBSPI3 RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6] DMAREQ[12]
RTI / MIBSPI1 / MIBSPI3 RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7] DMAREQ[13]
MIBSPI3 / MibADC2 / MIBSPI5 MIBSPI3[1](1) / MibADC2 event / MIBSPI5[6] DMAREQ[14]
MIBSPI3 / MIBSPI5 MIBSPI3[0](2) / MIBSPI5[7] DMAREQ[15]
MIBSPI1 / MIBSPI3 / DCAN1 / MibADC2 MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1 DMAREQ[16]
MIBSPI1 / MIBSPI3 / DCAN3 / MibADC2 MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2 DMAREQ[17]
RTI / MIBSPI5 RTI DMAREQ2 / MIBSPI5[8] DMAREQ[18]
RTI / MIBSPI5 RTI DMAREQ3 / MIBSPI5[9] DMAREQ[19]
N2HET1 / N2HET2 / DCAN3 N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3 IF2 DMAREQ[20]
N2HET1 / N2HET2 / DCAN3 N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3 IF3 DMAREQ[21]
MIBSPI1 / MIBSPI3 / MIBSPI5 MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10] DMAREQ[22]
MIBSPI1 / MIBSPI3 / MIBSPI5 MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11] DMAREQ[23]
N2HET1 / N2HET2 / SPI4 / MIBSPI5 N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12] DMAREQ[24]
N2HET1 / N2HET2 / SPI4 / MIBSPI5 N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13] DMAREQ[25]
CRC / MIBSPI1 / MIBSPI3 CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12] DMAREQ[26]
CRC / MIBSPI1 / MIBSPI3 CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13] DMAREQ[27]
LIN / MIBSPI5 LIN receive / MIBSPI5[14] DMAREQ[28]
LIN / MIBSPI5 LIN transmit / MIBSPI5[15] DMAREQ[29]
MIBSPI1 / MIBSPI3 / SCI / MIBSPI5 MIBSPI1[14] / MIBSPI3[14] / SCI receive / MIBSPI5[1](1) DMAREQ[30]
MIBSPI1 / MIBSPI3 / SCI / MIBSPI5 MIBSPI1[15] / MIBSPI3[15] / SCI transmit / MIBSPI5[0](2) DMAREQ[31]
(1) Receive DMA when configured in standard SPI mode
(2) Transmit DMA when configured in standard SPI mode

6.17 Real Time Interrupt Module

The real-time interrupt (RTI) module provides timer functionality for operating systems and for benchmarking code. The RTI module can incorporate several counters that define the timebases needed for scheduling an operating system.

The timers also allow you to benchmark certain areas of code by reading the values of the counters at the beginning and the end of the desired code range and calculating the difference between the values.

6.17.1 Features

The RTI module has the following features:

  • Two independent 64 bit counter blocks
  • Four configurable compares for generating operating system ticks or DMA requests. Each event can be driven by either counter block 0 or counter block 1.
  • Fast enabling/disabling of events
  • Two time-stamp (capture) functions for system or peripheral interrupts, one for each counter block

6.17.2 Block Diagrams

Figure 6-19 shows a high-level block diagram for one of the two 64-bit counter blocks inside the RTI module. Both the counter blocks are identical except the Network Time Unit (NTUx) inputs are only available as time base inputs for the counter block 0.

RM46L440 RM46L840 rti_counter_bd_pns160.gifFigure 6-19 Counter Block Diagram
RM46L440 RM46L840 rti_compare_bd_pns160.gifFigure 6-20 Compare Block Diagram

6.17.3 Clock Source Options

The RTI module uses the RTI1CLK clock domain for generating the RTI time bases.

The application can select the clock source for the RTI1CLK by configuring the RCLKSRC register in the System module at address 0xFFFFFF50. The default source for RTI1CLK is VCLK.

For more information on clock sources refer to Table 6-8 and Table 6-13.

6.17.4 Network Time Synchronization Inputs

The RTI module supports 4 Network Time Unit (NTU) inputs that signal internal system events, and which can be used to synchronize the time base used by the RTI module. On this device, these NTU inputs are connected as shown below.

Table 6-34 Network Time Synchronization Inputs

NTU Input Source
0 Reserved
1 Reserved
2 PLL2 Clock output
3 EXTCLKIN1 clock input

6.18 Error Signaling Module

The Error Signaling Module (ESM) manages the various error conditions on the TMS570 microcontroller. The error condition is handled based on a fixed severity level assigned to it. Any severe error condition can be configured to drive a low level on a dedicated device terminal called nERROR. This can be used as an indicator to an external monitor circuit to put the system into a safe state.

6.18.1 Features

The features of the Error Signaling Module are:

  • 128 interrupt/error channels are supported, divided into 3 different groups
    • 64 channels with maskable interrupt and configurable error pin behavior
    • 32 error channels with non-maskable interrupt and predefined error pin behavior
    • 32 channels with predefined error pin behavior only
  • Error pin to signal severe device failure
  • Configurable timebase for error signal
  • Error forcing capability

6.18.2 ESM Channel Assignments

The Error Signaling Module (ESM) integrates all the device error conditions and groups them in the order of severity. Group1 is used for errors of the lowest severity while Group3 is used for errors of the highest severity. The device response to each error is determined by the severity group it is connected to. Table 6-36 shows the channel assignment for each group.

Table 6-35 ESM Groups

ERROR GROUP INTERRUPT CHARACTERISTICS INFLUENCE ON ERROR PIN
Group1 maskable, low or high priority configurable
Group2 non-maskable, high priority fixed
Group3 no interrupt generated fixed

Table 6-36 ESM Channel Assignments

ERROR Condition Group Channels
Reserved Group1 0
MibADC2 - RAM parity error Group1 1
DMA - MPU configuration violation Group1 2
DMA - control packet RAM parity error Group1 3
Reserved Group1 4
DMA - error on DMA read access, imprecise error Group1 5
FMC - correctable ECC error: bus1 and bus2 interfaces
(does not include accesses to Bank 7)
Group1 6
N2HET1 - RAM parity error Group1 7
HTU1/HTU2 - dual-control packet RAM parity error Group1 8
HTU1/HTU2 - MPU configuration violation Group1 9
PLL1 - Slip Group1 10
Clock Monitor - oscillator fail Group1 11
Reserved Group1 12
DMA - error on DMA write access, imprecise error Group1 13
Reserved Group1 14
VIM RAM - parity error Group1 15
Reserved Group1 16
MibSPI1 - RAM parity error Group1 17
MibSPI3 - RAM parity error Group1 18
MibADC1 - RAM parity error Group1 19
Reserved Group1 20
DCAN1 - RAM parity error Group1 21
DCAN3 - RAM parity error Group1 22
DCAN2 - RAM parity error Group1 23
MibSPI5 - RAM parity error Group1 24
Reserved Group1 25
RAM even bank (B0TCM) - correctable ECC error Group1 26
CPU - self-test failed Group1 27
RAM odd bank (B1TCM) - correctable ECC error Group1 28
Reserved Group1 29
DCC1 - error Group1 30
CCM-R4 - self-test failed Group1 31
Reserved Group1 32
Reserved Group1 33
N2HET2 - RAM parity error Group1 34
FMC - correctable ECC error (Bank 7 access) Group1 35
FMC - uncorrectable ECC error (Bank 7 access) Group1 36
IOMM - Access to unimplemented location in IOMM frame, or write access detected in unprivileged mode Group1 37
Power domain controller compare error Group1 38
Power domain controller self-test error Group1 39
eFuse Controller Error – this error signal is generated when any bit in the eFuse controller error status register is set. The application can choose to generate an interrupt whenever this bit is set to service any eFuse controller error conditions. Group1 40
eFuse Controller - Self Test Error. This error signal is generated only when a self test on the eFuse controller generates an error condition. When an ECC self test error is detected, group 1 channel 40 error signal will also be set. Group1 41
PLL#2 - Slip Group1 42
Ethernet Controller bus master access error Group1 43
Reserved Group1 44
Reserved Group1 45
Reserved Group1 46
Reserved Group1 47
Reserved Group1 48
Reserved Group1 49
Reserved Group1 50
Reserved Group1 51
Reserved Group1 52
Reserved Group1 53
Reserved Group1 54
Reserved Group1 55
Reserved Group1 56
Reserved Group1 57
Reserved Group1 58
Reserved Group1 59
Reserved Group1 60
Reserved Group1 61
DCC2 - error Group1 62
Reserved Group1 63
Reserved Group2 0
Reserved Group2 1
CCMR4 - dual-CPU lock-step error Group2 2
Reserved Group2 3
FMC - uncorrectable address parity error on accesses to main flash Group2 4
Reserved Group2 5
RAM even bank (B0TCM) - uncorrectable redundant address decode error Group2 6
Reserved Group2 7
RAM odd bank (B1TCM) - uncorrectable redundant address decode error Group2 8
Reserved Group2 9
RAM even bank (B0TCM) - address bus parity error Group2 10
Reserved Group2 11
RAM odd bank (B1TCM) - address bus parity error Group2 12
Reserved Group2 13
Reserved Group2 14
Reserved Group2 15
TCM - ECC live lock detect Group2 16
Reserved Group2 17
Reserved Group2 18
Reserved Group2 19
Reserved Group2 20
Reserved Group2 21
Reserved Group2 22
Reserved Group2 23
Windowed Watchdog (WWD) violation Group2 24
Reserved Group2 25
Reserved Group2 26
Reserved Group2 27
Reserved Group2 28
Reserved Group2 29
Reserved Group2 30
Reserved Group2 31
Reserved Group3 0
eFuse Farm - autoload error Group3 1
Reserved Group3 2
RAM even bank (B0TCM) - ECC uncorrectable error Group3 3
Reserved Group3 4
RAM odd bank (B1TCM) - ECC uncorrectable error Group3 5
Reserved Group3 6
FMC - uncorrectable ECC error: ATCM and Flash OTP interfaces
(does not include address parity error and errors on accesses to Bank 7 data memory)
Group3 7
Reserved Group3 8
Reserved Group3 9
Reserved Group3 10
Reserved Group3 11
Reserved Group3 12
Reserved Group3 13
Reserved Group3 14
Reserved Group3 15
Reserved Group3 16
Reserved Group3 17
Reserved Group3 18
Reserved Group3 19
Reserved Group3 20
Reserved Group3 21
Reserved Group3 22
Reserved Group3 23
Reserved Group3 24
Reserved Group3 25
Reserved Group3 26
Reserved Group3 27
Reserved Group3 28
Reserved Group3 29
Reserved Group3 30
Reserved Group3 31

6.19 Reset / Abort / Error Sources

Table 6-37 Reset/Abort/Error Sources

ERROR SOURCE SYSTEM MODE ERROR RESPONSE ESM HOOKUP
group.channel
CPU TRANSACTIONS
Precise write error (NCNB/Strongly Ordered) User/Privilege Precise Abort (CPU) n/a
Precise read error (NCB/Device or Normal) User/Privilege Precise Abort (CPU) n/a
Imprecise write error (NCB/Device or Normal) User/Privilege Imprecise Abort (CPU) n/a
Illegal instruction User/Privilege Undefined Instruction Trap (CPU)(1) n/a
MPU access violation User/Privilege Abort (CPU) n/a
SRAM
B0 TCM (even) ECC single error (correctable) User/Privilege ESM 1.26
B0 TCM (even) ECC double error (non-correctable) User/Privilege Abort (CPU), ESM => nERROR 3.3
B0 TCM (even) uncorrectable error (for example, redundant address decode) User/Privilege ESM => NMI => nERROR 2.6
B0 TCM (even) address bus parity error User/Privilege ESM => NMI => nERROR 2.10
B1 TCM (odd) ECC single error (correctable) User/Privilege ESM 1.28
B1 TCM (odd) ECC double error (non-correctable) User/Privilege Abort (CPU), ESM => nERROR 3.5
B1 TCM (odd) uncorrectable error (for example, redundant address decode) User/Privilege ESM => NMI => nERROR 2.8
B1 TCM (odd) address bus parity error User/Privilege ESM => NMI => nERROR 2.12
FLASH WITH CPU BASED ECC
FMC correctable error - Bus1 and Bus2 interfaces (does not include accesses to Bank 7) User/Privilege ESM 1.6
FMC uncorrectable error - Bus1 and Bus2 accesses
(does not include address parity error)
User/Privilege Abort (CPU), ESM => nERROR 3.7
FMC uncorrectable error - address parity error on Bus1 accesses User/Privilege ESM => NMI => nERROR 2.4
FMC correctable error - Accesses to Bank 7 User/Privilege ESM 1.35
FMC uncorrectable error - Accesses to Bank 7 User/Privilege ESM 1.36
DMA TRANSACTIONS
External imprecise error on read (Illegal transaction with ok response) User/Privilege ESM 1.5
External imprecise error on write (Illegal transaction with ok response) User/Privilege ESM 1.13
Memory access permission violation User/Privilege ESM 1.2
Memory parity error User/Privilege ESM 1.3
High-End Timer Transfer Unit 1 (HTU1)
NCNB (Strongly Ordered) transaction with slave error response User/Privilege Interrupt => VIM n/a
External imprecise error (Illegal transaction with ok response) User/Privilege Interrupt => VIM n/a
Memory access permission violation User/Privilege ESM 1.9
Memory parity error User/Privilege ESM 1.8
High-End Timer Transfer Unit 2 (HTU2)
NCNB (Strongly Ordered) transaction with slave error response User/Privilege Interrupt => VIM n/a
External imprecise error (Illegal transaction with ok response) User/Privilege Interrupt => VIM n/a
Memory access permission violation User/Privilege ESM 1.9
Memory parity error User/Privilege ESM 1.8
N2HET1
Memory parity error User/Privilege ESM 1.7
N2HET2
Memory parity error User/Privilege ESM 1.34
ETHERNET MASTER INTERFACE
Any error reported by slave being accessed User/Privilege ESM 1.43
MIBSPI
MibSPI1 memory parity error User/Privilege ESM 1.17
MibSPI3 memory parity error User/Privilege ESM 1.18
MibSPI5 memory parity error User/Privilege ESM 1.24
MIBADC
MibADC1 Memory parity error User/Privilege ESM 1.19
MibADC2 Memory parity error User/Privilege ESM 1.1
DCAN
DCAN1 memory parity error User/Privilege ESM 1.21
DCAN2 memory parity error User/Privilege ESM 1.23
DCAN3 memory parity error User/Privilege ESM 1.22
PLL
PLL slip error User/Privilege ESM 1.10
PLL #2 slip error User/Privilege ESM 1.42
CLOCK MONITOR
Clock monitor interrupt User/Privilege ESM 1.11
DCC
DCC1 error User/Privilege ESM 1.30
DCC2 error User/Privilege ESM 1.62
CCM-R4
Self test failure User/Privilege ESM 1.31
Compare failure User/Privilege ESM => NMI => nERROR 2.2
VIM
Memory parity error User/Privilege ESM 1.15
VOLTAGE MONITOR
VMON out of voltage range n/a Reset n/a
CPU SELFTEST (LBIST)
CPU Selftest (LBIST) error User/Privilege ESM 1.27
PIN MULTIPLEXING CONTROL
Mux configuration error User/Privilege ESM 1.37
POWER DOMAIN CONTROL
PSCON compare error User/Privilege ESM 1.38
PSCON self-test error User/Privilege ESM 1.39
eFuse CONTROLLER
eFuse Controller Autoload error User/Privilege ESM => nERROR 3.1
eFuse Controller - Any bit set in the error status register User/Privilege ESM 1.40
eFuse Controller self-test error User/Privilege ESM 1.41
WINDOWED WATCHDOG
WWD Non-Maskable Interrupt exception n/a ESM => NMI => nERROR 2.24
ERRORS REFLECTED IN THE SYSESR REGISTER
Power-Up Reset n/a Reset n/a
Oscillator fail / PLL slip(2) n/a Reset n/a
Watchdog exception n/a Reset n/a
CPU Reset (driven by the CPU STC) n/a Reset n/a
Software Reset n/a Reset n/a
External Reset n/a Reset n/a
(1) The Undefined Instruction TRAP is NOT detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage of the CPU.
(2) Oscillator fail/PLL slip can be configured in the system register (SYS.PLLCTL1) to generate a reset.

6.20 Digital Windowed Watchdog

This device includes a digital windowed watchdog (DWWD) module that protects against runaway code execution.

The DWWD module allows the application to configure the time window within which the DWWD module expects the application to service the watchdog. A watchdog violation occurs if the application services the watchdog outside of this window, or fails to service the watchdog at all. The application can choose to generate a system reset or an ESM group2 error signal in case of a watchdog violation.

The watchdog is disabled by default and must be enabled by the application. Once enabled, the watchdog can only be disabled upon a system reset.

6.21 Debug Subsystem

6.21.1 Block Diagram

The device contains an ICEPICK module to allow JTAG access to the scan chains.

RM46L440 RM46L840 debug_subsystem_spns185.gifFigure 6-21 Debug Subsystem Block Diagram

6.21.2 Debug Components Memory Map

Table 6-38 Debug Components Memory Map

MODULE NAME FRAME CHIP SELECT FRAME ADDRESS RANGE FRAME SIZE ACTUAL SIZE RESPNSE FOR ACCESS TO UNIMPLEMENTED LOCATIONS IN FRAME
START END
CoreSight Debug ROM CSCS0 0xFFA0_0000 0xFFA0_0FFF 4KB 4KB Reads return zeros, writes have no effect
Cortex-R4F Debug CSCS1 0xFFA0_1000 0xFFA0_1FFF 4KB 4KB Reads return zeros, writes have no effect

6.21.3 JTAG Identification Code

The JTAG ID code for this device is the same as the device ICEPick Identification Code.

Table 6-39 JTAG ID Code

Silicon Revision ID
Rev A 0x0B95502F
Rev B 0x2B95502F
Rev C 0x3B95502F

6.21.4 Debug ROM

The Debug ROM stores the location of the components on the Debug APB bus:

Table 6-40 Debug ROM table

ADDRESS DESCRIPTION VALUE
0x000 pointer to Cortex-R4F 0x0000 1003
0x001 Reserved 0x0000 2002
0x002 Reserved 0x0000 3002
0x003 POM 0x0000 4003
0x004 end of table 0x0000 0000

6.21.5 JTAG Scan Interface Timings

Table 6-41 JTAG Scan Interface Timing(1)

No. Parameter Min MAX Unit
fTCK TCK frequency (at HCLKmax) 12 MHz
fRTCK RTCK frequency (at TCKmax and HCLKmax) 10 MHz
1 td(TCK -RTCK) Delay time, TCK to RTCK 24 ns
2 tsu(TDI/TMS - RTCKr) Setup time, TDI, TMS before RTCK rise (RTCKr) 26 ns
3 th(RTCKr -TDI/TMS) Hold time, TDI, TMS after RTCKr 0 ns
4 th(RTCKr -TDO) Hold time, TDO after RTCKf 0 ns
5 td(TCKf -TDO) Delay time, TDO valid after RTCK fall (RTCKf) 12 ns
(1) Timings for TDO are specified for a maximum of 50pF load on TDO
RM46L440 RM46L840 jtag_timing_pns160.gifFigure 6-22 JTAG Timing

6.21.6 Advanced JTAG Security Module

This device includes a an Advanced JTAG Security Module (AJSM). which provides maximum security to the device’s memory content by allowing users to secure the device after programming.

RM46L440 RM46L840 ajsm_unlock_pns160.gifFigure 6-23 AJSM Unlock

The device is unsecure by default by virtue of a 128-bit visible unlock code programmed in the OTP address 0xF0000000.The OTP contents are XOR-ed with the "Unlock By Scan" register contents. The outputs of these XOR gates are again combined with a set of secret internal tie-offs. The output of this combinational logic is compared against a secret hard-wired 128-bit value. A match results in the UNLOCK signal being asserted, so that the device is now unsecure.

A user can secure the device by changing at least one bit in the visible unlock code from 1 to 0. Changing a 0 to 1 is not possible since the visible unlock code is stored in the One Time Programmable (OTP) flash region. Also, changing all the 128 bits to zeros is not a valid condition and will permanently secure the device.

Once secured, a user can unsecure the device by scanning an appropriate value into the "Unlock By Scan" register of the AJSM module. This register is accessible by configuring an IR value of 0b1011 on the AJSM TAP. The value to be scanned is such that the XOR of the OTP contents and the Unlock-By-Scan register contents results in the original visible unlock code.

The Unlock-By-Scan register is reset only upon asserting power-on reset (nPORRST).

A secure device only permits JTAG accesses to the AJSM scan chain through the Secondary Tap # 2 of the ICEPick module. All other secondary taps, test taps and the boundary scan interface are not accessible in this state.

6.21.7 Boundary Scan Chain

The device supports BSDL-compliant boundary scan for testing pin-to-pin compatibility. The boundary scan chain is connected to the Boundary Scan Interface of the ICEPICK module.

RM46L440 RM46L840 boundary_scan_implementation _pns160.gifFigure 6-24 Boundary Scan Implementation (Conceptual Diagram)

Data is serially shifted into all boundary-scan buffers through TDI, and out through TDO.