SPNS175C April   2012  – June 2015

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 PGE QFP Package Pinout (144-Pin)
    2. 4.2 ZWT BGA Package Ball-Map (337-Ball Grid Array)
    3. 4.3 Terminal Functions
      1. 4.3.1 PGE Package
        1. 4.3.1.1  Multibuffered Analog-to-Digital Converters (MibADCs)
        2. 4.3.1.2  Enhanced Next Generation High-End Timer (N2HET) Modules
        3. 4.3.1.3  General-Purpose Input/Output (GPIO)
        4. 4.3.1.4  Controller Area Network Controllers (DCANs)
        5. 4.3.1.5  Local Interconnect Network Interface Module (LIN)
        6. 4.3.1.6  Standard Serial Communication Interface (SCI)
        7. 4.3.1.7  Inter-Integrated Circuit Interface Module (I2C)
        8. 4.3.1.8  Standard Serial Peripheral Interface (SPI)
        9. 4.3.1.9  Multibuffered Serial Peripheral Interface Modules (MibSPI)
        10. 4.3.1.10 Ethernet Controller
        11. 4.3.1.11 System Module Interface
        12. 4.3.1.12 Clock Inputs and Outputs
        13. 4.3.1.13 Test and Debug Modules Interface
        14. 4.3.1.14 Flash Supply and Test Pads
        15. 4.3.1.15 Supply for Core Logic: 1.2-V Nominal
        16. 4.3.1.16 Supply for I/O Cells: 3.3-V Nominal
        17. 4.3.1.17 Ground Reference for All Supplies Except VCCAD
      2. 4.3.2 ZWT Package
        1. 4.3.2.1  Multibuffered Analog-to-Digital Converters (MibADCs)
        2. 4.3.2.2  Enhanced Next Generation High-End Timer (N2HET) Modules
        3. 4.3.2.3  General-Purpose Input/Output (GPIO)
        4. 4.3.2.4  Controller Area Network Controllers (DCANs)
        5. 4.3.2.5  Local Interconnect Network Interface Module (LIN)
        6. 4.3.2.6  Standard Serial Communication Interface (SCI)
        7. 4.3.2.7  Inter-Integrated Circuit Interface Module (I2C)
        8. 4.3.2.8  Standard Serial Peripheral Interface (SPI)
        9. 4.3.2.9  Multibuffered Serial Peripheral Interface Modules (MibSPI)
        10. 4.3.2.10 Ethernet Controller
        11. 4.3.2.11 External Memory Interface (EMIF)
        12. 4.3.2.12 Embedded Trace Macrocell for Cortex-R4F CPU (ETM-R4F)
        13. 4.3.2.13 RAM Trace Port (RTP)
        14. 4.3.2.14 Data Modification Module (DMM)
        15. 4.3.2.15 System Module Interface
        16. 4.3.2.16 Clock Inputs and Outputs
        17. 4.3.2.17 Test and Debug Modules Interface
        18. 4.3.2.18 Flash Supply and Test Pads
        19. 4.3.2.19 Reserved
        20. 4.3.2.20 No Connects
        21. 4.3.2.21 Supply for Core Logic: 1.2-V Nominal
        22. 4.3.2.22 Supply for I/O Cells: 3.3-V Nominal
        23. 4.3.2.23 Ground Reference for All Supplies Except VCCAD
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Switching Characteristics for Clock Domains
    6. 5.6  Wait States Required
    7. 5.7  Power Consumption
    8. 5.8  Input/Output Electrical Characteristics
    9. 5.9  Thermal Resistance Characteristics
    10. 5.10 Output Buffer Drive Strengths
    11. 5.11 Input Timings
    12. 5.12 Output Timings
    13. 5.13 Low-EMI Output Buffers
  6. 6System Information and Electrical Specifications
    1. 6.1  Device Power Domains
    2. 6.2  Voltage Monitor Characteristics
      1. 6.2.1 Important Considerations
      2. 6.2.2 Voltage Monitor Operation
      3. 6.2.3 Supply Filtering
    3. 6.3  Power Sequencing and Power On Reset
      1. 6.3.1 Power-Up Sequence
      2. 6.3.2 Power-Down Sequence
      3. 6.3.3 Power-On Reset: nPORRST
        1. 6.3.3.1 nPORRST Electrical and Timing Requirements
    4. 6.4  Warm Reset (nRST)
      1. 6.4.1 Causes of Warm Reset
      2. 6.4.2 nRST Timing Requirements
    5. 6.5  ARM Cortex-R4F CPU Information
      1. 6.5.1 Summary of ARM Cortex-R4F CPU Features
      2. 6.5.2 ARM Cortex-R4F CPU Features Enabled by Software
      3. 6.5.3 Dual Core Implementation
      4. 6.5.4 Duplicate Clock Tree After GCLK
      5. 6.5.5 ARM Cortex-R4F CPU Compare Module (CCM-R4) for Safety
      6. 6.5.6 CPU Self-Test
        1. 6.5.6.1 Application Sequence for CPU Self-Test
        2. 6.5.6.2 CPU Self-Test Clock Configuration
        3. 6.5.6.3 CPU Self-Test Coverage
    6. 6.6  Clocks
      1. 6.6.1 Clock Sources
        1. 6.6.1.1 Main Oscillator
          1. 6.6.1.1.1 Timing Requirements for Main Oscillator
        2. 6.6.1.2 Low-Power Oscillator (LPO)
          1. 6.6.1.2.1 Features
          2. 6.6.1.2.2 LPO Electrical and Timing Specifications
        3. 6.6.1.3 Phase Locked Loop (PLL) Clock Modules
          1. 6.6.1.3.1 Block Diagram
          2. 6.6.1.3.2 PLL Timing Specifications
        4. 6.6.1.4 External Clock Inputs
      2. 6.6.2 Clock Domains
        1. 6.6.2.1 Clock Domain Descriptions
        2. 6.6.2.2 Mapping of Clock Domains to Device Modules
      3. 6.6.3 Clock Test Mode
    7. 6.7  Clock Monitoring
      1. 6.7.1 Clock Monitor Timings
      2. 6.7.2 External Clock (ECLK) Output Functionality
      3. 6.7.3 Dual Clock Comparators
        1. 6.7.3.1 Features
        2. 6.7.3.2 Mapping of DCC Clock Source Inputs
    8. 6.8  Glitch Filters
    9. 6.9  Device Memory Map
      1. 6.9.1 Memory Map Diagram
      2. 6.9.2 Memory Map Table
      3. 6.9.3 Master/Slave Access Privileges
        1. 6.9.3.1 Special Notes on Accesses to Certain Slaves
      4. 6.9.4 POM Overlay Considerations
    10. 6.10 Flash Memory
      1. 6.10.1 Flash Memory Configuration
      2. 6.10.2 Main Features of Flash Module
      3. 6.10.3 ECC Protection for Flash Accesses
      4. 6.10.4 Flash Access Speeds
      5. 6.10.5 Flash Program and Erase Timings for Program Flash
      6. 6.10.6 Flash Program and Erase Timings for Data Flash
    11. 6.11 Tightly Coupled RAM (TCRAM) Interface Module
      1. 6.11.1 Features
      2. 6.11.2 TCRAM Interface ECC Support
    12. 6.12 Parity Protection for Peripheral RAMs
    13. 6.13 On-Chip SRAM Initialization and Testing
      1. 6.13.1 On-Chip SRAM Self-Test Using PBIST
        1. 6.13.1.1 Features
        2. 6.13.1.2 PBIST RAM Groups
      2. 6.13.2 On-Chip SRAM Auto Initialization
    14. 6.14 External Memory Interface (EMIF)
      1. 6.14.1 Features
      2. 6.14.2 Electrical and Timing Specifications
        1. 6.14.2.1 Asynchronous RAM
        2. 6.14.2.2 Synchronous Timing
    15. 6.15 Vectored Interrupt Manager
      1. 6.15.1 VIM Features
      2. 6.15.2 Interrupt Request Assignments
    16. 6.16 DMA Controller
      1. 6.16.1 DMA Features
      2. 6.16.2 Default DMA Request Map
    17. 6.17 Real Time Interrupt Module
      1. 6.17.1 Features
      2. 6.17.2 Block Diagrams
      3. 6.17.3 Clock Source Options
      4. 6.17.4 Network Time Synchronization Inputs
    18. 6.18 Error Signaling Module
      1. 6.18.1 Features
      2. 6.18.2 ESM Channel Assignments
    19. 6.19 Reset / Abort / Error Sources
    20. 6.20 Digital Windowed Watchdog
    21. 6.21 Debug Subsystem
      1. 6.21.1  Block Diagram
      2. 6.21.2  Debug Components Memory Map
      3. 6.21.3  JTAG Identification Code
      4. 6.21.4  Debug ROM
      5. 6.21.5  JTAG Scan Interface Timings
      6. 6.21.6  Advanced JTAG Security Module
      7. 6.21.7  Embedded Trace Macrocell (ETM-R4)
        1. 6.21.7.1 ETM TRACECLKIN Selection
        2. 6.21.7.2 Timing Specifications
      8. 6.21.8  RAM Trace Port (RTP)
        1. 6.21.8.1 Features
        2. 6.21.8.2 Timing Specifications
      9. 6.21.9  Data Modification Module (DMM)
        1. 6.21.9.1 Features
        2. 6.21.9.2 Timing Specifications
      10. 6.21.10 Boundary Scan Chain
  7. 7Peripheral Information and Electrical Specifications
    1. 7.1  Peripheral Legend
    2. 7.2  Multibuffered 12-Bit Analog-to-Digital Converter
      1. 7.2.1 Features
      2. 7.2.2 Event Trigger Options
        1. 7.2.2.1 Default MIBADC1 Event Trigger Hookup
        2. 7.2.2.2 Alternate MIBADC1 Event Trigger Hookup
        3. 7.2.2.3 Default MIBADC2 Event Trigger Hookup
        4. 7.2.2.4 Alternate MIBADC2 Event Trigger Hookup
      3. 7.2.3 ADC Electrical and Timing Specifications
      4. 7.2.4 Performance (Accuracy) Specifications
        1. 7.2.4.1 MibADC Nonlinearity Errors
        2. 7.2.4.2 MibADC Total Error
    3. 7.3  General-Purpose Input/Output
      1. 7.3.1 Features
    4. 7.4  Enhanced Next Generation High-End Timer (N2HET)
      1. 7.4.1 Features
      2. 7.4.2 N2HET RAM Organization
      3. 7.4.3 Input Timing Specifications
      4. 7.4.4 N2HET1-N2HET2 Interconnections
      5. 7.4.5 N2HET Checking
        1. 7.4.5.1 Internal Monitoring
        2. 7.4.5.2 Output Monitoring Using Dual Clock Comparator (DCC)
      6. 7.4.6 Disabling N2HET Outputs
      7. 7.4.7 High-End Timer Transfer Unit (HTU)
        1. 7.4.7.1 Features
        2. 7.4.7.2 Trigger Connections
    5. 7.5  Controller Area Network (DCAN)
      1. 7.5.1 Features
      2. 7.5.2 Electrical and Timing Specifications
    6. 7.6  Local Interconnect Network Interface (LIN)
      1. 7.6.1 LIN Features
    7. 7.7  Serial Communication Interface (SCI)
      1. 7.7.1 Features
    8. 7.8  Inter-Integrated Circuit (I2C)
      1. 7.8.1 Features
      2. 7.8.2 I2C I/O Timing Specifications
    9. 7.9  Multibuffered / Standard Serial Peripheral Interface
      1. 7.9.1 Features
      2. 7.9.2 MibSPI Transmit and Receive RAM Organization
      3. 7.9.3 MibSPI Transmit Trigger Events
        1. 7.9.3.1 MIBSPI1 Event Trigger Hookup
        2. 7.9.3.2 MIBSPI3 Event Trigger Hookup
        3. 7.9.3.3 MIBSPI5 Event Trigger Hookup
      4. 7.9.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.9.5 SPI Slave Mode I/O Timings
    10. 7.10 Ethernet Media Access Controller
      1. 7.10.1 Ethernet MII Electrical and Timing Specifications
      2. 7.10.2 Ethernet RMII Electrical and Timing Specifications
      3. 7.10.3 Management Data Input/Output (MDIO) Electrical and Timing Specifications
  8. 8Device and Documentation Support
    1. 8.1  Device Support
      1. 8.1.1 Development Support
      2. 8.1.2 Device Nomenclature
    2. 8.2  Documentation Support
      1. 8.2.1 Related Documentation from Texas Instruments
    3. 8.3  Related Links
    4. 8.4  Community Resources
    5. 8.5  Trademarks
    6. 8.6  Electrostatic Discharge Caution
    7. 8.7  Glossary
    8. 8.8  Device Identification Code Register
    9. 8.9  Die Identification Registers
    10. 8.10 Module Certifications
      1. 8.10.1 DCAN Certification
      2. 8.10.2 LIN Certification
        1. 8.10.2.1 LIN Master Mode
        2. 8.10.2.2 LIN Slave Mode - Fixed Baud Rate
        3. 8.10.2.3 LIN Slave Mode - Adaptive Baud Rate
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Packaging Information

6 System Information and Electrical Specifications

6.1 Device Power Domains

The device core logic is split up into multiple power domains in order to optimize the power for a given application use case. There are eight core power domains in total: PD1, PD2, PD3, PD4, PD5, RAM_PD1, RAM_PD2, and RAM_PD3.

The actual contents of these power domains are indicated in Section 1.4.

PD1 is an "always-ON" power domain, which cannot be turned off. Each of the other core power domains can be turned ON/OFF one time during device initialization as per the application requirement. Refer to the Power Management Module (PMM) chapter of RM48x Technical Reference Manual (SPNU503) for more details.

NOTE

The clocks to a module must be turned off before powering down the core domain that contains the module.

NOTE

The logic in the modules that are powered down lose power completely. Any access to modules that are powered down results in an abort being generated. When power is restored, the modules power up to their default states (after normal power up). No register or memory contents are preserved in the core domains that are turned off.

6.2 Voltage Monitor Characteristics

A voltage monitor is implemented on this device. The purpose of this voltage monitor is to eliminate the requirement for a specific sequence when powering up the core and I/O voltage supplies.

6.2.1 Important Considerations

  • The voltage monitor does not eliminate the need of a voltage supervisor circuit to guarantee that the device is held in reset when the voltage supplies are out of range.
  • The voltage monitor only monitors the core supply (VCC) and the I/O supply (VCCIO). The other supplies are not monitored by the VMON. For example, if the VCCAD or VCCP are supplied from a source different from that for VCCIO, then there is no internal voltage monitor for the VCCAD and VCCP supplies.

6.2.2 Voltage Monitor Operation

The voltage monitor generates the Power Good MCU signal (PGMCU) as well as the I/Os Power Good IO signal (PGIO) on the device. During power-up or power-down processes, the PGMCU and PGIO are driven low when the core or I/O supplies are lower than the specified minimum monitoring thresholds. The PGIO and PGMCU being low isolates the core logic as well as the I/O controls during power up or power down of the supplies. This allows the core and I/O supplies to be powered up or down in any order.

When the voltage monitor detects a low voltage on the I/O supply, it will assert a power-on reset. When the voltage monitor detects an out-of-range voltage on the core supply, it asynchronously makes all output pins high impedance, and asserts a power-on reset. The voltage monitor is disabled when the device enters a low-power mode.

The VMON also incorporates a glitch filter for the nPORRST input. Refer to Section 6.3.3.1 for the timing information on this glitch filter.

Table 6-1 Voltage Monitoring Specifications

PARAMETER MIN TYP MAX UNIT
VMON Voltage monitoring
thresholds
VCC low - VCC level below this threshold is detected as too low. 0.75 0.9 1.13 V
VCC high - VCC level above this threshold is detected as too high. 1.40 1.7 2.1
VCCIO low - VCCIO level below this threshold is detected as too low. 1.85 2.4 2.9

6.2.3 Supply Filtering

The VMON has the capability to filter glitches on the VCC and VCCIO supplies.

Table 6-2 shows the characteristics of the supply filtering. Glitches in the supply larger than the maximum specification cannot be filtered.

Table 6-2 VMON Supply Glitch Filtering Capability

PARAMETER MIN MAX UNIT
Width of glitch on VCC that can be filtered 250 1000 ns
Width of glitch on VCCIO that can be filtered 250 1000 ns

6.3 Power Sequencing and Power On Reset

6.3.1 Power-Up Sequence

There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The power-up sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (see Table 6-4 for more details), core voltage rising above the minimum core supply threshold and the release of power-on reset. The high-frequency oscillator will start up first and its amplitude will grow to an acceptable level. The oscillator start up time is dependent on the type of oscillator and is provided by the oscillator vendor. The different supplies to the device can be powered up in any order.

The device goes through the following sequential phases during power up.

Table 6-3 Power-Up Phases

Oscillator start-up and validity check 1032 oscillator cycles
eFuse autoload 1180 oscillator cycles
Flash pump power up 688 oscillator cycles
Flash bank power up 617 oscillator cycles
Total 3517 oscillator cycles

The CPU reset is released at the end of the sequence in Table 6-3 and fetches the first instruction from address 0x00000000.

6.3.2 Power-Down Sequence

The different supplies to the device can be powered down in any order.

6.3.3 Power-On Reset: nPORRST

This is the power-on reset. This reset must be asserted by an external circuitry whenever the I/O or core supplies are outside the specified recommended range. This signal has a glitch filter on it. It also has an internal pulldown.

6.3.3.1 nPORRST Electrical and Timing Requirements

Table 6-4 Electrical Requirements for nPORRST

NO. PARAMETER MIN MAX UNIT
VCCPORL VCC low supply level when nPORRST must be active during power up 0.5 V
VCCPORH VCC high supply level when nPORRST must remain active during power up and become active during power down 1.14 V
VCCIOPORL VCCIO / VCCP low supply level when nPORRST must be active during power up 1.1 V
VCCIOPORH VCCIO / VCCP high supply level when nPORRST must remain active during power up and become active during power down 3.0 V
VIL(PORRST) Low-level input voltage of nPORRST VCCIO > 2.5V 0.2 * VCCIO V
Low-level input voltage of nPORRST VCCIO < 2.5V 0.5 V
3 tsu(PORRST) Setup time, nPORRST active before VCCIO and VCCP > VCCIOPORL during power up 0 ms
6 th(PORRST) Hold time, nPORRST active after VCC > VCCPORH 1 ms
7 tsu(PORRST) Setup time, nPORRST active before VCC < VCCPORH during power down 2 µs
8 th(PORRST) Hold time, nPORRST active after VCCIO and VCCP > VCCIOPORH 1 ms
9 th(PORRST) Hold time, nPORRST active after VCC < VCCPORL 0 ms
tf(nPORRST)

Filter time nPORRST pin;

pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset.

500 2000 ns
RM48L940 RM48L740 RM48L540 nporrst_timing_pns160.gifFigure 6-1 nPORRST Timing Diagram

6.4 Warm Reset (nRST)

This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the output buffer is implemented as an open drain (drives low only). To ensure an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.

This terminal has a glitch filter. It also has an internal pullup

6.4.1 Causes of Warm Reset

Table 6-5 Causes of Warm Reset

DEVICE EVENT SYSTEM STATUS FLAG
Power-Up Reset Exception Status Register, bit 15
Oscillator fail Global Status Register, bit 0
PLL slip Global Status Register, bits 8 and 9
Watchdog exception / Debugger reset Exception Status Register, bit 13
CPU Reset (driven by the CPU STC) Exception Status Register, bit 5
Software Reset Exception Status Register, bit 4
External Reset Exception Status Register, bit 3

6.4.2 nRST Timing Requirements

Table 6-6 nRST Timing Requirements

MIN MAX UNIT
tv(RST) Valid time, nRST active after nPORRST inactive 2256tc(OSC)(1) ns
Valid time, nRST active (all other System reset conditions) 32tc(VCLK)
tf(nRST) Filter time nRST pin; pulses less than MIN will be filtered out; pulses greater than MAX will generate a reset. See Section 6.8. 475 2000 ns
(1) Assumes the oscillator has started up and stabilized before nPORRST is released .

6.5 ARM Cortex-R4F CPU Information

6.5.1 Summary of ARM Cortex-R4F CPU Features

The features of the ARM Cortex-R4F CPU include:

  • An integer unit with integral EmbeddedICE-RT logic.
  • High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI) for Level two (L2) master and slave interfaces.
  • Floating Point Coprocessor
  • Dynamic branch prediction with a global history buffer, and a 4-entry return stack
  • Low interrupt latency.
  • Nonmaskable interrupt.
  • A Harvard Level one (L1) memory system with:
    • Tightly Coupled Memory (TCM) interfaces with support for error correction or parity checking memories
    • ARMv7-R architecture Memory Protection Unit (MPU) with 12 regions
  • Dual core logic for fault detection in safety-critical applications.
  • An L2 memory interface:
    • Single 64-bit master AXI interface
    • 64-bit slave AXI interface to TCM RAM blocks
  • A debug interface to a CoreSight Debug Access Port (DAP).
  • Six Hardware Breakpoints
  • Two Watchpoints
  • A trace interface to a CoreSight ETM-R4.
  • A Performance Monitoring Unit (PMU).
  • A Vectored Interrupt Controller (VIC) port.

For more information on the ARM Cortex-R4F CPU see www.arm.com.

6.5.2 ARM Cortex-R4F CPU Features Enabled by Software

The following CPU features are disabled on reset and must be enabled by the application if required.

  • ECC On TCM Accesses
  • Hardware VIC Port
  • Floating Point Coprocessor
  • MPU

6.5.3 Dual Core Implementation

The device has two Cortex-R4F cores, where the output signals of both CPUs are compared in the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by two clock cycles as shown in Figure 6-3.

The CPUs have a diverse CPU placement given by following requirements:

  • different orientation; for example, CPU1 = "north" orientation, CPU2 = "flip west" orientation
  • dedicated guard ring for each CPU
RM48L940 RM48L740 RM48L540 dual_cpu_orient.gifFigure 6-2 Dual-CPU Orientation

6.5.4 Duplicate Clock Tree After GCLK

The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the second CPU running at the same frequency and in phase to the clock of CPU1. See Figure 6-3.

6.5.5 ARM Cortex-R4F CPU Compare Module (CCM-R4) for Safety

This device has two ARM Cortex-R4F CPU cores, where the output signals of both CPUs are compared in the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed in a different way as shown in Figure 6-3.

RM48L940 RM48L740 RM48L540 dual_core_implementation_pns160.gifFigure 6-3 Dual Core Implementation

To avoid an erroneous CCM-R4 compare error, the application software must initialize the registers of both CPUs before the registers are used, including function calls where the register values are pushed onto the stack.

6.5.6 CPU Self-Test

The CPU STC (Self-Test Controller) is used to test the two Cortex-R4F CPU Cores using the Deterministic Logic BIST Controller as the test engine.

The main features of the self-test controller are:

  • Ability to divide the complete test run into independent test intervals
  • Capable of running the complete test as well as running few intervals at a time
  • Ability to continue from the last executed interval (test set) as well as ability to restart from the beginning (First test set)
  • Complete isolation of the self-tested CPU core from rest of the system during the self-test run
  • Ability to capture the Failure interval number
  • Time-out counter for the CPU self-test run as a fail-safe feature

6.5.6.1 Application Sequence for CPU Self-Test

  1. Configure clock domain frequencies.
  2. Select number of test intervals to be run.
  3. Configure the time-out period for the self-test run.
  4. Enable self-test.
  5. Wait for CPU reset.
  6. In the reset handler, read CPU self-test status to identify any failures.
  7. Retrieve CPU state if required.

For more information see the device specific technical reference manual.

6.5.6.2 CPU Self-Test Clock Configuration

The maximum clock rate for the self-test is 100 MHz. The STCCLK is divided down from the CPU clock. This divider is configured by the STCCLKDIV register at address 0xFFFFE108.

For more information see the device specific technical reference manual.

6.5.6.3 CPU Self-Test Coverage

Table 6-7 shows CPU test coverage achieved for each self-test interval. It also lists the cumulative test cycles. The test time can be calculated by multiplying the number of test cycles with the STC clock period.

Table 6-7 CPU Self-Test Coverage

INTERVALS TEST COVERAGE, % TEST CYCLES
0 0 0
1 62.13 1365
2 70.09 2730
3 74.49 4095
4 77.28 5460
5 79.28 6825
6 80.90 8190
7 82.02 9555
8 83.10 10920
9 84.08 12285
10 84.87 13650
11 85.59 15015
12 86.11 16380
13 86.67 17745
14 87.16 19110
15 87.61 20475
16 87.98 21840
17 88.38 23205
18 88.69 24570
19 88.98 25935
20 89.28 27300
21 89.50 28665
22 89.76 30030
23 90.01 31395
24 90.21 32760

6.6 Clocks

6.6.1 Clock Sources

Table 6-8 lists the available clock sources on the device. Each of the clock sources can be enabled or disabled using the CSDISx registers in the system module. The clock source number in the table corresponds to the control bit in the CSDISx register for that clock source.

Table 6-8 also shows the default state of each clock source.

Table 6-8 Available Clock Sources

CLOCK
SOURCE
NO.
NAME DESCRIPTION DEFAULT
STATE
0 OSCIN Main Oscillator Enabled
1 PLL1 Output From PLL1 Disabled
2 Reserved Reserved Disabled
3 EXTCLKIN1 External Clock Input #1 Disabled
4 CLK80K Low-Frequency Output of Internal Reference Oscillator Enabled
5 CLK10M High-Frequency Output of Internal Reference Oscillator Enabled
6 PLL2 Output From PLL2 Disabled
7 EXTCLKIN2 External Clock Input #2 Disabled

6.6.1.1 Main Oscillator

The oscillator is enabled by connecting the appropriate fundamental resonator/crystal and load capacitors across the external OSCIN and OSCOUT pins as shown in Figure 6-4. The oscillator is a single stage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and low power modes.

TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature/voltage extremes.

An external oscillator source can be used by connecting a 3.3-V clock signal to the OSCIN pin and leaving the OSCOUT pin unconnected (open) as shown in Figure 6-4.

RM48L940 RM48L740 RM48L540 clock_connection_pns160.gifFigure 6-4 Recommended Crystal/Clock Connection

6.6.1.1.1 Timing Requirements for Main Oscillator

Table 6-9 Timing Requirements for Main Oscillator

MIN MAX UNIT
tc(OSC) Cycle time, OSCIN (when using a sine-wave input) 50 200 ns
tc(OSC_SQR) Cycle time, OSCIN, (when input to the OSCIN is a square wave ) 50 200 ns
tw(OSCIL) Pulse duration, OSCIN low (when input to the OSCIN is a square wave) 6 ns
tw(OSCIH) Pulse duration, OSCIN high (when input to the OSCIN is a square wave) 6 ns

6.6.1.2 Low-Power Oscillator (LPO)

The LPO is comprised of two oscillators — HF LPO and LF LPO, in a single macro.

6.6.1.2.1 Features

The main features of the LPO are:

  • Supplies a clock at extremely low power for power-saving modes. This is connected as clock source # 4 of the GCM.
  • Supplies a high-frequency clock for nontiming-critical systems. This is connected as clock source # 5 of the GCM.
  • Provides a comparison clock for the crystal oscillator failure detection circuit.

RM48L940 RM48L740 RM48L540 LPO_Block_Diagram_pns160.gifFigure 6-5 LPO Block Diagram

Figure 6-5 shows a block diagram of the internal reference oscillator. This is an LPO and provides two clock sources: one nominally 80 kHz and one nominally 10 MHz.

6.6.1.2.2 LPO Electrical and Timing Specifications

Table 6-10 LPO Specifications

PARAMETER MIN TYP MAX UNIT
Clock Detection Oscillator fail frequency - lower threshold, using untrimmed LPO output 1.375 2.4 4.875 MHz
Oscillator fail frequency - higher threshold, using untrimmed LPO output 22 38.4 78
LPO - HF oscillator (fHFLPO) Untrimmed frequency 5.5 9 19.5
Trimmed frequency 8 9.6 11 MHz
Start-up time from STANDBY (LPO BIAS_EN High for at least 900 µs) 10 µs
Cold start-up time 900 µs
LPO - LF oscillator (fLFLPO) Untrimmed frequency 36 85 180 kHz
Start-up time from STANDBY (LPO BIAS_EN High for at least 900 µs) 100 µs
Cold start-up time 2000 µs

6.6.1.3 Phase Locked Loop (PLL) Clock Modules

The PLL is used to multiply the input frequency to some higher frequency.

The main features of the PLL are:

  • Frequency modulation can be optionally superimposed on the synthesized frequency of PLL1. The frequency modulation capability of PLL2 is permanently disabled.
  • Configurable frequency multipliers and dividers.
  • Built-in PLL Slip monitoring circuit.
  • Option to reset the device on a PLL slip detection.

6.6.1.3.1 Block Diagram

Figure 6-6 shows a high-level block diagram of the two PLL macros on this microcontroller. PLLCTL1 and PLLCTL2 are used to configure the multiplier and dividers for the PLL1. PLLCTL3 is used to configure the multiplier and dividers for PLL2.

RM48L940 RM48L740 RM48L540 FMzPLLx_block_diagram_pns160.gifFigure 6-6 ZWT PLLx Block Diagram

6.6.1.3.2 PLL Timing Specifications

Table 6-11 PLL Timing Specifications

PARAMETER MIN MAX UNIT
fINTCLK PLL1 Reference Clock frequency 1 20 MHz
fpost_ODCLK Post-ODCLK – PLL1 Post-divider input clock frequency 400 MHz
fVCOCLK VCOCLK – PLL1 Output Divider (OD) input clock frequency 150 550 MHz
fINTCLK2 PLL2 Reference Clock frequency 1 20 MHz
fpost_ODCLK2 Post-ODCLK – PLL2 Post-divider input clock frequency 400 MHz
fVCOCLK2 VCOCLK – PLL2 Output Divider (OD) input clock frequency 150 550 MHz

6.6.1.4 External Clock Inputs

The device supports up to two external clock inputs. This clock input must be a square wave input. The electrical and timing requirements for these clock inputs are specified in Table 6-12. The external clock sources are not checked for validity. They are assumed valid when enabled.

Table 6-12 External Clock Timing and Electrical Specifications

PARAMETER DESCRIPTION MIN MAX UNIT
fEXTCLKx External clock input frequency 80 MHz
tw(EXTCLKIN)H EXTCLK high-pulse duration 6 ns
tw(EXTCLKIN)L EXTCLK low-pulse duration 6 ns
viL(EXTCLKIN) Low-level input voltage -0.3 0.8 V
viH(EXTCLKIN) High-level input voltage 2 VCCIO + 0.3 V

6.6.2 Clock Domains

6.6.2.1 Clock Domain Descriptions

Table 6-13 lists the device clock domains and their default clock sources. The table also shows the system module control register that is used to select an available clock source for each clock domain.

Table 6-13 Clock Domain Descriptions

CLOCK DOMAIN
NAME
DEFAULT CLOCK
SOURCE
CLOCK SOURCE
SELECTION REGISTER
DESCRIPTION
HCLK OSCIN GHVSRC
  • Is disabled via the CDDISx registers bit 1
  • Used for all system modules including DMA, ESM
GCLK OSCIN GHVSRC
  • Always the same frequency as HCLK
  • In phase with HCLK
  • Is disabled separately from HCLK through the CDDISx registers bit 0
  • Can be divided by 1 up to 8 when running CPU self-test (LBIST) using the CLKDIV field of the STCCLKDIV register at address 0xFFFFE108
GCLK2 OSCIN GHVSRC
  • Always the same frequency as GCLK
  • 2 cycles delayed from GCLK
  • Is disabled along with GCLK
  • Gets divided by the same divider setting as that for GCLK when running CPU self-test (LBIST)
VCLK OSCIN GHVSRC
  • Divided down from HCLK
  • Can be HCLK/1, HCLK/2, ... or HCLK/16
  • Is disabled separately from HCLK through the CDDISx registers bit 2
VCLK2 OSCIN GHVSRC
  • Divided down from HCLK
  • Can be HCLK/1, HCLK/2, ... or HCLK/16
  • Frequency must be an integer multiple of VCLK frequency
  • Is disabled separately from HCLK through the CDDISx registers bit 3
VCLK3 OSCIN GHVSRC
  • Divided down from HCLK
  • Can be HCLK/1, HCLK/2, ... or HCLK/16
  • Is disabled separately from HCLK through the CDDISx registers bit 8
VCLKA1 VCLK VCLKASRC
  • Defaults to VCLK as the source
  • Is disabled via the CDDISx registers bit 4
VCLKA3 VCLK VCLKACON1
  • Defaults to VCLK as the source
  • Frequency can be as fast as HCLK frequency.
  • Is disabled through the CDDISx registers bit 10
VCLKA3_DIVR VCLK VCLKACON1
  • Divided down from the VCLKA3 using the VCLKA3R field of the VCLKACON1 register at address 0xFFFFE140
  • Frequency can be VCLKA3/1, VCLKA3/2, ..., or VCLKA3/8
  • Default frequency is VCLKA3/2
  • Is disabled separately through the VCLKACON1 register VCLKA3_DIV_CDDIS bit only if the VCLKA3 clock is not disabled
VCLKA4 VCLK VCLKACON1
  • Defaults to VCLK as the source
  • Is disabled through the CDDISx registers bit 11
RTICLK VCLK RCLKSRC
  • Defaults to VCLK as the source
  • If a clock source other than VCLK is selected for RTICLK, then the RTICLK frequency must be less than or equal to VCLK/3
    • Application can ensure this by programming the RTI1DIV field of the RCLKSRC register, if necessary
  • Is disabled through the CDDISx registers bit 6

6.6.2.2 Mapping of Clock Domains to Device Modules

Each clock domain has a dedicated functionality as shown in Figure 6-7.

RM48L940 RM48L740 RM48L540 dev_clock_domains_f8_pns160.gifFigure 6-7 Device Clock Domains

6.6.3 Clock Test Mode

The RM4x platform architecture defines a special mode that allows various clock signals to be brought out on to the ECLK pin and N2HET1[12] device outputs. This mode is called the Clock Test mode. It is very useful for debugging purposes and can be configured through the CLKTEST register in the system module.

Table 6-14 Clock Test Mode Options

SEL_ECP_PIN
=
CLKTEST[3-0]
SIGNAL ON ECLK SEL_GIO_PIN
=
CLKTEST[11-8]
SIGNAL ON N2HET1[12]
0000 Oscillator 0000 Oscillator Valid Status
0001 Main PLL free-running clock output 0001 Main PLL Valid status
0010 Reserved 0010 Reserved
0011 EXTCLKIN1 0011 Reserved
0100 CLK80K 0100 Reserved
0101 CLK10M 0101 CLK10M Valid status
0110 Secondary PLL free-running clock output 0110 Secondary PLL Valid Status
0111 EXTCLKIN2 0111 Reserved
1000 GCLK 1000 CLK80K
1001 RTI Base 1001 Reserved
1010 Reserved 1010 Reserved
1011 VCLKA1 1011 Reserved
1100 Reserved 1100 Reserved
1101 VCLKA3 1101 Reserved
1110 VCLKA4 1110 Reserved
1111 Reserved 1111 Reserved

6.7 Clock Monitoring

The LPO Clock Detect (LPOCLKDET) module consists of a clock monitor (CLKDET) and an internal LPO.

The LPO provides two different clock sources – a low frequency (LFLPO) and a high frequency (HFLPO).

The CLKDET is a supervisor circuit for an externally supplied clock signal (OSCIN). In case the OSCIN frequency falls out of a frequency window, the CLKDET flags this condition in the global status register (GLBSTAT bit 0: OSC FAIL) and switches all clock domains sourced by OSCIN to the HFLPO clock (limp mode clock).

The valid OSCIN frequency range is defined as: fHFLPO / 4 < fOSCIN < fHFLPO * 4.

6.7.1 Clock Monitor Timings

For more information on LPO and Clock detection, refer to Table 6-10.

RM48L940 RM48L740 RM48L540 LPO_Clk_Detection_pns160.gifFigure 6-8 LPO and Clock Detection, Untrimmed HFLPO

6.7.2 External Clock (ECLK) Output Functionality

The ECLK pin can be configured to output a prescaled clock signal indicative of an internal device clock. This output can be externally monitored as a safety diagnostic.

6.7.3 Dual Clock Comparators

The Dual Clock Comparator (DCC) module determines the accuracy of selectable clock sources by counting the pulses of two independent clock sources (counter 0 and counter 1). If one clock is out of spec, an error signal is generated. For example, the DCC1 can be configured to use CLK10M as the reference clock (for counter 0) and VCLK as the "clock under test" (for counter 1). This configuration allows the DCC1 to monitor the PLL output clock when VCLK is using the PLL output as its source.

An additional use of this module is to measure the frequency of a selectable clock source, using the input clock as a reference, by counting the pulses of two independent clock sources. Counter 0 generates a fixed-width counting window after a preprogrammed number of pulses. Counter 1 generates a fixed-width pulse (1 cycle) after a preprogrammed number of pulses. This pulse sets as an error signal if counter 1 does not reach 0 within the counting window generated by counter 0.

6.7.3.1 Features

  • Takes two different clock sources as input to two independent counter blocks.
  • One of the clock sources is the known-good, or reference clock; the second clock source is the "clock under test."
  • Each counter block is programmable with initial, or seed values.
  • The counter blocks start counting down from their seed values at the same time; a mismatch from the expected frequency for the clock under test generates an error signal which is used to interrupt the CPU.

6.7.3.2 Mapping of DCC Clock Source Inputs

Table 6-15 DCC1 Counter 0 Clock Sources

CLOCK SOURCE [3:0] CLOCK NAME
Others Oscillator (OSCIN)
0x5 High-frequency LPO
0xA Test clock (TCK)

Table 6-16 DCC1 Counter 1 Clock Sources

KEY [3:0] CLOCK SOURCE [3:0] CLOCK NAME
Others - N2HET1[31]
0x0 Main PLL free-running clock output
0x1 reserved
0x2 Low-frequency LPO
0xA 0x3 High-frequency LPO
0x4 Flash HD pump oscillator
0x5 EXTCLKIN1
0x6 EXTCLKIN2
0x7 Ring oscillator
0x8 - 0xF VCLK

Table 6-17 DCC2 Counter 0 Clock Sources

CLOCK SOURCE [3:0] CLOCK NAME
Others Oscillator (OSCIN)
0xA Test clock (TCK)

Table 6-18 DCC2 Counter 1 Clock Sources

KEY [3:0] CLOCK SOURCE [3:0] CLOCK NAME
Others - N2HET2[0]
0xA 00x0 - 0x7 Reserved
0x8 - 0xF VCLK

6.8 Glitch Filters

A glitch filter is present on the following signals.

Table 6-19 Glitch Filter Timing Specifications

PIN PARAMETER MIN MAX UNIT
nPORRST tf(nPORRST)

Filter time nPORRST pin;

pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset(1)

475 2000 ns
nRST tf(nRST)

Filter time nRST pin;

pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset

475 2000 ns
TEST tf(TEST)

Filter time TEST pin;

pulses less than MIN will be filtered out, pulses greater than MAX will pass through

475 2000 ns
(1) The glitch filter design on the nPORRST signal is designed such that no size pulse will reset any part of the microcontroller (flash pump, I/O pins, and so forth) without also generating a valid reset signal to the CPU.

6.9 Device Memory Map

6.9.1 Memory Map Diagram

The figures below show the device memory maps.

RM48L940 RM48L740 RM48L540 memory_map_pns160.gifFigure 6-9 RM48L940 Memory Map
RM48L940 RM48L740 RM48L540 memory_map_2MB_256KB_pns164.gifFigure 6-10 RM48L740 Memory Map
RM48L940 RM48L740 RM48L540 memory_map_2MB_192KB_pns164.gifFigure 6-11 RM48L540 Memory Map

The Flash memory is mirrored to support ECC logic testing. The base address of the mirrored Flash image is 0x20000000.

6.9.2 Memory Map Table

Table 6-20 Device Memory Map

MODULE NAME FRAME CHIP SELECT FRAME ADDRESS RANGE FRAME SIZE ACTUAL SIZE RESPONSE FOR ACCESS TO UNIMPLEMENTED LOCATIONS IN FRAME
START END
MEMORIES TIGHTLY COUPLED TO THE ARM CORTEX-R4F CPU
TCM Flash CS0 0x00000000 0x00FFFFFF 16MB 3MB(2) Abort
TCM RAM + RAM ECC CSRAM0 0x08000000 0x0BFFFFFF 64MB 256KB(1)
Mirrored Flash Flash mirror frame 0x20000000 0x20FFFFFF 16MB 3MB(2)
EXTERNAL MEMORY ACCESSES
EMIF Chip Select 2 (asynchronous) EMIF select 2 0x60000000 0x63FFFFFF 64MB 16MB Access to "Reserved" space will generate Abort
EMIF Chip Select 3 (asynchronous) EMIF select 3 0x64000000 0x67FFFFFF 64MB 16MB
EMIF Chip Select 4 (asynchronous) EMIF select 4 0x68000000 0x6BFFFFFF 64MB 16MB
EMIF Chip Select 0 (synchronous) EMIF select 0 0x80000000 0x87FFFFFF 128MB 128MB
FLASH MODULE BUS2 INTERFACE
Customer OTP, TCM Flash Bank 0 0xF0000000 0xF0001FFF 8KB 4KB Abort
Customer OTP, TCM Flash Bank 1 0xF0002000 0xF0003FFF 8KB 4KB
Customer OTP, EEPROM Bank 7 0xF000E000 0xF000FFFF 8KB 2KB
Customer OTP–ECC, TCM Flash Bank 0 0xF0040000 0xF00403FF 1KB 512B
Customer OTP–ECC, TCM Flash Bank 1 0xF0040400 0xF00407FF 1KB 512B
Customer OTP–ECC, EEPROM Bank 7 0xF0041C00 0xF0041FFF 1KB 256B
TI OTP, TCM Flash Bank 0 0xF0080000 0xF0081FFF 8KB 4KB
TI OTP, TCM Flash Bank 1 0xF0082000 0xF0083FFF 8KB 4KB
TI OTP, EEPROM Bank 7 0xF008E000 0xF008FFFF 8KB 2KB
TI OTP–ECC, TCM Flash Bank 0 0xF00C0000 0xF00C03FF 1KB 512B
TI OTP–ECC, TCM Flash Bank 1 0xF00C0400 0xF00C07FF 1KB 512B
TI OTP–ECC, EEPROM Bank 7 0xF00C1C00 0xF00C1FFF 1KB 256B
EEPROM Bank–ECC 0xF0100000 0xF013FFFF 256KB 8KB
EEPROM Bank 0xF0200000 0xF03FFFFF 2MB 64KB
Flash Data Space ECC 0xF0400000 0xF04FFFFF 1MB 384KB
ETHERNET AND EMIF SLAVE INTERFACES
CPPI Memory Slave (Ethernet RAM) 0xFC520000 0xFC521FFF 8KB 8KB Abort
EMAC Slave (Ethernet Slave) 0xFCF78000 0xFCF787FF 2KB 2KB No error
EMACSS Wrapper (Ethernet Wrapper) 0xFCF78800 0xFCF788FF 256B 256B No error
Ethernet MDIO Interface 0xFCF78900 0xFCF789FF 256B 256B No error
EMIF Registers 0xFCFFE800 0xFCFFE8FF 256B 256B Abort
CYCLIC REDUNDANCY CHECKER (CRC) MODULE REGISTERS
CRC CRC frame 0xFE000000 0xFEFFFFFF 16MB 512B Accesses above 0x200 generate abort.
PERIPHERAL MEMORIES
MIBSPI5 RAM PCS[5] 0xFF0A0000 0xFF0BFFFF 128KB 2KB Abort for accesses above 2KB
MIBSPI3 RAM PCS[6] 0xFF0C0000 0xFF0DFFFF 128KB 2KB Abort for accesses above 2KB
MIBSPI1 RAM PCS[7] 0xFF0E0000 0xFF0FFFFF 128KB 2KB Abort for accesses above 2KB
DCAN3 RAM PCS[13] 0xFF1A0000 0xFF1BFFFF 128KB 2KB Wrap around for accesses to unimplemented address offsets lower than 0x7FF. Abort generated for accesses beyond offset 0x800.
DCAN2 RAM PCS[14] 0xFF1C0000 0xFF1DFFFF 128KB 2KB Wrap around for accesses to unimplemented address offsets lower than 0x7FF. Abort generated for accesses beyond offset 0x800.
DCAN1 RAM PCS[15] 0xFF1E0000 0xFF1FFFFF 128KB 2KB Wrap around for accesses to unimplemented address offsets lower than 0x7FF. Abort generated for accesses beyond offset 0x800.
MIBADC2 RAM PCS[29] 0xFF3A0000 0xFF3BFFFF 128KB 8KB Wrap around for accesses to unimplemented address offsets lower than 0x1FFF. Abort generated for accesses beyond 0x1FFF.
MIBADC1 RAM PCS[31] 0xFF3E0000 0xFF3FFFFF 128KB 8KB Wrap around for accesses to unimplemented address offsets lower than 0x1FFF. Abort generated for accesses beyond 0x1FFF.
N2HET2 RAM PCS[34] 0xFF440000 0xFF45FFFF 128KB 16KB Wrap around for accesses to unimplemented address offsets lower than 0x3FFF. Abort generated for accesses beyond 0x3FFF.
N2HET1 RAM PCS[35] 0xFF460000 0xFF47FFFF 128KB 16KB Wrap around for accesses to unimplemented address offsets lower than 0x3FFF. Abort generated for accesses beyond 0x3FFF.
HTU2 RAM PCS[38] 0xFF4C0000 0xFF4DFFFF 128KB 1KB Abort
HTU1 RAM PCS[39] 0xFF4E0000 0xFF4FFFFF 128KB 1KB Abort
DEBUG COMPONENTS
CoreSight Debug ROM CSCS0 0xFFA00000 0xFFA00FFF 4KB 4KB Reads: 0, writes: no effect
Cortex-R4F Debug CSCS1 0xFFA01000 0xFFA01FFF 4KB 4KB Reads: 0, writes: no effect
ETM-R4 CSCS2 0xFFA02000 0xFFA02FFF 4KB 4KB Reads: 0, writes: no effect
CoreSight TPIU CSCS3 0xFFA03000 0xFFA03FFF 4KB 4KB Reads: 0, writes: no effect
POM CSCS4 0xFFA04000 0xFFA04FFF 4KB 4KB Abort
PERIPHERAL CONTROL REGISTERS
HTU1 PS[22] 0xFFF7A400 0xFFF7A4FF 256B 256B Reads: 0, writes: no effect
HTU2 PS[22] 0xFFF7A500 0xFFF7A5FF 256B 256B Reads: 0, writes: no effect
N2HET1 PS[17] 0xFFF7B800 0xFFF7B8FF 256B 256B Reads: 0, writes: no effect
N2HET2 PS[17] 0xFFF7B900 0xFFF7B9FF 256B 256B Reads: 0, writes: no effect
GPIO PS[16] 0xFFF7BC00 0xFFF7BCFF 256B 256B Reads: 0, writes: no effect
MIBADC1 PS[15] 0xFFF7C000 0xFFF7C1FF 512B 512B Reads: 0, writes: no effect
MIBADC2 PS[15] 0xFFF7C200 0xFFF7C3FF 512B 512B Reads: 0, writes: no effect
I2C PS[10] 0xFFF7D400 0xFFF7D4FF 256B 256B Reads: 0, writes: no effect
DCAN1 PS[8] 0xFFF7DC00 0xFFF7DDFF 512B 512B Reads: 0, writes: no effect
DCAN2 PS[8] 0xFFF7DE00 0xFFF7DFFF 512B 512B Reads: 0, writes: no effect
DCAN3 PS[7] 0xFFF7E000 0xFFF7E1FF 512B 512B Reads: 0, writes: no effect
LIN PS[6] 0xFFF7E400 0xFFF7E4FF 256B 256B Reads: 0, writes: no effect
SCI PS[6] 0xFFF7E500 0xFFF7E5FF 256B 256B Reads: 0, writes: no effect
MibSPI1 PS[2] 0xFFF7F400 0xFFF7F5FF 512B 512B Reads: 0, writes: no effect
SPI2 PS[2] 0xFFF7F600 0xFFF7F7FF 512B 512B Reads: 0, writes: no effect
MibSPI3 PS[1] 0xFFF7F800 0xFFF7F9FF 512B 512B Reads: 0, writes: no effect
SPI4 PS[1] 0xFFF7FA00 0xFFF7FBFF 512B 512B Reads: 0, writes: no effect
MibSPI5 PS[0] 0xFFF7FC00 0xFFF7FDFF 512B 512B Reads: 0, writes: no effect
SYSTEM MODULES CONTROL REGISTERS AND MEMORIES
DMA RAM PPCS0 0xFFF80000 0xFFF80FFF 4KB 4KB Abort
VIM RAM PPCS2 0xFFF82000 0xFFF82FFF 4KB 1KB Wrap around for accesses to unimplemented address offsets between 1kB and 4kB.
RTP RAM PPCS3 0xFFF83000 0xFFF83FFF 4KB 4KB Abort
Flash Module PPCS7 0xFFF87000 0xFFF87FFF 4KB 4KB Abort
eFuse Controller PPCS12 0xFFF8C000 0xFFF8CFFF 4KB 4KB Abort
Power Management Module (PMM) PPSE0 0xFFFF0000 0xFFFF01FF 512B 512B Abort
Test Controller (FMTM) PPSE1 0xFFFF0400 0xFFFF07FF 1KB 1KB Reads: 0, writes: no effect
PCR registers PPS0 0xFFFFE000 0xFFFFE0FF 256B 256B Reads: 0, writes: no effect
System Module - Frame 2 (see device TRM) PPS0 0xFFFFE100 0xFFFFE1FF 256B 256B Reads: 0, writes: no effect
PBIST PPS1 0xFFFFE400 0xFFFFE5FF 512B 512B Reads: 0, writes: no effect
STC PPS1 0xFFFFE600 0xFFFFE6FF 256B 256B Generates address error interrupt, if enabled
IOMM Multiplexing Control Module PPS2 0xFFFFEA00 0xFFFFEBFF 512B 512B Reads: 0, writes: no effect
DCC1 PPS3 0xFFFFEC00 0xFFFFECFF 256B 256B Reads: 0, writes: no effect
DMA PPS4 0xFFFFF000 0xFFFFF3FF 1KB 1KB Reads: 0, writes: no effect
DCC2 PPS5 0xFFFFF400 0xFFFFF4FF 256B 256B Reads: 0, writes: no effect
ESM PPS5 0xFFFFF500 0xFFFFF5FF 256B 256B Reads: 0, writes: no effect
CCMR4 PPS5 0xFFFFF600 0xFFFFF6FF 256B 256B Reads: 0, writes: no effect
DMM PPS5 0xFFFFF700 0xFFFFF7FF 256B 256B Reads: 0, writes: no effect
RAM ECC even PPS6 0xFFFFF800 0xFFFFF8FF 256B 256B Reads: 0, writes: no effect
RAM ECC odd PPS6 0xFFFFF900 0xFFFFF9FF 256B 256B Reads: 0, writes: no effect
RTP PPS6 0xFFFFFA00 0xFFFFFAFF 256B 256B Reads: 0, writes: no effect
RTI + DWWD PPS7 0xFFFFFC00 0xFFFFFCFF 256B 256B Reads: 0, writes: no effect
VIM Parity PPS7 0xFFFFFD00 0xFFFFFDFF 256B 256B Reads: 0, writes: no effect
VIM PPS7 0xFFFFFE00 0xFFFFFEFF 256B 256B Reads: 0, writes: no effect
System Module - Frame 1 (see device TRM) PPS7 0xFFFFFF00 0xFFFFFFFF 256B 256B Reads: 0, writes: no effect
(1) The RM48L540 device has only 192KB of RAM.
(2) The RM48L740 and RM48L540 devices only have 2MB of Flash

6.9.3 Master/Slave Access Privileges

Table 6-21 lists the access permissions for each bus master on the device. A bus master is a module that can initiate a read or a write transaction on the device.

Each slave module on the main interconnect is listed in the table. A "Yes" indicates that the module listed in the "MASTERS" column can access that slave module.

Table 6-21 Master / Slave Access Matrix

MASTERS ACCESS MODE SLAVES ON MAIN SCR
Flash Module Bus2 Interface:
OTP, ECC, EEPROM Bank
Non-CPU Accesses to Program Flash and CPU Data RAM CRC EMIF, Ethernet Slave Interfaces Peripheral Control Registers, All Peripheral Memories, And All System Module Control Registers And Memories
CPU READ User/Privilege Yes Yes Yes Yes Yes
CPU WRITE User/Privilege No Yes Yes Yes Yes
DMA User Yes Yes Yes Yes Yes
POM User Yes Yes Yes Yes Yes
DMM User Yes Yes Yes Yes Yes
DAP Privilege Yes Yes Yes Yes Yes
HTU1 Privilege No Yes Yes Yes Yes
HTU2 Privilege No Yes Yes Yes Yes
EMAC DMA User No Yes No Yes No

6.9.3.1 Special Notes on Accesses to Certain Slaves

Write accesses to the Power Domain Management Module (PMM) control registers are limited to the CPU (master id = 1). The other masters can only read from these registers.

A debugger can also write to the PMM registers. The master-id check is disabled in debug mode.

The device contains dedicated logic to generate a bus error response on any access to a module that is in a power domain that has been turned OFF.

6.9.4 POM Overlay Considerations

  • The POM overlay can map onto up to 8MB of the internal or external memory space. The starting address and the size of the memory overlay are configurable via the POM module control registers. Care must be taken to ensure that the overlay is mapped on to available memory.
  • ECC must be disabled by software via CP15 in case POM overlay is enabled; otherwise ECC errors will be generated.
  • POM overlay must not be enabled when the flash and internal RAM memories are swapped via the MEM SWAP field of the Bus Matrix Module Control Register 1 (BMMCR1).
  • When POM is used to overlay the flash onto internal or external RAM, there is a bus contention possibility when another master accesses the TCM flash. This results in a system hang.
    • The POM module implements a time-out feature to detect this exact scenario. The time-out needs to be enabled whenever POM overlay is enabled.
    • The time-out can be enabled by writing 1010 to the Enable TimeOut (ETO) field of the POM Global Control register (POMGLBCTRL, address = 0xFFA04000).
    • In case a read request by the POM cannot be completed within 32 HCLK cycles, the time-out (TO) flag is set in the POM Flag register (POMFLG, address = 0xFFA0400C). Also, an abort is generated to the CPU. This can be a prefetch abort for an instruction fetch or a data abort for a data fetch.
    • The prefetch- and data-abort handlers must be modified to check if the TO flag in the POM module is set. If so, then the application can assume that the time-out is caused by a bus contention between the POM transaction and another master accessing the same memory region. The abort handlers need to clear the TO flag, so that any further aborts are not misinterpreted as having been caused due to a time-out from the POM.

6.10 Flash Memory

6.10.1 Flash Memory Configuration

Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense amplifiers, and control logic.

Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical construction constraints.

Flash Pump: A charge pump which generates all the voltages required for reading, programming, or erasing the flash banks.

Flash Module: Interface circuitry required between the host CPU and the flash banks and pump module.

Table 6-22 Flash Memory Banks and Sectors

MEMORY ARRAYS (OR BANKS)(1) SECTOR
NO.
SEGMENT
(BYTES)
LOW ADDRESS HIGH ADDRESS
BANK0 (1.5MB) 0 32KB 0x00000000 0x00007FFF
1 32KB 0x00008000 0x0000FFFF
2 32KB 0x00010000 0x00017FFF
3 32KB 0x00018000 0x0001FFFF
4 128KB 0x00020000 0x0003FFFF
5 128KB 0x00040000 0x0005FFFF
6 128KB 0x00060000 0x0007FFFF
7 128KB 0x00080000 0x0009FFFF
8 128KB 0x000A0000 0x000BFFFF
9 128KB 0x000C0000 0x000DFFFF
10 128KB 0x000E0000 0x000FFFFF
11 128KB 0x00100000 0x0011FFFF
12 128KB 0x00120000 0x0013FFFF
13 128KB 0x00140000 0x0015FFFF
14 128KB 0x00160000 0x0017FFFF
BANK1 (1.5MB) 0 128KB 0x00180000 0x0019FFFF
1 128KB 0x001A0000 0x001BFFFF
2 128KB 0x001C0000 0x001DFFFF
3 128KB 0x001E0000 0x001FFFFF
(3MB devices only) 4 128KB 0x00200000 0x0021FFFF
5 128KB 0x00220000 0x0023FFFF
6 128KB 0x00240000 0x0025FFFF
7 128KB 0x00260000 0x0027FFFF
8 128KB 0x00280000 0x0029FFFF
9 128KB 0x002A0000 0x002BFFFF
10 128KB 0x002C0000 0x002DFFFF
11 128KB 0x002E0000 0x002FFFFF
BANK7 (64KB) for EEPROM emulation(2)(3) 0 16KB 0xF0200000 0xF0203FFF
1 16KB 0xF0204000 0xF0207FFF
2 16KB 0xF0208000 0xF020BFFF
3 16KB 0xF020C000 0xF020FFFF
(1) The flash banks are 144-bit-wide bank with ECC support.
(2) The flash bank7 can be programmed while executing code from flash bank0 or bank1.
(3) Code execution is not allowed from flash bank7.

6.10.2 Main Features of Flash Module

  • Support for multiple flash banks for program and/or data storage
  • Simultaneous read access on a bank while performing program or erase operation on any other bank
  • Integrated state machines to automate flash erase and program operations
  • Software interface for flash program and erase operations
  • Pipelined mode operation to improve instruction access interface bandwidth
  • Support for Single Error Correction Double Error Detection (SECDED) block inside Cortex-R4F CPU
    • Error address is captured for host system debugging
  • Support for a rich set of diagnostic features

6.10.3 ECC Protection for Flash Accesses

All accesses to the program flash memory are protected by Single Error Correction Double Error Detection (SECDED) logic embedded inside the CPU. The flash module provides 8 bits of ECC code for 64 bits of instructions or data fetched from the flash memory. The CPU calculates the expected ECC code based on the 64 bits received and compares it with the ECC code returned by the flash module. A single-bit error is corrected and flagged by the CPU, while a multibit error is only flagged. The CPU signals an ECC error via its Event bus. This signaling mechanism is not enabled by default and must be enabled by setting the 'X' bit of the Performance Monitor Control Register, c9.

MRC p15,#0,r1,c9,c12,#0 ;Enabling Event monitor statesORR r1, r1, #0x00000010MCR p15,#0,r1,c9,c12,#0 ;Set 4th bit (‘X’) of PMNC registerMRC p15,#0,r1,c9,c12,#0

The application must also explicitly enable the CPU's ECC checking for accesses on the CPU's ATCM and BTCM interfaces. These are connected to the program flash and data RAM respectively. ECC checking for these interfaces can be done by setting the B1TCMPCEN, B0TCMPCEN and ATCMPCEN bits of the System Control coprocessor's Auxiliary Control Register, c1.

MRC p15, #0, r1, c1, c0, #1ORR r1, r1, #0x0e000000 ;Enable ECC checking for ATCM and BTCMsDMBMCR p15, #0, r1, c1, c0, #1

6.10.4 Flash Access Speeds

For information on flash memory access speeds and the relevant wait states required, refer to Section 5.6.

6.10.5 Flash Program and Erase Timings for Program Flash

Table 6-23 Timing Specifications for Program Flash

PARAMETER MIN NOM MAX UNIT
tprog (144bit) Wide Word (144bit) programming time 40 300 µs
tprog (Total) 3-MB programming time(1) –40°C to 105°C 32 s
0°C to 60°C, for first 25 cycles 8 16 s
terase Sector/Bank erase time(2) –40°C to 105°C 0.03 4 s
0°C to 60°C, for first 25 cycles 16 100 ms
twec Write/erase cycles with 15-year Data Retention requirement –40°C to 105°C 1000 cycles
(1) This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes programming 144 bits at a time at the maximum specified operating frequency.
(2) During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase a sector.

6.10.6 Flash Program and Erase Timings for Data Flash

Table 6-24 Timing Specifications for Data Flash

PARAMETER MIN NOM MAX UNIT
tprog (144bit) Wide Word (144bit) programming time 40 300 µs
tprog (Total) 64-KB programming time(1) –40°C to 105°C 660 ms
0°C to 60°C, for first 25 cycles 165 330 ms
terase Sector/Bank erase time(1) –40°C to 105°C 0.2 8 s
0°C to 60°C, for first 25 cycles 14 100 ms
twec Write/erase cycles with 15-year Data Retention requirement –40°C to 105°C 100000 cycles
(1) During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase a sector.

6.11 Tightly Coupled RAM (TCRAM) Interface Module

Figure 6-12 illustrates the connection of the Tightly Coupled RAM (TCRAM) to the Cortex-R4F CPU.

RM48L940 RM48L740 RM48L540 tcram_fbd_spns185.gifFigure 6-12 TCRAM Block Diagram

6.11.1 Features

The features of the TCRAM Module are:

  • Acts as slave to the BTCM interface of the Cortex-R4F CPU
  • Supports CPU's internal ECC scheme by providing 64-bit data and 8-bit ECC code
  • Monitors CPU Event Bus and generates single or multibit error interrupts
  • Stores addresses for single and multibit errors
  • Supports RAM trace module
  • Provides CPU address bus integrity checking by supporting parity checking on the address bus
  • Performs redundant address decoding for the RAM bank chip select and ECC select generation logic
  • Provides enhanced safety for the RAM addressing by implementing two 36-bit-wide byte-interleaved RAM banks and generating independent RAM access control signals to the two banks
  • Supports auto-initialization of the RAM banks along with the ECC bits

6.11.2 TCRAM Interface ECC Support

The TCRAM interface passes on the ECC code for each data read by the Cortex-R4F CPU from the RAM. It also stores the ECC port contents of the CPU in the ECC RAM when the CPU does a write to the RAM. The TCRAM interface monitors the event bus of the CPU and provides registers for indicating singlebit or multibit errors and also for identifying the address that caused the single or multibit error. The event signaling and the ECC checking for the RAM accesses must be enabled inside the CPU.

For more information see the device specific technical reference manual.

6.12 Parity Protection for Peripheral RAMs

Most peripheral RAMs are protected by odd/even parity checking. During a read access the parity is calculated based on the data read from the peripheral RAM and compared with the good parity value stored in the parity RAM for that peripheral. If any word fails the parity check, the module generates a parity error signal that is mapped to the Error Signaling Module. The module also captures the peripheral RAM address that caused the parity error.

The parity protection for peripheral RAMs is not enabled by default and must be enabled by the application. Each individual peripheral contains control registers to enable the parity protection for accesses to its RAM.

NOTE

The CPU read access gets the actual data from the peripheral. The application can choose to generate an interrupt whenever a peripheral RAM parity error is detected.

6.13 On-Chip SRAM Initialization and Testing

6.13.1 On-Chip SRAM Self-Test Using PBIST

6.13.1.1 Features

  • Extensive instruction set to support various memory test algorithms
  • ROM-based algorithms allow application to run TI production-level memory tests
  • Independent testing of all on-chip SRAM

6.13.1.2 PBIST RAM Groups

Table 6-25 PBIST RAM Grouping

MEMORY RAM GROUP TEST CLOCK MEM TYPE TEST PATTERN (ALGORITHM)
TRIPLE READ
SLOW READ
TRIPLE READ
FAST READ
MARCH 13N(1)
TWO PORT
(CYCLES)
MARCH 13N(1)
SINGLE PORT
(CYCLES)
ALGO MASK 0x1 ALGO MASK 0x2 ALGO MASK 0x4 ALGO MASK 0x8
PBIST_ROM 1 ROM CLK ROM 24578 8194
STC_ROM 2 ROM CLK ROM 19586 6530
DCAN1 3 VCLK Dual Port 25200
DCAN2 4 VCLK Dual Port 25200
DCAN3 5 VCLK Dual Port 25200
ESRAM1(2) 6 HCLK Single Port 266280
MIBSPI1 7 VCLK Dual Port 33440
MIBSPI3 8 VCLK Dual Port 33440
MIBSPI5 9 VCLK Dual Port 33440
VIM 10 VCLK Dual Port 12560
MIBADC1 11 VCLK Dual Port 4200
DMA 12 HCLK Dual Port 18960
N2HET1 13 VCLK Dual Port 31680
HTU1 14 VCLK Dual Port 6480
RTP 15 HCLK Dual Port 37800
MIBADC2 18 VCLK Dual Port 4200
N2HET2 19 VCLK Dual Port 31680
HTU2 20 VCLK Dual Port 6480
ESRAM5(3) 21 HCLK Single Port 266280
ESRAM6(4) 22 HCLK Single Port 266280
ETHERNET 23 VCLK3 Dual Port 8700
24 6360
25 Single Port 133160
ESRAM8(5) 28 HCLK Single Port 266280
(1) There are several memory testing algorithms stored in the PBIST ROM. However, TI recommends the March13N algorithm for application testing.
(2) ESRAM1: Address 0x08000000 - 0x0800FFFF (Always on power domain)
(3) ESRAM5: Address 0x08010000 - 0x0801FFFF (RAM power domain 1)
(4) ESRAM6: Address 0x08020000 - 0x0802FFFF (RAM power domain 2)
(5) ESRAM8: Address 0x08030000 - 0x0803FFFF (RAM power domain 3) Not available on theRM48L540 device.

The PBIST ROM clock frequency is limited to 100 MHz, if 100 MHz < HCLK <= HCLKmax, or HCLK, if HCLK <= 100 MHz.

The PBIST ROM clock is divided down from HCLK. The divider is selected by programming the ROM_DIV field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58.

6.13.2 On-Chip SRAM Auto Initialization

This microcontroller allows some of the on-chip memories to be initialized to zero through the Memory Hardware Initialization mechanism in the System module. This hardware mechanism allows an application to program the memory arrays with error detection capability to a known state based on their error detection scheme (odd/even parity or ECC).

The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects the memories that are to be initialized.

For more information on these registers see the device specific technical reference manual.

The mapping of the different on-chip memories to the specific bits of the MSINENA registers is shown in Table 6-26.

Table 6-26 Memory Initialization

CONNECTING MODULE ADDRESS RANGE MSINENA REGISTER
BIT NO.
BASE ADDRESS ENDING ADDRESS
RAM (PD#1) 0x08000000 0x0800FFFF 0(1)
RAM (RAM_PD#1) 0x08010000 0x0801FFFF 0(1)
RAM (RAM_PD#2) 0x08020000 0x0802FFFF 0(1)
RAM (RAM_PD#3)(3) 0x08030000 0x0803FFFF 0(1)
MIBSPI5 RAM 0xFF0A0000 0xFF0BFFFF 12(2)
MIBSPI3 RAM 0xFF0C0000 0xFF0DFFFF 11(2)
MIBSPI1 RAM 0xFF0E0000 0xFF0FFFFF 7(2)
DCAN3 RAM 0xFF1A0000 0xFF1BFFFF 10
DCAN2 RAM 0xFF1C0000 0xFF1DFFFF 6
DCAN1 RAM 0xFF1E0000 0xFF1FFFFF 5
MIBADC2 RAM 0xFF3A0000 0xFF3BFFFF 14
MIBADC1 RAM 0xFF3E0000 0xFF3FFFFF 8
N2HET2 RAM 0xFF440000 0xFF45FFFF 15
N2HET1 RAM 0xFF460000 0xFF47FFFF 3
HTU2 RAM 0xFF4C0000 0xFF4DFFFF 16
HTU1 RAM 0xFF4E0000 0xFF4FFFFF 4
DMA RAM 0xFFF80000 0xFFF80FFF 1
VIM RAM 0xFFF82000 0xFFF82FFF 2
Ethernet RAM (CPPI Memory Slave) 0xFC520000 0xFC521FFF n/a
(1) The TCM RAM wrapper has separate control bits to select the RAM power domain that is to be auto-initialized.
(2) The MibSPIx modules perform an initialization of the transmit and receive RAMs as soon as the module is released from its local reset via the SPIGCR0 register. This is independent of whether the application chooses to initialize the MibSPIx RAMs using the system module auto-initialization method. Before the MibSPI RAM can be initialized using the system module auto-initialization method: (I) The module must be released from its local reset, AND (ii) The application must poll for the "BUF INIT ACTIVE" status flag in the SPIFLG register to become cleared (zero)
(3) Not available on theRM48L540 device.

6.14 External Memory Interface (EMIF)

6.14.1 Features

The EMIF includes many features to enhance the ease and flexibility of connecting to external asynchronous memories or SDRAM devices. The EMIF features includes support for:

  • 3 addressable chip select for asynchronous memories of up to 16MB each
  • 1 addressable chip select space for SDRAMs up to 128MB
  • 8- or 16-bit data bus width
  • Programmable cycle timings such as setup, strobe, and hold times as well as turnaround time
  • Select strobe mode
  • Extended Wait mode
  • Data bus parking

6.14.2 Electrical and Timing Specifications

6.14.2.1 Asynchronous RAM

RM48L940 RM48L740 RM48L540 emif_async_memory_read_timing_pns160.gifFigure 6-13 Asynchronous Memory Read Timing
RM48L940 RM48L740 RM48L540 emif_nwait_read_pns160.gifFigure 6-14 EMIFnWAIT Read Timing Requirements
RM48L940 RM48L740 RM48L540 emif_async_memory_write_timing_pns160.gifFigure 6-15 Asynchronous Memory Write Timing
RM48L940 RM48L740 RM48L540 emif_nwait_write_pns160.gifFigure 6-16 EMIFnWAIT Write Timing Requirements

Table 6-27 EMIF Asynchronous Memory Timing Requirements

NO. MIN NOM MAX UNIT
READS AND WRITES
E EMIF clock period 10 ns
2 tw(EM_WAIT) Pulse duration, EMIFnWAIT assertion and deassertion 2E ns
READS
12 tsu(EMDV-EMOEH) Setup time, EMIFDATA[15:0] valid before EMIFnOE high 30 ns
13 th(EMOEH-EMDIV) Hold time, EMIFDATA[15:0] valid after EMIFnOE high 0.5 ns
14 tsu(EMOEL-EMWAIT) Setup Time, EMIFnWAIT asserted before end of Strobe Phase(1) 4E+30 ns
WRITES
28 tsu(EMWEL-EMWAIT) Setup Time, EMIFnWAIT asserted before end of Strobe Phase(1) 4E+30 ns
(1) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMIFnWAIT must be asserted to add extended wait states. Figure 6-14 and Figure 6-16 describe EMIF transactions that include extended wait states inserted during the STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles.

Table 6-28 EMIF Asynchronous Memory Switching Characteristics(1)(2)(3)

NO. PARAMETER MIN NOM MAX UNIT
READS AND WRITES
1 td(TURNAROUND) Turn around time (TA)*E-4 (TA)*E (TA)*E+3 ns
READS
3 tc(EMRCYCLE) EMIF read cycle time (EW = 0) (RS+RST+RH)*E-3 (RS+RST+RH)*E (RS+RST+RH)*E+3 ns
EMIF read cycle time (EW = 1) (RS+RST+RH+(EWC*16))* E-3 (RS+RST+RH+(EWC*16))* E (RS+RST+RH+(EWC*16))* E+3
4 tsu(EMCEL-EMOEL) Output setup time, EMIFnCS[4:2] low to EMIFnOE low (SS = 0) (RS)*E-4 (RS)*E (RS)*E+3 ns
Output setup time, EMIFnCS[4:2] low to EMIFnOE low (SS = 1) -3 0 +3
5 th(EMOEH-EMCEH) Output hold time, EMIFnOE high to EMIFnCS[4:2] high (SS = 0) (RH)*E-4 (RH)*E (RH)*E+3 ns
Output hold time, EMIFnOE high to EMIFnCS[4:2] high (SS = 1) -3 0 +3
6 tsu(EMBAV-EMOEL) Output setup time, EMIFBA[1:0] valid to EMIFnOE low (RS)*E-4 (RS)*E (RS)*E+3 ns
7 th(EMOEH-EMBAIV) Output hold time, EMIFnOE high to EMIFBA[1:0] invalid (RH)*E-4 (RH)*E (RH)*E+3 ns
8 tsu(EMAV-EMOEL) Output setup time, EMIFADDR[21:0] valid to EMIFnOE low (RS)*E-4 (RS)*E (RS)*E+3 ns
9 th(EMOEH-EMAIV) Output hold time, EMIFnOE high to EMIFADDR[21:0] invalid (RH)*E-4 (RH)*E (RH)*E+3 ns
10 tw(EMOEL) EMIFnOE active low width
(EW = 0)
(RST)*E-3 (RST)*E (RST)*E+3 ns
EMIFnOE active low width
(EW = 1)
(RST+(EWC*16))*E-3 (RST+(EWC*16))*E (RST+(EWC*16))*E+3
11 td(EMWAITH-EMOEH) Delay time from EMIFnWAIT deasserted to EMIFnOE high 3E-3 4E 4E+30 ns
29 tsu(EMDQMV-EMOEL) Output setup time, EMIFnDQM[1:0] valid to EMIFnOE low (RS)*E-4 (RS)*E (RS)*E+3 ns
30 th(EMOEH-EMDQMIV) Output hold time, EMIFnOE high to EMIFnDQM[1:0] invalid (RH)*E-4 (RH)*E (RH)*E+3 ns
WRITES
15 tc(EMWCYCLE) EMIF write cycle time (EW = 0) (WS+WST+WH)* E-3 (WS+WST+WH)*E (WS+WST+WH)* E+3 ns
EMIF write cycle time (EW = 1) (WS+WST+WH+(EWC*16))* E-3 (WS+WST+WH+(EWC*16))* E (WS+WST+WH+(EWC*16))* E+3
16 tsu(EMCEL-EMWEL) Output setup time, EMIFnCS[4:2] low to EMIFnWE low (SS = 0) (WS)*E -4 (WS)*E (WS)*E + 3 ns
Output setup time, EMIFnCS[4:2] low to EMIFnWE low (SS = 1) -4 0 +3
17 th(EMWEH-EMCEH) Output hold time, EMIFnWE high to EMIFnCS[4:2] high (SS = 0) (WH)*E-4 (WH)*E (WH)*E+3 ns
Output hold time, EMIFnWE high to EMIFCS[4:2] high (SS = 1) -4 0 +3
18 tsu(EMDQMV-EMWEL) Output setup time, EMIFBA[1:0] valid to EMIFnWE low (WS)*E-4 (WS)*E (WS)*E+3 ns
19 th(EMWEH-EMDQMIV) Output hold time, EMIFnWE high to EMIFBA[1:0] invalid (WH)*E-4 (WH)*E (WH)*E+3 ns
20 tsu(EMBAV-EMWEL) Output setup time, EMIFBA[1:0] valid to EMIFnWE low (WS)*E-4 (WS)*E (WS)*E+3 ns
21 th(EMWEH-EMBAIV) Output hold time, EMIFnWE high to EMIFBA[1:0] invalid (WH)*E-4 (WH)*E (WH)*E+3 ns
22 tsu(EMAV-EMWEL) Output setup time, EMIFADDR[21:0] valid to EMIFnWE low (WS)*E-4 (WS)*E (WS)*E+3 ns
23 th(EMWEH-EMAIV) Output hold time, EMIFnWE high to EMIFADDR[21:0] invalid (WH)*E-4 (WH)*E (WH)*E+3 ns
24 tw(EMWEL) EMIFnWE active low width (EW = 0) (WST)*E-3 (WST)*E (WST)*E+3 ns
EMIFnWE active low width (EW = 1) (WST+(EWC*16))*E-3 (WST+(EWC*16))*E (WST+(EWC*16))* E+3
25 td(EMWAITH-EMWEH) Delay time from EMIFnWAIT deasserted to EMIFnWE high 3E-4 4E 4E+30 ns
26 tsu(EMDV-EMWEL) Output setup time, EMIFDATA[15:0] valid to EMIFnWE low (WS)*E-4 (WS)*E (WS)*E+3 ns
27 th(EMWEH-EMDIV) Output hold time, EMIFnWE high to EMIFDATA[15:0] invalid (WH)*E-4 (WH)*E (WH)*E+3 ns
31 tsu(EMDQMV-EMWEL) Output setup time, EMIFnDQM[1:0] valid to EMIFnWE low (WH)*E-4 (WH)*E (WH)*E+3 ns
32 th(EMWEH-EMDQMIV) Output hold time, EMIFnWE high to EMIFnDQM[1:0] invalid (WH)*E-4 (WH)*E (WH)*E+3 ns
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–1], RH[8–1], WS[16–1], WST[64–1], WH[8–1], and MEWC[1–256]. See the RM48x Technical Reference Manual (SPNU503) for more information.
(2) E = EMIF_CLK period in ns.
(3) EWC = external wait cycles determined by EMIFnWAIT input signal. EWC supports the following range of values. EWC[256–1]. Note that the maximum wait time before time-out is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See the RM48x Technical Reference Manual (SPNU503) for more information.

6.14.2.2 Synchronous Timing

RM48L940 RM48L740 RM48L540 emif_sdram_read_pns160.gifFigure 6-17 Basic SDRAM Read Operation
RM48L940 RM48L740 RM48L540 emif_sdram_write_pns160.gifFigure 6-18 Basic SDRAM Write Operation

Table 6-29 EMIF Synchronous Memory Timing Requirements

NO. MIN MAX UNIT
19 tsu(EMIFDV-EM_CLKH) Input setup time, read data valid on EMIFDATA[15:0] before EMIF_CLK rising 2 ns
20 th(CLKH-DIV) Input hold time, read data valid on EMIFDATA[15:0] after EMIF_CLK rising 1.5 ns

Table 6-30 EMIF Synchronous Memory Switching Characteristics

NO. PARAMETER MIN MAX UNIT
1 tc(CLK) Cycle time, EMIF clock EMIF_CLK 20 ns
2 tw(CLK) Pulse width, EMIF clock EMIF_CLK high or low 5 ns
3 td(CLKH-CSV) Delay time, EMIF_CLK rising to EMIFnCS[0] valid 13 ns
4 toh(CLKH-CSIV) Output hold time, EMIF_CLK rising to EMIFnCS[0] invalid 1 ns
5 td(CLKH-DQMV) Delay time, EMIF_CLK rising to EMIFnDQM[1:0] valid 13 ns
6 toh(CLKH-DQMIV) Output hold time, EMIF_CLK rising to EMIFnDQM[1:0] invalid 1 ns
7 td(CLKH-AV) Delay time, EMIF_CLK rising to EMIFADDR[21:0] and EMIFBA[1:0] valid 13 ns
8 toh(CLKH-AIV) Output hold time, EMIF_CLK rising to EMIFADDR[21:0] and EMIFBA[1:0] invalid 1 ns
9 td(CLKH-DV) Delay time, EMIF_CLK rising to EMIFDATA[15:0] valid 13 ns
10 toh(CLKH-DIV) Output hold time, EMIF_CLK rising to EMIFDATA[15:0] invalid 1 ns
11 td(CLKH-RASV) Delay time, EMIF_CLK rising to EMIFnRAS valid 13 ns
12 toh(CLKH-RASIV) Output hold time, EMIF_CLK rising to EMIFnRAS invalid 1 ns
13 td(CLKH-CASV) Delay time, EMIF_CLK rising to EMIFnCAS valid 13 ns
14 toh(CLKH-CASIV) Output hold time, EMIF_CLK rising to EMIFnCAS invalid 1 ns
15 td(CLKH-WEV) Delay time, EMIF_CLK rising to EMIFnWE valid 13 ns
16 toh(CLKH-WEIV) Output hold time, EMIF_CLK rising to EMIFnWE invalid 1 ns
17 tdis(CLKH-DHZ) Delay time, EMIF_CLK rising to EMIFDATA[15:0] tri-stated 7 ns
18 tena(CLKH-DLZ) Output hold time, EMIF_CLK rising to EMIFDATA[15:0] driving 1 ns

6.15 Vectored Interrupt Manager

The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling the many interrupt sources present on this device. Interrupts are caused by events outside of the normal flow of program execution. Normally, these events require a timely response from the central processing unit (CPU); therefore, when an interrupt occurs, the CPU switches execution from the normal program flow to an interrupt service routine (ISR).

6.15.1 VIM Features

The VIM module has the following features:

  • Supports 96 interrupt channels.
    • Provides programmable priority and enable for interrupt request lines.
  • Provides a direct hardware dispatch mechanism for fastest IRQ dispatch.
  • Provides two software dispatch mechanisms when the CPU VIC port is not used.
    • Index interrupt
    • Register vectored interrupt
  • Parity protected vector interrupt table

6.15.2 Interrupt Request Assignments

Table 6-31 Interrupt Request Assignments

MODULES INTERRUPT SOURCES DEFAULT VIM
INTERRUPT CHANNEL
ESM ESM High level interrupt (NMI) 0
Reserved Reserved 1
RTI RTI compare interrupt 0 2
RTI RTI compare interrupt 1 3
RTI RTI compare interrupt 2 4
RTI RTI compare interrupt 3 5
RTI RTI overflow interrupt 0 6
RTI RTI overflow interrupt 1 7
RTI RTI time base interrupt 8
GPIO GPIO interrupt A 9
N2HET1 N2HET1 level 0 interrupt 10
HTU1 HTU1 level 0 interrupt 11
MIBSPI1 MIBSPI1 level 0 interrupt 12
LIN LIN level 0 interrupt 13
MIBADC1 MIBADC1 event group interrupt 14
MIBADC1 MIBADC1 sw group 1 interrupt 15
DCAN1 DCAN1 level 0 interrupt 16
SPI2 SPI2 level 0 interrupt 17
Reserved Reserved 18
CRC CRC Interrupt 19
ESM ESM Low level interrupt 20
SYSTEM Software interrupt (SSI) 21
CPU PMU Interrupt 22
GPIO GPIO interrupt B 23
N2HET1 N2HET1 level 1 interrupt 24
HTU1 HTU1 level 1 interrupt 25
MIBSPI1 MIBSPI1 level 1 interrupt 26
LIN LIN level 1 interrupt 27
MIBADC1 MIBADC1 sw group 2 interrupt 28
DCAN1 DCAN1 level 1 interrupt 29
SPI2 SPI2 level 1 interrupt 30
MIBADC1 MIBADC1 magnitude compare interrupt 31
Reserved Reserved 32
DMA FTCA interrupt 33
DMA LFSA interrupt 34
DCAN2 DCAN2 level 0 interrupt 35
DMM DMM level 0 interrupt 36
MIBSPI3 MIBSPI3 level 0 interrupt 37
MIBSPI3 MIBSPI3 level 1 interrupt 38
DMA HBCA interrupt 39
DMA BTCA interrupt 40
EMIF AEMIFINT3 41
DCAN2 DCAN2 level 1 interrupt 42
DMM DMM level 1 interrupt 43
DCAN1 DCAN1 IF3 interrupt 44
DCAN3 DCAN3 level 0 interrupt 45
DCAN2 DCAN2 IF3 interrupt 46
FPU "OR" of the six Cortex R4F FPU Exceptions 47
Reserved Reserved 48
SPI4 SPI4 level 0 interrupt 49
MIBADC2 MibADC2 event group interrupt 50
MIBADC2 MibADC2 sw group1 interrupt 51
Reserved Reserved 52
MIBSPI5 MIBSPI5 level 0 interrupt 53
SPI4 SPI4 level 1 interrupt 54
DCAN3 DCAN3 level 1 interrupt 55
MIBSPI5 MIBSPI5 level 1 interrupt 56
MIBADC2 MibADC2 sw group2 interrupt 57
Reserved Reserved 58
MIBADC2 MibADC2 magnitude compare interrupt 59
DCAN3 DCAN3 IF3 interrupt 60
FMC FSM_DONE interrupt 61
Reserved Reserved 62
N2HET2 N2HET2 level 0 interrupt 63
SCI SCI level 0 interrupt 64
HTU2 HTU2 level 0 interrupt 65
I2C I2C level 0 interrupt 66
Reserved Reserved 67-72
N2HET2 N2HET2 level 1 interrupt 73
SCI SCI level 1 interrupt 74
HTU2 HTU2 level 1 interrupt 75
Ethernet C0_MISC_PULSE 76
Ethernet C0_TX_PULSE 77
Ethernet C0_THRESH_PULSE 78
Ethernet C0_RX_PULSE 79
HWAG1 HWA_INT_REQ_H 80
HWAG2 HWA_INT_REQ_H 81
DCC1 DCC1 done interrupt 82
DCC2 DCC2 done interrupt 83
Reserved Reserved 84
PBIST PBIST_DONE 85
Reserved Reserved 86
Reserved Reserved 87
HWAG1 HWA_INT_REQ_L 88
HWAG2 HWA_INT_REQ_L 89
Reserved Reserved 90-95

NOTE

Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR entry; therefore only request channels 0 to 94 can be used and are offset by 1 address in the VIM RAM.

NOTE

The lower-order interrupt channels are higher priority channels than the higher-order interrupt channels.

NOTE

The application can change the mapping of interrupt sources to the interrupt channels via the interrupt channel control registers (CHANCTRLx) inside the VIM module.

6.16 DMA Controller

The DMA controller is used to transfer data between two locations in the memory map in the background of CPU operations. Typically, the DMA is used to:

  • Transfer blocks of data between external and internal data memories
  • Restructure portions of internal data memory
  • Continually service a peripheral

6.16.1 DMA Features

  • CPU independent data transfer
  • One master port - PortB (64 bits wide) that interfaces to the RM4x Memory System.
  • FIFO buffer (4 entries deep and each 64 bits wide)
  • Channel control information is stored in RAM protected by parity
  • 16 channels with individual enable
  • Channel chaining capability
  • 32 peripheral DMA requests
  • Hardware and Software DMA requests
  • 8-, 16-, 32-, or 64-bit transactions supported
  • Multiple addressing modes for source/destination (fixed, increment, offset)
  • Auto-initiation
  • Power-management mode
  • Memory Protection with four configurable memory regions

6.16.2 Default DMA Request Map

The DMA module on this microcontroller has 16 channels and up to 32 hardware DMA requests. The module contains DREQASIx registers which are used to map the DMA requests to the DMA channels. By default, channel 0 is mapped to request 0, channel 1 to request 1, and so on.

Some DMA requests have multiple sources, as shown in Table 6-32. The application must ensure that only one of these DMA request sources is enabled at any time.

Table 6-32 DMA Request Line Connection

Modules DMA Request Sources DMA Request
MIBSPI1 MIBSPI1[1](1) DMAREQ[0]
MIBSPI1 MIBSPI1[0](2) DMAREQ[1]
SPI2 SPI2 receive DMAREQ[2]
SPI2 SPI2 transmit DMAREQ[3]
MIBSPI1 / MIBSPI3 / DCAN2 MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3 DMAREQ[4]
MIBSPI1 / MIBSPI3 / DCAN2 MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2 DMAREQ[5]
DCAN1 / MIBSPI5 DCAN1 IF2 / MIBSPI5[2] DMAREQ[6]
MIBADC1 / MIBSPI5 MIBADC1 event / MIBSPI5[3] DMAREQ[7]
MIBSPI1 / MIBSPI3 / DCAN1 MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1 DMAREQ[8]
MIBSPI1 / MIBSPI3 / DCAN2 MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1 DMAREQ[9]
MIBADC1 / I2C / MIBSPI5 MIBADC1 G1 / I2C receive / MIBSPI5[4] DMAREQ[10]
MIBADC1 / I2C / MIBSPI5 MIBADC1 G2 / I2C transmit / MIBSPI5[5] DMAREQ[11]
RTI / MIBSPI1 / MIBSPI3 RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6] DMAREQ[12]
RTI / MIBSPI1 / MIBSPI3 RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7] DMAREQ[13]
MIBSPI3 / MibADC2 / MIBSPI5 MIBSPI3[1](1) / MibADC2 event / MIBSPI5[6] DMAREQ[14]
MIBSPI3 / MIBSPI5 MIBSPI3[0](2) / MIBSPI5[7] DMAREQ[15]
MIBSPI1 / MIBSPI3 / DCAN1 / MibADC2 MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1 DMAREQ[16]
MIBSPI1 / MIBSPI3 / DCAN3 / MibADC2 MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2 DMAREQ[17]
RTI / MIBSPI5 RTI DMAREQ2 / MIBSPI5[8] DMAREQ[18]
RTI / MIBSPI5 RTI DMAREQ3 / MIBSPI5[9] DMAREQ[19]
N2HET1 / N2HET2 / DCAN3 N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3 IF2 DMAREQ[20]
N2HET1 / N2HET2 / DCAN3 N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3 IF3 DMAREQ[21]
MIBSPI1 / MIBSPI3 / MIBSPI5 MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10] DMAREQ[22]
MIBSPI1 / MIBSPI3 / MIBSPI5 MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11] DMAREQ[23]
N2HET1 / N2HET2 / SPI4 / MIBSPI5 N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12] DMAREQ[24]
N2HET1 / N2HET2 / SPI4 / MIBSPI5 N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13] DMAREQ[25]
CRC / MIBSPI1 / MIBSPI3 CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12] DMAREQ[26]
CRC / MIBSPI1 / MIBSPI3 CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13] DMAREQ[27]
LIN / MIBSPI5 LIN receive / MIBSPI5[14] DMAREQ[28]
LIN / MIBSPI5 LIN transmit / MIBSPI5[15] DMAREQ[29]
MIBSPI1 / MIBSPI3 / SCI / MIBSPI5 MIBSPI1[14] / MIBSPI3[14] / SCI receive / MIBSPI5[1](1) DMAREQ[30]
MIBSPI1 / MIBSPI3 / SCI / MIBSPI5 MIBSPI1[15] / MIBSPI3[15] / SCI transmit / MIBSPI5[0](2) DMAREQ[31]
(1) SPI1, SPI3, SPI5 receive in standard SPI mode
(2) SPI1, SPI3, SPI5 transmit in standard SPI mode

6.17 Real Time Interrupt Module

The real-time interrupt (RTI) module provides timer functionality for operating systems and for benchmarking code. The RTI module can incorporate several counters that define the time bases needed for scheduling an operating system.

The timers also allow you to benchmark certain areas of code by reading the values of the counters at the beginning and the end of the desired code range and calculating the difference between the values.

6.17.1 Features

The RTI module has the following features:

  • Two independent 64 bit counter blocks
  • Four configurable compares for generating operating system ticks or DMA requests. Each event can be driven by either counter block 0 or counter block 1.
  • Fast enabling/disabling of events
  • Two time-stamp (capture) functions for system or peripheral interrupts, one for each counter block

6.17.2 Block Diagrams

Figure 6-19 shows a high-level block diagram for one of the two 64-bit counter blocks inside the RTI module. Both the counter blocks are identical except the Network Time Unit (NTUx) inputs are only available as time base inputs for the counter block 0.

RM48L940 RM48L740 RM48L540 rti_counter_bd_pns160.gifFigure 6-19 Counter Block Diagram
RM48L940 RM48L740 RM48L540 rti_compare_bd_pns160.gifFigure 6-20 Compare Block Diagram

6.17.3 Clock Source Options

The RTI module uses the RTI1CLK clock domain for generating the RTI time bases.

The application can select the clock source for the RTI1CLK by configuring the RCLKSRC register in the System module at address 0xFFFFFF50. The default source for RTI1CLK is VCLK.

For more information on clock sources refer to Table 6-8 and Table 6-13.

6.17.4 Network Time Synchronization Inputs

The RTI module supports four NTU inputs that signal internal system events, and which can be used to synchronize the time base used by the RTI module. On this device, these NTU inputs are connected as shown in Table 6-33.

Table 6-33 Network Time Synchronization Inputs

NTU Input Source
0 Reserved
1 Reserved
2 PLL2 Clock output
3 EXTCLKIN1 clock input

6.18 Error Signaling Module

The Error Signaling Module (ESM) manages the various error conditions on the RM4x microcontroller. The error condition is handled based on a fixed severity level assigned to it. Any severe error condition can be configured to drive a low level on a dedicated device terminal called nERROR. This can be used as an indicator to an external monitor circuit to put the system into a safe state.

6.18.1 Features

The features of the ESM are:

  • 128 interrupt/error channels are supported, divided into 3 different groups
    • 64 channels with maskable interrupt and configurable error pin behavior
    • 32 error channels with nonmaskable interrupt and predefined error pin behavior
    • 32 channels with predefined error pin behavior only
  • Error pin to signal severe device failure
  • Configurable time base for error signal
  • Error forcing capability

6.18.2 ESM Channel Assignments

The ESM integrates all the device error conditions and groups them in the order of severity. Group1 is used for errors of the lowest severity while Group3 is used for errors of the highest severity. The device response to each error is determined by the severity group it is connected to. Table 6-35 shows the channel assignment for each group.

Table 6-34 ESM Groups

ERROR GROUP INTERRUPT CHARACTERISTICS INFLUENCE ON ERROR PIN
Group1 Maskable, low or high priority Configurable
Group2 Nonmaskable, high priority Fixed
Group3 No interrupt generated Fixed

Table 6-35 ESM Channel Assignments

ERROR SOURCES GROUP CHANNELS
Reserved Group1 0
MibADC2 - parity Group1 1
DMA - MPU Group1 2
DMA - parity Group1 3
Reserved Group1 4
DMA/DMM - imprecise read error Group1 5
FMC - correctable error: bus1 and bus2 interfaces
(does not include accesses to EEPROM bank)
Group1 6
N2HET1/N2HET2 - parity Group1 7
HTU1/HTU2 - parity Group1 8
HTU1/HTU2 - MPU Group1 9
PLL - Slip Group1 10
Clock Monitor - interrupt Group1 11
Reserved Group1 12
DMA/DMM - imprecise write error Group1 13
Reserved Group1 14
VIM RAM - parity Group1 15
Reserved Group1 16
MibSPI1 - parity Group1 17
MibSPI3 - parity Group1 18
MibADC1 - parity Group1 19
Reserved Group1 20
DCAN1 - parity Group1 21
DCAN3 - parity Group1 22
DCAN2 - parity Group1 23
MibSPI5 - parity Group1 24
Reserved Group1 25
RAM even bank (B0TCM) - correctable error Group1 26
CPU - self-test Group1 27
RAM odd bank (B1TCM) - correctable error Group1 28
Reserved Group1 29
DCC1 - error Group1 30
CCM-R4 - self-test Group1 31
Reserved Group1 32
Reserved Group1 33
Reserved Group1 34
FMC - correctable error (EEPROM bank access) Group1 35
FMC - uncorrectable error (EEPROM bank access) Group1 36
IOMM - Mux configuration error Group1 37
Power domain controller compare error Group1 38
Power domain controller self-test error Group1 39
eFuse Controller Error – this error signal is generated when any bit in the eFuse controller error status register is set. The application can choose to generate an interrupt whenever this bit is set to service any eFuse controller error conditions. Group1 40
eFuse Controller - Self Test Error. This error signal is generated only when a self test on the eFuse controller generates an error condition. When an ECC self test error is detected, group 1 channel 40 error signal will also be set. Group1 41
PLL2 - Slip Group1 42
Ethernet Controller master interface Group1 43
Reserved Group1 44
Reserved Group1 45
Reserved Group1 46
Reserved Group1 47
Reserved Group1 48
Reserved Group1 49
Reserved Group1 50
Reserved Group1 51
Reserved Group1 52
Reserved Group1 53
Reserved Group1 54
Reserved Group1 55
Reserved Group1 56
Reserved Group1 57
Reserved Group1 58
Reserved Group1 59
Reserved Group1 60
Reserved Group1 61
DCC2 - error Group1 62
Reserved Group1 63
GROUP 2
Reserved Group2 0
Reserved Group2 1
CCMR4 - compare Group2 2
Reserved Group2 3
FMC - uncorrectable error (address parity on bus1 accesses) Group2 4
Reserved Group2 5
RAM even bank (B0TCM) - uncorrectable error Group2 6
Reserved Group2 7
RAM odd bank (B1TCM) - uncorrectable error Group2 8
Reserved Group2 9
RAM even bank (B0TCM) - address bus parity error Group2 10
Reserved Group2 11
RAM odd bank (B1TCM) - address bus parity error Group2 12
Reserved Group2 13
Reserved Group2 14
Reserved Group2 15
TCM - ECC live lock detect Group2 16
Reserved Group2 17
Reserved Group2 18
Reserved Group2 19
Reserved Group2 20
Reserved Group2 21
Reserved Group2 22
Reserved Group2 23
RTI_WWD_NMI Group2 24
Reserved Group2 25
Reserved Group2 26
Reserved Group2 27
Reserved Group2 28
Reserved Group2 29
Reserved Group2 30
Reserved Group2 31
GROUP 3
Reserved Group3 0
eFuse Controller - autoload error Group3 1
Reserved Group3 2
RAM even bank (B0TCM) - ECC uncorrectable error Group3 3
Reserved Group3 4
RAM odd bank (B1TCM) - ECC uncorrectable error Group3 5
Reserved Group3 6
FMC - uncorrectable error: bus1 and bus2 interfaces
(does not include address parity error and errors on accesses to EEPROM bank)
Group3 7
Reserved Group3 8
Reserved Group3 9
Reserved Group3 10
Reserved Group3 11
Reserved Group3 12
Reserved Group3 13
Reserved Group3 14
Reserved Group3 15
Reserved Group3 16
Reserved Group3 17
Reserved Group3 18
Reserved Group3 19
Reserved Group3 20
Reserved Group3 21
Reserved Group3 22
Reserved Group3 23
Reserved Group3 24
Reserved Group3 25
Reserved Group3 26
Reserved Group3 27
Reserved Group3 28
Reserved Group3 29
Reserved Group3 30
Reserved Group3 31

6.19 Reset / Abort / Error Sources

Table 6-36 Reset/Abort/Error Sources

ERROR SOURCE SYSTEM MODE ERROR RESPONSE ESM HOOKUP
group.channel
CPU TRANSACTIONS
Precise write error (NCNB/Strongly Ordered) User/Privilege Precise Abort (CPU) n/a
Precise read error (NCB/Device or Normal) User/Privilege Precise Abort (CPU) n/a
Imprecise write error (NCB/Device or Normal) User/Privilege Imprecise Abort (CPU) n/a
Illegal instruction User/Privilege Undefined Instruction Trap (CPU)(1) n/a
MPU access violation User/Privilege Abort (CPU) n/a
SRAM
B0 TCM (even) ECC single error (correctable) User/Privilege ESM 1.26
B0 TCM (even) ECC double error (noncorrectable) User/Privilege Abort (CPU), ESM => nERROR 3.3
B0 TCM (even) uncorrectable error (for example, redundant address decode) User/Privilege ESM => NMI => nERROR 2.6
B0 TCM (even) address bus parity error User/Privilege ESM => NMI => nERROR 2.10
B1 TCM (odd) ECC single error (correctable) User/Privilege ESM 1.28
B1 TCM (odd) ECC double error (noncorrectable) User/Privilege Abort (CPU), ESM => nERROR 3.5
B1 TCM (odd) uncorrectable error (for example, redundant address decode) User/Privilege ESM => NMI => nERROR 2.8
B1 TCM (odd) address bus parity error User/Privilege ESM => NMI => nERROR 2.12
FLASH
FMC correctable error - Bus1 and Bus2 interfaces User/Privilege ESM 1.6
FMC uncorrectable error - Bus1 accesses
(does not include address parity error)
User/Privilege Abort (CPU), ESM => nERROR 3.7
FMC uncorrectable error - Bus2 accesses
(does not include address parity error and EEPROM bank accesses)
User/Privilege ESM => nERROR 3.7
FMC uncorrectable error - address parity error on Bus1 accesses User/Privilege ESM => NMI => nERROR 2.4
FMC correctable error - Accesses to EEPROM bank User/Privilege ESM 1.35
FMC uncorrectable error - Accesses to EEPROM bank User/Privilege ESM 1.36
DMA TRANSACTIONS
External imprecise error on read (Illegal transaction with ok response) User/Privilege ESM 1.5
External imprecise error on write (Illegal transaction with ok response) User/Privilege ESM 1.13
Memory access permission violation User/Privilege ESM 1.2
Memory parity error User/Privilege ESM 1.3
DMM TRANSACTIONS
External imprecise error on read (Illegal transaction with ok response) User/Privilege ESM 1.5
External imprecise error on write (Illegal transaction with ok response) User/Privilege ESM 1.13
HTU1
NCNB (Strongly Ordered) transaction with slave error response User/Privilege Interrupt => VIM n/a
External imprecise error (Illegal transaction with ok response) User/Privilege Interrupt => VIM n/a
Memory access permission violation User/Privilege ESM 1.9
Memory parity error User/Privilege ESM 1.8
HTU2
NCNB (Strongly Ordered) transaction with slave error response User/Privilege Interrupt => VIM n/a
External imprecise error (Illegal transaction with ok response) User/Privilege Interrupt => VIM n/a
Memory access permission violation User/Privilege ESM 1.9
Memory parity error User/Privilege ESM 1.8
N2HET1
Memory parity error User/Privilege ESM 1.7
N2HET2
Memory parity error User/Privilege ESM 1.7
ETHERNET MASTER INTERFACE
Any error reported by slave being accessed User/Privilege ESM 1.43
MIBSPI
MibSPI1 memory parity error User/Privilege ESM 1.17
MibSPI3 memory parity error User/Privilege ESM 1.18
MibSPI5 memory parity error User/Privilege ESM 1.24
MIBADC
MibADC1 Memory parity error User/Privilege ESM 1.19
MibADC2 Memory parity error User/Privilege ESM 1.1
DCAN
DCAN1 memory parity error User/Privilege ESM 1.21
DCAN2 memory parity error User/Privilege ESM 1.23
DCAN3 memory parity error User/Privilege ESM 1.22
PLL
PLL slip error User/Privilege ESM 1.10
PLL #2 slip error User/Privilege ESM 1.42
CLOCK MONITOR
Clock monitor interrupt User/Privilege ESM 1.11
DCC
DCC1 error User/Privilege ESM 1.30
DCC2 error User/Privilege ESM 1.62
CCM-R4
Self-test failure User/Privilege ESM 1.31
Compare failure User/Privilege ESM => NMI => nERROR 2.2
VIM
Memory parity error User/Privilege ESM 1.15
VOLTAGE MONITOR
VMON out of voltage range n/a Reset n/a
CPU SELF-TEST (LBIST)
CPU self-test (LBIST) error User/Privilege ESM 1.27
PIN MULTIPLEXING CONTROL
Mux configuration error User/Privilege ESM 1.37
POWER DOMAIN CONTROL
PSCON compare error User/Privilege ESM 1.38
PSCON self-test error User/Privilege ESM 1.39
eFuse CONTROLLER
eFuse Controller Autoload error User/Privilege ESM => nERROR 3.1
eFuse Controller - Any bit set in the error status register User/Privilege ESM 1.40
eFuse Controller self-test error User/Privilege ESM 1.41
WINDOWED WATCHDOG
WWD Nonmaskable Interrupt exception n/a ESM => NMI => nERROR 2.24
ERRORS REFLECTED IN THE SYSESR REGISTER
Power-Up Reset n/a Reset n/a
Oscillator fail / PLL slip(2) n/a Reset n/a
Watchdog exception n/a Reset n/a
CPU Reset (driven by the CPU STC) n/a Reset n/a
Software Reset n/a Reset n/a
External Reset n/a Reset n/a
(1) The Undefined Instruction TRAP is NOT detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage of the CPU.
(2) Oscillator fail/PLL slip can be configured in the system register (SYS.PLLCTL1) to generate a reset.

6.20 Digital Windowed Watchdog

This device includes a digital windowed watchdog (DWWD) module that protects against runaway code execution.

The DWWD module allows the application to configure the time window within which the DWWD module expects the application to service the watchdog. A watchdog violation occurs if the application services the watchdog outside of this window, or fails to service the watchdog at all. The application can choose to generate a system reset or a nonmaskable interrupt to the CPU in case of a watchdog violation.

The watchdog is disabled by default and must be enabled by the application. Once enabled, the watchdog can only be disabled upon a system reset.

6.21 Debug Subsystem

6.21.1 Block Diagram

The device contains an ICEPICK module to allow JTAG access to the scan chains (see Figure 6-21).

RM48L940 RM48L740 RM48L540 debug_subsystem_pns160.gifFigure 6-21 Debug Subsystem Block Diagram

NOTE

The ETM, RTP and DMM exist in silicon, but are not supported in the PGE package.

6.21.2 Debug Components Memory Map

Table 6-37 Debug Components Memory Map

MODULE NAME FRAME CHIP SELECT FRAME ADDRESS RANGE FRAME SIZE ACTUAL SIZE RESPONSE FOR ACCESS TO UNIMPLEMENTED LOCATIONS IN FRAME
START END
CoreSight Debug ROM CSCS0 0xFFA00000 0xFFA00FFF 4KB 4KB Reads: 0, writes: no effect
Cortex-R4F Debug CSCS1 0xFFA01000 0xFFA01FFF 4KB 4KB Reads: 0, writes: no effect
ETM-R4 CSCS2 0xFFA02000 0xFFA02FFF 4KB 4KB Reads: 0, writes: no effect
CoreSight TPIU CSCS3 0xFFA03000 0xFFA03FFF 4KB 4KB Reads: 0, writes: no effect

6.21.3 JTAG Identification Code

The JTAG ID code for this device is the same as the device ICEPick Identification Code (see Table 6-38).

Table 6-38 JTAG ID Code

SILICON REVISION ID
Rev A 0x0B8A002F
Rev B 0x2B8A002F
Rev C 0x3B8A002F
Rev D 0x4B8A002F

6.21.4 Debug ROM

The Debug ROM stores the location of the components on the Debug APB bus (see Table 6-39).

Table 6-39 Debug ROM table

ADDRESS DESCRIPTION VALUE
0x000 pointer to Cortex-R4F 0x00001003
0x001 ETM-R4 0x00002003
0x002 TPIU 0x00003003
0x003 POM 0x00004003
0x004 end of table 0x00000000

6.21.5 JTAG Scan Interface Timings

Table 6-40 JTAG Scan Interface Timing(1)

NO. PARAMETER MIN MAX UNIT
fTCK TCK frequency (at HCLKmax) 12 MHz
fRTCK RTCK frequency (at TCKmax and HCLKmax) 10 MHz
1 td(TCK -RTCK) Delay time, TCK to RTCK 24 ns
2 tsu(TDI/TMS - RTCKr) Setup time, TDI, TMS before RTCK rise (RTCKr) 26 ns
3 th(RTCKr -TDI/TMS) Hold time, TDI, TMS after RTCKr 0 ns
4 th(RTCKr -TDO) Hold time, TDO after RTCKf 0 ns
5 td(TCKf -TDO) Delay time, TDO valid after RTCK fall (RTCKf) 12 ns
(1) Timings for TDO are specified for a maximum of 50-pF load on TDO
RM48L940 RM48L740 RM48L540 jtag_timing_pns160.gifFigure 6-22 JTAG Timing

6.21.6 Advanced JTAG Security Module

This device includes an Advanced JTAG Security Module (AJSM) which provides maximum security to the memory content of the device by letting users secure the device after programming.

RM48L940 RM48L740 RM48L540 ajsm_unlock_pns160.gifFigure 6-23 AJSM Unlock

The device is unsecure by default by virtue of a 128-bit visible unlock code programmed in the OTP address 0xF0000000. The OTP contents are XOR-ed with the "Unlock By Scan" register contents (see Figure 6-23). The outputs of these XOR gates are again combined with a set of secret internal tie-offs. The output of this combinational logic is compared against a secret hard-wired 128-bit value. A match results in the UNLOCK signal being asserted, so that the device is now unsecure.

A user can secure the device by changing at least one bit in the visible unlock code from 1 to 0. Changing a 0 to 1 is not possible because the visible unlock code is stored in the One Time Programmable (OTP) flash region. Also, changing all the 128 bits to zeros is not a valid condition and will permanently secure the device.

Once secured, a user can unsecure the device by scanning an appropriate value into the "Unlock By Scan" register of the AJSM module. The value to be scanned is such that the XOR of the OTP contents and the Unlock-By-Scan register contents results in the original visible unlock code.

The Unlock-By-Scan register is reset only upon asserting power-on reset (nPORRST).

A secure device only permits JTAG accesses to the AJSM scan chain via the Secondary Tap # 2 of the ICEPick module. All other secondary taps, test taps and the boundary scan interface are not accessible in this state.

6.21.7 Embedded Trace Macrocell (ETM-R4)

The device contains a ETM-R4 module with a 32-bit internal data port. The ETM-R4 module is connected to a TPIU with a 32-bit data bus; the TPIU provides a 35-bit (32-bit data, 3-bit control) external interface for trace. The ETM-R4 is CoreSight compliant and follows the ETM v3 specification; for more details see ARM CoreSight ETM-R4 TRM specification.

6.21.7.1 ETM TRACECLKIN Selection

The ETM clock source can be selected as either VCLK or the external ETMTRACECLKIN pin. The selection is done by the EXTCTLOUT[1:0] control bits of the TPIU; the default is '00' (see Table 6-41). The address of this register is TPIU base address + 0x404.

Before you begin accessing TPIU registers, TPIU should be unlocked via coresight key and 1 or 2 should be written to this register.

Table 6-41 TPIU / TRACECLKIN Selection

EXTCTLOUT[1:0] TPIU/TRACECLKIN
00 [default] tied-zero
01 VCLK
10 ETMTRACECLKIN
11 tied-zero

6.21.7.2 Timing Specifications

RM48L940 RM48L740 RM48L540 etmtraceclkout_timing_pns160.gifFigure 6-24 ETMTRACECLKOUT Timing

Table 6-42 ETMTRACECLK Timing

PARAMETER MIN MAX UNIT
tcyc(ETM) Clock period t(HCLK) * 4 ns
tl(ETM) Low pulse width 20 ns
th(ETM) High pulse width 20 ns
tr(ETM) Clock and data rise time 3 ns
tf(ETM) Clock and data fall time 3 ns
RM48L940 RM48L740 RM48L540 etm.gifFigure 6-25 ETMDATA Timing

Table 6-43 ETMDATA Timing

PARAMETER MIN MAX UNIT
td(ETMTRACECLKH-ETMDATAV) Delay time, ETM trace clock high to ETM data valid 1.5 7 ns
td(ETMTRACECLKl-ETMDATAV) Delay time, ETM trace clock low to ETM data valid 1.5 7 ns

NOTE

The ETMTRACECLK and ETMDATA timing is based on a 15-pF load and for ambient temperature lower than 85°C.

6.21.8 RAM Trace Port (RTP)

The RTP provides the ability to datalog the RAM contents of the RM4x devices or accesses to peripherals without program intrusion. It can trace all data write or read accesses to internal RAM. In addition, it provides the capability to directly transfer data to a FIFO to support a CPU-controlled transmission of the data. The trace data is transmitted over a dedicated external interface.

6.21.8.1 Features

The RTP offers the following features:

  • Two modes of operation - Trace Mode and Direct Data Mode
    • Trace Mode
      • Nonintrusive data trace on write or read operation
      • Visibility of RAM content at any time on external capture hardware
      • Trace of peripheral accesses
      • 2 configurable trace regions for each RAM module to limit amount of data to be traced
      • FIFO to store data and address of data of multiple read/write operations
      • Trace of CPU and/or DMA accesses with indication of the master in the transmitted data packet
    • Direct Data Mode
      • Directly write data with the CPU or trace read operations to a FIFO, without transmitting header and address information
  • Dedicated synchronous interface to transmit data to external devices
  • Free-running clock generation or clock stop mode between transmissions
  • Up to 100 Mbps/pin transfer rate for transmitting data
  • Pins not used in functional mode can be used as GIOs

6.21.8.2 Timing Specifications

RM48L940 RM48L740 RM48L540 rtpclk_timing_pns160.gifFigure 6-26 RTPCLK Timing

Table 6-44 RTPCLK Timing

PARAMETER MIN MAX UNIT
tcyc(RTP) Clock period, prescaled from HCLK; must not be faster than HCLK / 2 11 (= 90 MHz) ns
th(RTP) High pulse width ((tcyc(RTP))/2) - ((tr+tf)/2) ns
tl(RTP) Low pulse width ((tcyc(RTP))/2) - ((tr+tf)/2) ns
RM48L940 RM48L740 RM48L540 rtp.gifFigure 6-27 RTPDATA Timing

Table 6-45 RTPDATA Timing

PARAMETER MIN MAX UNIT
td(RTPCLKH-RTPSYNCV) Delay time, RTPCLK high to RTPSYNC valid –5 4 ns
td(RTPCLKH-RTPDATAV) Delay time, RTPCLK high to RTPDATA valid –5 4 ns
RM48L940 RM48L740 RM48L540 rtp_nena_timing_pns160.gifFigure 6-28 RTPnENA Timing

Table 6-46 RTPnENA Timing

PARAMETER MIN MAX UNIT
tdis(RTP) time RTPnENA must go high before what would be the next RTPSYNC, to ensure delaying the next packet 3tc(HCLK) + tr(RTPSYNC) + 12 ns
tena(RTP) time after RTPnENA goes low before a packet that has been halted, resumes 4tc(HCLK) + tr(RTPSYNC) 5tc(HCLK) + tr(RTPSYNC) + 12 ns

6.21.9 Data Modification Module (DMM)

The Data Modification Module (DMM) provides the capability to modify data in the entire 4-GB address space of the RM4x devices from an external peripheral, with minimal interruption of the application.

6.21.9.1 Features

The DMM has the following features:

  • Acts as a bus master, thus enabling direct writes to the 4-GB address space without CPU intervention
  • Writes to memory locations specified in the received packet (leverages packets defined by trace mode of the RAM trace port (RTP) module
  • Writes received data to consecutive addresses, which are specified by the DMM (leverages packets defined by direct data mode of RTP module)
  • Configurable port width (1, 2, 4, 8, 16 pins)
  • Up to 100 Mbps/pin data rate
  • Unused pins configurable as GPIO pins

6.21.9.2 Timing Specifications

RM48L940 RM48L740 RM48L540 dmmclk_timing_pns160.gifFigure 6-29 DMMCLK Timing

Table 6-47 Timing Requirements for DMMCLK

MIN MAX UNIT
tcyc(DMM) Cycle time, DMMCLK period tc(HCLK) * 2 ns
th(DMM) Pulse duration, DMMCLK high ((tcyc(DMM))/2) - ((tr+tf)/2) ns
tl(DMM) Pulse duration, DMMCLK low ((tcyc(DMM))/2) - ((tr+tf)/2) ns
RM48L940 RM48L740 RM48L540 dmmdata_timing_pns160.gifFigure 6-30 DMMDATA Timing

Table 6-48 Timing Requirements for DMMDATA

MIN MAX UNIT
tssu(DMM) SYNC active to clk falling edge setup time 2 ns
tsh(DMM) clk falling edge to SYNC inactive hold time 3 ns
tdsu(DMM) DATA to clk falling edge setup time 2 ns
tdh(DMM) clk falling edge to DATA hold time 3 ns
RM48L940 RM48L740 RM48L540 dmm_nena_timing_pns160.gifFigure 6-31 DMMnENA Timing

Figure 6-31 shows a case with 1 DMM packet per 2 DMMCLK cycles (Mode = Direct Data Mode, data width = 8, port width = 4) where none of the packets received by the DMM are sent out, leading to filling up of the internal buffers. The DMMnENA signal is shown asserted, after the first two packets have been received and synchronized to the HCLK domain. Here, the DMM has the capacity to accept packets D4x, D5x, D6x, D7x. Packet D8 would result in an overflow. Once DMMnENA is asserted, the DMM expects to stop receiving packets after 4 HCLK cycles; once DMMnENA is deasserted, the DMM can handle packets immediately (after 0 HCLK cycles).

6.21.10 Boundary Scan Chain

The device supports IEEE1149.1-compliant boundary scan for testing pin-to-pin compatibility. The boundary scan chain is connected to the Boundary Scan Interface of the ICEPICK module (see Figure 6-32).

RM48L940 RM48L740 RM48L540 boundary_scan_implementation _pns160.gifFigure 6-32 Boundary Scan Implementation (Conceptual Diagram)

Data is serially shifted into all boundary-scan buffers through TDI and out through TDO.