SNVU860 april   2023 LP87523-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Sequencing
  5. 3Register Bits Loaded From OTP Memory

1 Introduction

This technical reference manual can be used as a reference for the LP875230D-Q1 default register bits after power up. This technical reference manual does not provide information about the electrical characteristics, external components, package, or the functionality of the device. For this information and the full register map, refer to the LP8752x-Q1 Four-Phase 10-A Buck Converter With Integrated Switches data sheet data sheet.

Table 1-1 provides the quick overview of each regulator default OTP settings. Section 2 provides an overview of default power up and power down sequence. Table 3-1 lists all the default OTP settings after power up.

Table 1-1 Main OTP Settings for regulators
DescriptionBit NameValue
Device identificationOTP configurationOTP_IDE4h
BUCK0+BUCK1 (2-phase operation)Output voltageBUCK0_VSET800 mV
Enable (ENx pin or I2C register write)EN_BUCK0, EN_PIN_CTRL0, BUCK0_EN_PIN_SELECTEN1 pin
Startup delayBUCK0_STARTUP_DELAY6 ms
Shutdown delayBUCK0_SHUTDOWN_DELAY0 ms
Force PWMBUCK0_FPWMForced PWM
Force multiphaseBUCK0_FPWM _MPForced multi-phase operation
Peak current limitILIM0, ILIM14.5 A
Maximum load currentN/A7 A
Slew rateN/A3.8 mV/us
BUCK2Output voltageBUCK2_VSET1200 mV
Enable (ENx pin or I2C register write)EN_BUCK2, EN_PIN_CTRL2, BUCK2_EN_PIN_SELECTEN1 pin
Startup delayBUCK2_STARTUP_DELAY4 ms
Shutdown delayBUCK2_SHUTDOWN_DELAY2 ms
Force PWMBUCK2_FPWMForced PWM
Peak current limitILIM23.0 A
Maximum load currentN/A2 A
Slew rateN/A3.8 mV/us

BUCK3

Output voltageBUCK3_VSET1800 mV
Enable (ENx pin or I2C register write)EN_BUCK3, EN_PIN_CTRL3, BUCK3_EN_PIN_SELECTEN1 pin
Startup delayBUCK3_STARTUP_DELAY2 ms
Shutdown delayBUCK3_SHUTDOWN_DELAY4 ms
Force PWMBUCK3_FPWMForced PWM
Peak current limitILIM32.0 A
Maximum load currentN/A1 A
Slew rateN/A3.8 mV/us
Spread spectrumEN_SPREAD_SPECENABLED
Switching frequencyN/A2 MHz
I2C addressN/A60h