SNAU319 August   2025 LMK3H2108

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1Configuration Overview
    1. 1.1 LMK3H2108 Configuration Information
  4. 2Device Register Map
  5. 3Device Registers
  6. 4Revision History

1.1 LMK3H2108 Configuration Information

Table 1-1 LMK3H2108 Frequency Configuration
OTP Page OUT0 (MHz) OUT1 (MHz) OUT2 (MHz) OUT3 (MHz) OUT4 (MHz) OUT5 (MHz) OUT6 (MHz) OUT7 (MHz)
OTP Page 0 100 100 100 100 100 100 100 100
OTP Page 1 100 100 100 100 100 100 100 100
OTP Page 2 100 100 100 100 100 100 100 100
OTP Page 3 100 100 100 100 100 100 100 100
Table 1-2 LMK3H2108 I2C Configuration
OTP Page I2C Configuration
OTP Page 0

I2C Address: 0x68

1 Byte Register Addressing
OTP Page 1

I2C Address: 0x68

1 Byte Register Addressing
OTP Page 2

I2C Address: 0x68

1 Byte Register Addressing
OTP Page 3

I2C Address: 0x68

1 Byte Register Addressing

OTP Page 0

Table 1-3 LMK3H2108 GPI Settings, OTP Page 0
GPI Pin Pin Behavior Polarity Internal Pull-Down Internal Pull-Up
GPI0 GPI Normal Disabled Disabled
GPI1 GPI Normal Disabled Disabled
GPI2 Group OE, OE_GROUP_2 Inverted Enabled Disabled
GPI3 Group OE, OE_GROUP_3 Inverted Enabled Disabled
GPI4 Group OE, OE_GROUP_4 Inverted Enabled Disabled
GPI5 Group OE, OE_GROUP_5 Inverted Enabled Disabled
Table 1-4 LMK3H2108 GPIO Settings, OTP Page 0
GPIO Pin Pin Behavior Polarity Internal Pull-Down Internal Pull-Up
GPIO0 Dynamic OTP Normal Enabled Disabled
GPIO1 Dynamic OTP Normal Enabled Disabled
GPIO2 Group OE, OE_GROUP_8 Inverted Enabled Disabled
GPIO3 Group OE, OE_GROUP_9 Inverted Enabled Disabled
GPIO4 Group OE, OE_GROUP_10 Inverted Enabled Disabled
Table 1-5 LMK3H2108 Input Settings, OTP Page 0
Input Powered Up/Down Input Format Input Termination
IN_0 Powered Down N/A (IN0 Unused) None, DC
IN_1 Powered Down N/A (IN1 Unused) None, DC
IN_2 Powered Down N/A (IN2 Unused) None, DC
Table 1-6 LMK3H2108 Output Settings, OTP Page 0
Output Frequency (MHz) Format Clock Source Output State OE Group SSC Behavior
OUT0 100 100 Ω LP-HCSL PATH1 Enabled No OE Group Disabled
OUT1 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_2 Disabled
OUT2 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_3 Disabled
OUT3 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_4 Disabled
OUT4 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_5 Disabled
OUT5 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_8 Disabled
OUT6 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_9 Disabled
OUT7 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_10 Disabled

OTP Page 1

Table 1-7 LMK3H2108 GPI Settings, OTP Page 1
GPI Pin Pin Behavior Polarity Internal Pull-Down Internal Pull-Up
GPI0 GPI Normal Disabled Disabled
GPI1 GPI Normal Disabled Disabled
GPI2 Group OE, OE_GROUP_2 Inverted Enabled Disabled
GPI3 Group OE, OE_GROUP_3 Inverted Enabled Disabled
GPI4 Group OE, OE_GROUP_4 Inverted Enabled Disabled
GPI5 Group OE, OE_GROUP_5 Inverted Enabled Disabled
Table 1-8 LMK3H2108 GPIO Settings, OTP Page 1
GPIO Pin Pin Behavior Polarity Internal Pull-Down Internal Pull-Up
GPIO0 Dynamic OTP Normal Enabled Disabled
GPIO1 Dynamic OTP Normal Enabled Disabled
GPIO2 Group OE, OE_GROUP_8 Inverted Enabled Disabled
GPIO3 Group OE, OE_GROUP_9 Inverted Enabled Disabled
GPIO4 Group OE, OE_GROUP_10 Inverted Enabled Disabled
Table 1-9 LMK3H2108 Input Settings, OTP Page 1
Input Powered Up/Down Input Format Input Termination
IN_0 Powered Down N/A (IN0 Unused) None, DC
IN_1 Powered Down N/A (IN1 Unused) None, DC
IN_2 Powered Down N/A (IN2 Unused) None, DC
Table 1-10 LMK3H2108 Output Settings, OTP Page 1
Output Frequency (MHz) Format Clock Source Output State OE Group SSC Behavior
OUT0 100 100 Ω LP-HCSL PATH1 Enabled No OE Group Enabled, -0.1% Down-spread
OUT1 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_2 Enabled, -0.1% Down-spread
OUT2 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_3 Enabled, -0.1% Down-spread
OUT3 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_4 Enabled, -0.1% Down-spread
OUT4 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_5 Enabled, -0.1% Down-spread
OUT5 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_8 Enabled, -0.1% Down-spread
OUT6 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_9 Enabled, -0.1% Down-spread
OUT7 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_10 Enabled, -0.1% Down-spread

OTP Page 2

Table 1-11 LMK3H2108 GPI Settings, OTP Page 2
GPI Pin Pin Behavior Polarity Internal Pull-Down Internal Pull-Up
GPI0 GPI Normal Disabled Disabled
GPI1 GPI Normal Disabled Disabled
GPI2 Group OE, OE_GROUP_2 Inverted Enabled Disabled
GPI3 Group OE, OE_GROUP_3 Inverted Enabled Disabled
GPI4 Group OE, OE_GROUP_4 Inverted Enabled Disabled
GPI5 Group OE, OE_GROUP_5 Inverted Enabled Disabled
Table 1-12 LMK3H2108 GPIO Settings, OTP Page 2
GPIO Pin Pin Behavior Polarity Internal Pull-Down Internal Pull-Up
GPIO0 Dynamic OTP Normal Enabled Disabled
GPIO1 Dynamic OTP Normal Enabled Disabled
GPIO2 Group OE, OE_GROUP_8 Inverted Enabled Disabled
GPIO3 Group OE, OE_GROUP_9 Inverted Enabled Disabled
GPIO4 Group OE, OE_GROUP_10 Inverted Enabled Disabled
Table 1-13 LMK3H2108 Input Settings, OTP Page 2
Input Powered Up/Down Input Format Input Termination
IN_0 Powered Down N/A (IN0 Unused) None, DC
IN_1 Powered Down N/A (IN1 Unused) None, DC
IN_2 Powered Down N/A (IN2 Unused) None, DC
Table 1-14 LMK3H2108 Output Settings, OTP Page 2
Output Frequency (MHz) Format Clock Source Output State OE Group SSC Behavior
OUT0 100 100 Ω LP-HCSL PATH1 Enabled No OE Group Enabled, -0.3% Down-spread
OUT1 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_2 Enabled, -0.3% Down-spread
OUT2 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_3 Enabled, -0.3% Down-spread
OUT3 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_4 Enabled, -0.3% Down-spread
OUT4 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_5 Enabled, -0.3% Down-spread
OUT5 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_8 Enabled, -0.3% Down-spread
OUT6 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_9 Enabled, -0.3% Down-spread
OUT7 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_10 Enabled, -0.3% Down-spread

OTP Page 3

Table 1-15 LMK3H2108 GPI Settings, OTP Page 3
GPI Pin Pin Behavior Polarity Internal Pull-Down Internal Pull-Up
GPI0 GPI Normal Disabled Disabled
GPI1 GPI Normal Disabled Disabled
GPI2 Group OE, OE_GROUP_2 Inverted Enabled Disabled
GPI3 Group OE, OE_GROUP_3 Inverted Enabled Disabled
GPI4 Group OE, OE_GROUP_4 Inverted Enabled Disabled
GPI5 Group OE, OE_GROUP_5 Inverted Enabled Disabled
Table 1-16 LMK3H2108 GPIO Settings, OTP Page 3
GPIO Pin Pin Behavior Polarity Internal Pull-Down Internal Pull-Up
GPIO0 Dynamic OTP Normal Enabled Disabled
GPIO1 Dynamic OTP Normal Enabled Disabled
GPIO2 Group OE, OE_GROUP_8 Inverted Enabled Disabled
GPIO3 Group OE, OE_GROUP_9 Inverted Enabled Disabled
GPIO4 Group OE, OE_GROUP_10 Inverted Enabled Disabled
Table 1-17 LMK3H2108 Input Settings, OTP Page 3
Input Powered Up/Down Input Format Input Termination
IN_0 Powered Down N/A (IN0 Unused) None, DC
IN_1 Powered Down N/A (IN1 Unused) None, DC
IN_2 Powered Down N/A (IN2 Unused) None, DC
Table 1-18 LMK3H2108 Output Settings, OTP Page 3
Output Frequency (MHz) Format Clock Source Output State OE Group SSC Behavior
OUT0 100 100 Ω LP-HCSL PATH1 Enabled No OE Group Enabled, -0.5% Down-spread
OUT1 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_2 Enabled, -0.5% Down-spread
OUT2 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_3 Enabled, -0.5% Down-spread
OUT3 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_4 Enabled, -0.5% Down-spread
OUT4 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_5 Enabled, -0.5% Down-spread
OUT5 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_8 Enabled, -0.5% Down-spread
OUT6 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_9 Enabled, -0.5% Down-spread
OUT7 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_10 Enabled, -0.5% Down-spread