SNAU266A July   2021  – August 2022

 

  1.   Abstract
  2. 1First-Time Setup
    1. 1.1 Evaluation Module Contents
    2. 1.2 Evaluation Setup Requirements
  3. 2EVM Connections
    1. 2.1 Connection Diagram
    2. 2.2 Power Supply
    3. 2.3 Reference Clock
    4. 2.4 Output Connections
    5. 2.5 Programming Interface
  4. 3Feature Evaluation
    1. 3.1 Buffer, Divider, and Multiplier Modes
    2. 3.2 SYSREF Generation
    3. 3.3 SYSREF Delay Generators
  5. 4Schematic
  6. 5PCB Layout and Layer Stack-Up
    1. 5.1 PCB Layer Stack-Up
    2. 5.2 PCB Layout
  7. 6Bill of Materials
  8.   A Troubleshooting
  9.   B USB2ANY Firmware Upgrade
  10.   C Revision History

Reference Clock

Connect the CLKINP SMA connector to a high-quality signal source such as an SMA100B signal generator. Both CLKIN inputs are terminated internally with 50 Ω to AC-GND (that is, GND connection is formed by an internal capacitor), so no external termination is required or recommended. The other CLKINN SMA connector may be optionally installed beforehand so the input can be driven differentially, provided a suitable balun or differential clock source is available.

The default EVM profile configures the device to evaluate the buffer, multiplier, and divider modes with an 800-MHz CLKIN. This frequency can be modified per the operating range of each functional element if desired. This EVM setup guide and related plots assume 6000-MHz CLKIN for buffer mode and divider mode & 3000-MHz CLKIN for multiplier mode.

If a suitable input source is available, connect the SYSREF input SMAs to a differential output source such as an arbitrary function generator. The EVM connections for the SYSREF input are DC-coupled and provide internal 100-Ω termination with several biasing options. At POR, the EVM automatically applies a weak 1.3-V common mode bias to the SYSREFREQ pins. However, the default EVM profile configures the SYSREF input for DC-coupled input. In DC-coupled mode, the common mode bias on the SYSREFREQ pins must be between 1 V and 2 V. The input common mode requirements can be fulfilled with a standard LVDS output buffer.

For evaluating SYNC mode and SYSREF windowing, it is critical to have a SYSREFREQ input source capable of consistently meeting setup and hold requirements for a single cycle of the input clock. This can become very challenging at higher frequencies where setup and hold requirements can be < 50 ps. Another device capable of picosecond-precision timed pulses, such as LMX2820 or LMX2594, could be used as a reference input to both CLKIN and SYSREF for evaluating these features.