6 Settling time

A wide bandwidth amplifier with a high slew rate, low output impedance and high phase margin settles faster. When driving the ADC, select an op amp with a settling time to the required resolution that matches the ADC acquisition time. Remember that the acquisition time is the sampling time minus the conversion time. Slowing the sampling rate down helps you relax the op-amp settling-time requirement.

Ideally, the op amp should settle within one-half LSB of the ADC to avoid errors. However, very few op-amp datasheets specify settling time up to 16 bits (0.0015%). One often-overlooked specification is the open-loop output impedance. A low open-loop output impedance means a higher phase margin, which in turn means a faster settling time. Furthermore, the shape of the open-loop output impedance affects circuit stability. A flat (resistive) open-loop output impedance op amp is much easier to compensate. A charge bucket resistor-capacitor filter at the output of the op amp creates a pole and degrades the phase margin but minimizes output voltage droop during the sampling time. Depending on the pole location, you may see excessive ringing (overshoot), which affects the settling time.

Figure 8 shows a circuit using the OPA328 to drive the ADS8860. The sampling rate is set at 500kSPS. The acquisition period of the ADS8860 is Tacq = 2µs – 710ns = 1,290ns.

Lowering the sampling rate to 500kSPS allows the circuit to settle much faster at 425ns, well below one-half LSB.

Figure 9 shows the OPA328 paired to the ADS8860 and uses the circuit to simulate the settling time (Figure 10).