SLVSJM6 November   2025 MSPM0G5187

 

  1.   1
  2.   Abstract
  3. 1Functional Advisories
  4. 2Preprogrammed Software Advisories
  5. 3Debug Only Advisories
  6. 4Fixed by Compiler Advisories
  7. 5Device Nomenclature
    1. 5.1 Device Symbolization and Revision Identification
  8. 6Advisory Descriptions
    1. 6.1  AES_ERR_01
    2. 6.2  CPU_ERR_02
    3. 6.3  CPU_ERR_03
    4. 6.4  FLASH_ERR_03
    5. 6.5  FLASH_ERR_04
    6. 6.6  FLASH_ERR_05
    7. 6.7  FLASH_ERR_08
    8. 6.8  GPIO_ERR_05
    9. 6.9  GPIO_ERR_06
    10. 6.10 KEYSTORE_ERR_01
    11. 6.11 PMCU_ERR_13
    12. 6.12 RST_ERR_01
    13. 6.13 SYSCTL_ERR_01
    14. 6.14 SYSCTL_ERR_02
    15. 6.15 SYSCTL_ERR_03
    16. 6.16 SYSCTL_ERR_04
    17. 6.17 SYSOSC_ERR_01
    18. 6.18 SYSOSC_ERR_02
    19. 6.19 SYSPLL_ERR_01
    20. 6.20 TIMER_ERR_04
    21. 6.21 TIMER_ERR_06
    22. 6.22 TIMER_ERR_07
    23. 6.23 UNICOMMI2CC_ERR_01
    24. 6.24 UNICOMMI2CT_ERR_01
    25. 6.25 UNICOMMI2CT_ERR_02
    26. 6.26 UNICOMMI2CT_ERR_03
    27. 6.27 UNICOMMSPI_ERR_01
    28. 6.28 UNICOMMUART_ERR_01
    29. 6.29 UNICOMMUART_ERR_02
    30. 6.30 UNICOMMUART_ERR_03
    31. 6.31 UNICOMMUART_ERR_04
    32. 6.32 UNICOMMUART_ERR_05
    33. 6.33 UNICOMMUART_ERR_06
    34. 6.34 UNICOMMUART_ERR_07
    35. 6.35 UNICOMMUART_ERR_08
    36. 6.36 UNICOMMUART_ERR_09
    37. 6.37 UNICOMMUART_ERR_10
    38. 6.38 UNICOMMUART_ERR_11
  9. 7Trademarks
  10. 8Revision History

6.19 SYSPLL_ERR_01

SYSPLL Module

Category

Functional

Function

SYSPLL Frequency may not lock to correct frequency when enabled.

Description

When setting the SYSPLLEN bit to 1 in SYSCTL HSCLKEN register, the SYSPLL will run the phase locked loop search. The search can potentially fail where the frequency will not be set to the correct value, instead the resultant frequency will be drastically different than the configured frequency.

Workaround

Check the frequency output of the SYSPLL using the Frequency Clock Counter (FCC) anytime the SYSPLLEN bit is set to 1. Once the frequency is correct it will maintain the correct value until disabled and reenabled (SYSPLLEN set to 0 then 1), once reenabled the PLL will re-run the search and the SYSPLL output will need to be rechecked.

Workaround 1: Set FCC with SYSPLLCLK0 as the CLK input and LFCLK as the Trigger source. Run the FCC and check the value for the configured SYSPLL frequency with reference to the LFCLK; for example, with SYSPLL = 80MHz and LFCLK = 32kHz, the resultant FCC count should be 80,000,000/32,768= ~2441. The count will vary depending on the combined clock accuracies, so it is recommended to add a +-5% to allowed range. Estimated time for FCC is 30us.

FCC Settings: SYSCTL.GENCLKCFG.FCCTRIGCNT = 0, SYSCTL.GENCLKCFG.FCCTRIGSRC = 1, SYSCTL.GENCLKCFG.FCCSELCLK = 4;

If the FCC value is incorrect, disable and reenable the SYSPLL by setting SYSPLLEN to 0 then 1. Rerun the FCC check.

Workaround 2: Output SYSOSC/2 from the CLK_OUT pin and route the signal into FCC_IN. Use the SYSPLLCLK0 as the FCC CLK and the FCC_IN  for the trigger source. Run the FCC for 16 Clock cycles, and check the value for the configured SYSPLL frequency with reference to the SYSOSC; for example, with SYSPLL = 80MHz and SYSOSC/2 = 16MHz, the resultant FCC count should be 80,000,000/16,000,000 * 16  = ~80. The count will vary depending on the combined clock accuracies, so it is recommended to add a +-5% to allowed range. Estimated time for FCC is 1us.

FCC Settings: SYSCTL.GENCLKCFG.FCCTRIGCNT = 0x0F, SYSCTL.GENCLKCFG.FCCTRIGSRC = 0, SYSCTL.GENCLKCFG.FCCSELCLK = 4;

If the FCC value is incorrect, disable and reenable the SYSPLL by setting SYSPLLEN to 0 then 1. Rerun the FCC check.