SLVSJM6 November 2025 MSPM0G5187
UNICOMMI2CC Module
Functional
Polling the I2C BUSY bit might not guarantee that the controller transfer has completed
After setting the BUSRTRUN/FRAME_START bit to initiate an I2C controller transfer, it takes approximately 2 I2C functional clock cycles for the BUSY status to be asserted. If polling for the BUSY bit is used immediately after setting BUSRTRUN/FRAME_START to wait for transfer completion, the BUSY status might be checked before it is set. This problem is more likely to occur with high CLKDIV values (resulting in a slower I2C functional clock) or under higher compiler optimization levels.
Add software delay before polling BUSY status. Software delay = 3 x I2C functional clock = 3 x clock_divider x (CPU_CLK / selected clock source frequency) For example, with a clock_divider of 8, a clock source of 4 MHz(MFCLK), and CPU_CLK of 32 MHz: Software delay = 3 x 8 x (32 MHz / 4 MHz)= 192 CPU cycles