TPS548C26EVM 4-V to 16-V, 35-A Step-Down Converter Evaluation Module
- SLUUCG4 November 2022 TPS548C26

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EVM USER'S GUIDE

TPS548C26EVM 4-V to 16-V, 35-A Step-Down Converter Evaluation Module

Abstract

This user’s guide contains information for the TPS548C26EVM evaluation module (BSR152) as well as for the TPS548C26 DC/DC converter. This user's guide also includes performance specifications, schematic, layout, and bill of materials for the TPS548C26EVM.

Trademarks

D-CAP+™ is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

1 Introduction

1.1 Description

The TPS548C26EVM is an evaluation module for the TPS548C26 DC/DC synchronous buck converter. The evaluation module accepts an 8-V to 16-V input and can deliver an output current up to 35 A. The converter uses D-CAP+™ control scheme for fast transient response, using less output capacitance to save board space. Rated input voltage and output current range for the evaluation module are given in Table 1-1. Figure 1-1 highlights the user interface items associated with the EVM.

The high-side and low-side MOSFETs are incorporated inside the package along with the gate-drive circuitry. The low drain-to-source on-resistance of the MOSFET allows the to achieve high efficiencies and helps keep the junction temperature low at the rated output current. Fixed frequency advanced current mode control allows you to synchronize the regulators to an external clock source. An external divider allows for an adjustable output voltage. The FSEL and MODE pins provide selectable switching frequency, soft-start time, current limit, and internal compensation. Lastly, the TPS548C26 includes an enable pin and a power-good output which can be used for sequencing multiple regulators.

Table 1-1 Input Voltage and Output Current Summary

EVM	INPUT VOLTAGE RANGE	OUTPUT CURRENT RANGE
TPS548C26EVM	8 V to 16 V	0 A to 35 A

Figure 1-1 EVM User Interface

1.2 Before You Begin

The following warnings and cautions are noted for the safety of anyone using or working close to the TPS548C26EVM. Observe all safety precautions.

Warning

The TPS548C26EVM can become hot during operation due to dissipation of power in some operating conditions. Avoid contact with the board. Follow all applicable safety procedures applicable to your laboratory.

WARNING:

The circuit module has signal traces, components, and component leads on the bottom of the board. This can result in exposed voltages, hot surfaces or sharp edges. Do not reach under the board during operation.

CAUTION:

Some power supplies can be damaged by application of external voltages. If using more than 1 power supply, check your equipment requirements and use blocking diodes or other isolation techniques, as needed, to prevent damage to your equipment.

2 Performance Characteristics

Table 2-1 provides a summary of the TPS548C26EVM performance characteristics. The TPS548C26EVM is designed and tested for V_IN = 8 V to 16 V. Characteristics are given for an input voltage of V_IN = 12 V and output voltage of 3.3 V, unless otherwise specified. The ambient temperature is room temperature (20°C to 25°C) for all measurements, unless otherwise noted.

Table 2-1 TPS548C26EVM Performance Characteristics Summary

SPECIFICATION	TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IN voltage range		8	12	16	V
PVIN input current	PVIN = 12 V, internal VCC/VDRV, I_O = 0 A, Pulse-skip mode		15		mA
VCC/VDRV input current	External 5-V bias, f_SW = 800 kHz, PVIN = 12 V, I_O = 35 A		38		mA
Output voltage setpoint			3.3		V
Output current range	V_IN = 8 V to 16 V	0		35	A
Output ripple voltage	f_SW = 800 kHz, I_O = 35 A		28		mVPP
Output rise time			1		ms
Current limit	Set by J10		35		A
Switching frequency (f_SW)	Set by J11	600	800	1200	kHz
Efficiency	V_IN = 12 V, external 5-V bias, f_SW = 800 kHz, I_O = 35 A		91		%
IC case temperature	V_IN = 12 V, external 5-V bias, f_SW = 1.2 MHz, I_O = 35 A, 15-minute dwell time		103		°C

Figure 2-1 Efficiency, FCCM, Internal LDO

Figure 2-3 Efficiency, FCCM, External 5-V Bias

Figure 2-5 Efficiency, DCM. Internal LDO

Figure 2-7 Efficiency, DCM, External 5-V Bias

Figure 2-9 Load Regulation, FCCM, Internal LDO

Figure 2-11 Load Regulation, DCM, Internal VCC LDO

Figure 2-13 ENABLE Start-Up Waveform

Figure 2-15 Output Voltage Ripple, 800-kHz FCCM, 35-A Load

Figure 2-17 Output Voltage Ripple, DCM, No Load

Figure 2-19 Thermal Characteristics, 600-kHz FCCM, Internal LDO, 35-A Load

Figure 2-21 Thermal Characteristics, 800-kHz FCCM, Internal LDO, 35-A Load

Figure 2-23 Thermal Characteristics, 1.2-MHz FCCM, Internal LDO, 35-A Load

Figure 2-2 Power Dissipation, FCCM, Internal LDO

Figure 2-4 Power Dissipation, FCCM, External 5-V Bias

Figure 2-6 Power Dissipation, DCM, Internal LDO

Figure 2-8 Power Dissipation, DCM, External 5-V Bias

Figure 2-10 Load Regulation, FCCM, External 5-V Bias

Figure 2-12 Load Regulation, DCM, External 5-V Bias

Figure 2-14 ENABLE Shutdown Waveform

Figure 2-16 Output Voltage Ripple, 800-kHz FCCM, No Load

Figure 2-18 Output Voltage Ripple, DCM, 1-A Load

Figure 2-20 Thermal Characteristics, 600-kHz FCCM, External 5-V Bias, 35-A Load

Figure 2-22 Thermal Characteristics, 800-kHz FCCM, External 5-V Bias, 35-A Load

Figure 2-24 Thermal Characteristics, 1.2-MHz FCCM, External 5-V Bias, 35-A Load

3 Test Point Descriptions

A description of each test point follows:

Table 3-1 Connectors and Jumpers

REFERENCE DESIGNATOR	NAME	FUNCTION
J1	VOUT	Output voltage scope monitor
J2	IEXT	Load current interface for the input power telemetry
J3	PVIN	VIN screw terminal to connect input voltage (see Table 1-1 for V_IN range)
J4	VOUT	VOUT screw terminal to connect load to output
J5	EXTBIAS	Monitors internal LDO voltage or override internal LDO with external bias for improving efficiency
J6	BIASSEL	Pin header to select PVIN or an external VCC.
J7, J12	RED/+	Connector blocks to interface with Mini Slammer
J8	EN_ON	2-pin header for enable. Add shunt to connect EN to PVIN and enable device. Remove shunt to disable device.
J9	PGND	Power ground test point
J10	ILIM	Pin header block to select current limit.
J11	MODE	Pin header block to select switching mode and switching frequency.
J14	IIN_EXT	Screw terminal to apply an external voltage source for input power telemetry.
J15	ADDR/SS	Pin header block to select soft-start time
J16	PG_PULLUP	PGOOD pullup pin. 2-pin header to pull up PGOOD to VCC.

Table 3-2 Test Points

COLOR REFERNCE	NAME	FUNCTION
Red	PVIN_SNS	Positive side of input voltage sensing point
Red	EN	Monitors enable pin
Red	VCCIO	External 1-V pullup for SVID
Red	BOOT	Monitors the bootstrap capacitor voltage
Red	VINSENP/AVIN	Positive voltage of the power sense resistor on the input power telemetry
Red	VO_EFF	Excellent output voltage sense point to measure efficiency
Red	VO_REG	Monitors the output voltage
Red	SW	Monitors output switching terminal of the power converter
Red	VINSENM/VCC	Voltage reference point of the power sense resistor on the input power telemetry
Red	EXTBIAS	Monitors the voltage on EXBIAS
Red	VCC/VDRV	Monitors the voltage on VCC/VDRV
Red	PG	Monitors the power good signal
White	BODE-CH1	Inject frequency from the frequency response analyzer
White	BODE-CH2	Measurement point of the receiving end from the frequency response analyzer
Black	PGND_SNS	Reference side of input voltage sensing point
Black	GOSNS	Remote sense reference for PGND
Black	GND	Power ground test point
Black	AGND	Analog ground test point
Black	PGND_EFF	Excellent output voltage reference sense point to measure efficiency
Black	GND_REG	Output voltage PGND sense point
TP1	VOUT	Monitors output voltage
TP2	SW	Monitors output switching terminal of the power converter
TP19	EN	Monitors enable pin
TP25	IIN_EXT S+	Remote sense for the bias voltage used to supply the input power telemetry
TP26	IIN_EXT S-	Negative remote sense for the input power telemetry
TP27	VOSNS	Output voltage sense point for internal compensation circuitry

4 Test Setup

A power supply capable of providing 10 A or greater must be connected to J3 (PVIN) through a pair of 14-AWG wires or better. The PVIN test points, PVIN_SNS and PGND_SNS, provide a place to monitor the PVIN input voltage. Do not use these monitoring test points as the input supply connection points. The PCB traces connecting to these test points are not designed to support high currents.
The load must be connected to J4 (VOUT) with a pair of 10-AWG wires or better. Wire lengths must be minimized to reduce losses in the wires. If there is too much voltage drops in the wires, then the electronic load can not be able to sink the full rated current. The VO_REG test point is used to monitor the output voltage with GND_REG as the ground reference.
Ensure that J8 is populated so that the part is enabled.
Populate J6 to the correct bias selection - PVIN or EXT.
When testing with an external 5-V bias supply to power VCC/VDRV, connect the external supply to J5 (EXTBIAS) with a pair of 20-AWG wires or better.
To test the VINSENP function, connect a load to J2 (IEXT) with a pair of 14-AWG wires or better. When testing this function, the PVIN power supply must be capable of sourcing this additional external load current. Additionally, the load must have the proper voltage and power rating. For example, when the voltage at PVIN is 12 V and if pulling 20 A out of J2, the power supply must also source an additional 20 A and the load must have a power rating of at least 240 W.
If modifications are made to the TPS548C26EVM, the input current can change. The input power supply and wires connecting the EVM to the power supply must be rated for the input current.

5 Configurations

All Jumper selections must be made prior to applying power to the EVM. Configure this EVM using the following configuration selections.