SLUSAB0D October   2010  – April 2016 BQ24153A , BQ24156A , BQ24158 , BQ24159

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Device Comparisons
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Input Voltage Protection
        1. 9.3.1.1 Input Overvoltage Protection
        2. 9.3.1.2 Bad Adaptor Detection/Rejection
        3. 9.3.1.3 Sleep Mode
        4. 9.3.1.4 Input Voltage Based DPM (Special Charger Voltage Threshold)
      2. 9.3.2 Battery Protection
        1. 9.3.2.1 Output Overvoltage Protection
        2. 9.3.2.2 Battery Short Protection
        3. 9.3.2.3 Battery Detection at Power Up in 15-minute Mode (bq24153A/6A only)
        4. 9.3.2.4 Battery Detection in Host Mode
      3. 9.3.3 15-Minute Safety Timer and 32-second Watchdog Timer in Charge Mode
      4. 9.3.4 USB Friendly Power Up
      5. 9.3.5 Input Current Limiting at Power Up
    4. 9.4 Device Functional Modes
      1. 9.4.1 Charge Mode Operation
        1. 9.4.1.1 Charge Profile
      2. 9.4.2 PWM Controller in Charge Mode
      3. 9.4.3 Battery Charging Process
      4. 9.4.4 Thermal Regulation and Protection
      5. 9.4.5 Charge Status Output, STAT Pin
      6. 9.4.6 Control Bits in Charge Mode
        1. 9.4.6.1 CE Bit (Charge Mode)
        2. 9.4.6.2 RESET Bit
        3. 9.4.6.3 OPA_Mode Bit
      7. 9.4.7 Control Pins in Charge Mode
        1. 9.4.7.1 CD Pin (Charge Disable)
        2. 9.4.7.2 SLRST Pin (Safety Limit Register 06H Reset, bq24156A/9 only)
      8. 9.4.8 BOOST Mode Operation (bq24153A/8 only)
        1. 9.4.8.1 PWM Controller in Boost Mode
        2. 9.4.8.2 Boost Start Up
        3. 9.4.8.3 PFM Mode at Light Load
        4. 9.4.8.4 Safety Timer in Boost Mode
        5. 9.4.8.5 Protection in Boost Mode
          1. 9.4.8.5.1 Output Overvoltage Protection
          2. 9.4.8.5.2 Output Overload Protection
          3. 9.4.8.5.3 Battery Overvoltage Protection
        6. 9.4.8.6 STAT Pin in Boost Mode
      9. 9.4.9 High Impedance (HI-Z) Mode
    5. 9.5 Programming
      1. 9.5.1 Serial Interface Description
        1. 9.5.1.1 F/S Mode Protocol
        2. 9.5.1.2 H/S Mode Protocol
        3. 9.5.1.3 I2C Update Sequence
        4. 9.5.1.4 Slave Address Byte
        5. 9.5.1.5 Register Address Byte
    6. 9.6 Register Maps
      1. 9.6.1 Status/Control Register [Memory Location: 00, Reset State: x1xx 0xxx]
      2. 9.6.2 Control Register [Memory Location: 01, Reset State: 0011 0000]
      3. 9.6.3 Control/Battery Voltage Register [Memory Location: 02, Reset State: 0000 1010]
      4. 9.6.4 Vender/Part/Revision Register [Memory Location: 03, Reset State: 0101 000x]
      5. 9.6.5 Battery Termination/Fast Charge Current Register [Memory Location: 04, Reset State: 0000 000]
      6. 9.6.6 Special Charger Voltage/Enable Pin Status Register [Memory location: 05, Reset state: 001X X100]
      7. 9.6.7 Safety Limit Register [Memory location: 06, Reset state: 01000000]
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Systems Design Specifications
        2. 10.2.2.2 Charge Current Sensing Resistor Selection Guidelines
        3. 10.2.2.3 Output Inductor and Capacitance Selection Guidelines
      3. 10.2.3 Application Curves
    3. 10.3 System Example
  11. 11Power Supply Recommendations
    1. 11.1 System Load After Sensing Resistor
    2. 11.2 System Load Before Sensing Resistor
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Current Path
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Third-Party Products Disclaimer
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Package Summary
      1. 14.1.1 Chip Scale Packaging Dimensions

9 Detailed Description

9.1 Overview

For a current restricted power source, such as a USB host or hub, a high efficiency converter is critical to fully use the input power capacity for quickly charging the battery. Due to the high efficiency for a wide range of input voltages and battery voltages, the switch mode charger is a good choice for high speed charging with less power loss and better thermal management than a linear charger.

The bq24153A/8/9 are highly integrated synchronous switch-mode chargers, featuring integrated FETs and small external components, targeted at extremely space-limited portable applications powered by 1-cell Li-Ion or Li-polymer battery pack. Furthermore, bq24153A/8 also has bi-directional operation to achieve boost function for USB OTG support.

The bq24153A/8 have three operation modes: charge mode, boost mode, and high impedance mode, while the bq24156A/9 only has charge mode and high impedance mode. In charge mode, the IC supports a precision Li-ion or Li-polymer charging system for single-cell applications. In boost mode, the IC boosts the battery voltage to VBUS for powering attached OTG devices. In high impedance mode, the IC stops charging or boosting and operates in a mode with very low current from VBUS or battery, to effectively reduce the power consumption when the portable device is in standby mode. Through I2C communication with a host, referred to as "HOST or 32-second" control/mode, the IC achieves smooth transition among the different operation modes. Even when no I2C communication is available, the IC starts a 15 minute saftey timer and enters "15-minute" (default) mode. During 15-minute operation, the charger will still charge the battery but using each register's default values.

9.2 Functional Block Diagram

bq24153A bq24156A bq24158 bq24159 fbd_chg2_lusab0.gif Figure 13. Function Block Diagram of bq2415x in Charge Mode
bq24153A bq24156A bq24158 bq24159 fbd_1538_boost2_lusab0.gif Figure 14. Function Block Diagram of bq2415x in Boost Mode

9.3 Feature Description

9.3.1 Input Voltage Protection

9.3.1.1 Input Overvoltage Protection

The IC provides a built-in input overvoltage protection to protect the device and other components against damage if the input voltage (Voltage from VBUS to PGND) goes too high. When an input overvoltage condition is detected, the IC turns off the PWM converter, sets fault status bits, and sends out a fault pulse from the STAT pin. Once VBUS drops below the input overvoltage exit threshold, the fault is cleared and charge process resumes.

9.3.1.2 Bad Adaptor Detection/Rejection

Although not shown in Figure 26, at power-on-reset (POR) of VBUS, the IC performs the bad adaptor detection by applying a current sink to VBUS. If the VBUS is higher than VIN(MIN) for 30ms, the adaptor is good and the charge process begins. Otherwise, if the VBUS drops below VIN(MIN), a bad adaptor is detected. Then, the IC disables the current sink, sends a send fault pulse in FAULT pin and sets the bad adaptor flag (B2 - B0 = 011 for Register 00H). After a delay of TINT, the IC repeats the adaptor detection process, as shown in Figure 15 and Figure 16.

bq24153A bq24156A bq24158 bq24159 adap_det_lusa27.gif Figure 15. Bad Adaptor Detection Circuit
bq24153A bq24156A bq24158 bq24159 adap_flo_lusa27.gif Figure 16. Bad Adaptor Detection Scheme Flow Chart

9.3.1.3 Sleep Mode

The IC enters the low-power sleep mode if the VBUS pin voltage falls below the sleep-mode entry threshold, VCSOUT+VSLP, and VBUS is higher than the bad adaptor detection threshold, VIN(MIN). This feature prevents draining the battery during the absence of VBUS. During sleep mode, both the reverse blocking switch Q1 and PWM are turned off.

9.3.1.4 Input Voltage Based DPM (Special Charger Voltage Threshold)

During the charging process, if the input power source is not able to support the programmed or default charging current, the VBUS voltage will decrease. Once the VBUS drops to VIN_DPM (default 4.52V), the charge current begins to taper down to prevent any further drop of VBUS. When the IC enters this mode, the charge current is lower than the set value and the special charger bit is set (B4 in Register 05H). This feature makes the IC compatible with adapters having different current capabilities.

9.3.2 Battery Protection

9.3.2.1 Output Overvoltage Protection

The IC provides a built-in overvoltage protection to protect the device and other components against damage if the battery voltage goes too high, as when the battery is suddenly removed. When an overvoltage condition is detected, the IC turns off the PWM converter, sets fault status bits, and sends out a fault pulse from the STAT pin. Once V(CSOUT) drops to the battery overvoltage exit threshold, the fault is cleared and charge process resumes.

9.3.2.2 Battery Short Protection

During the normal charging process, if the battery voltage is lower than the short-circuit threshold, VSHORT, the charger operates in short circuit mode with a lower charge rate of ISHORT.

9.3.2.3 Battery Detection at Power Up in 15-minute Mode (bq24153A/6A only)

bq24153A/6A also have a unique battery detection scheme during the start up of the charger. At VBUS power up, if the timer is in 15-minute mode, bq24153A/6A will start a 262ms timer when exiting from short circuit mode to PWM charge mode. If the battery voltage is charged above the recharge threshold (VOREG-VRCH) when the 262ms timer expired, bq2153A/6A will not consider the battery present; then stop charging, and go to high impedance mode immediately. However, if the battery voltage is still below the recharge threshold when the 262ms timer expires, the charging process will continue as normal battery charging process.

bq24158/9 simply begin regulating the output voltage to their default values (3.54V) at power up while in 15-minute mode.

9.3.2.4 Battery Detection in Host Mode

For applications with removable battery packs, the IC provides a battery absent detection scheme to reliably detect insertion or removal of battery packs.

During the normal charging process with host control, once the voltage at the CSOUT pin is above the battery recharge threshold, VOREG - VRCH, and the termination charge current is detected, the IC turns off the PWM charge and enables a discharge current, IDETECT, for a period of tDETECT, (262 ms typical) then checks the battery voltage. If the battery voltage is still above the recharge threshold after tDETECT, the battery is present. On the other hand, if the battery voltage is below the battery recharge threshold, the battery is absent. Under this condition, the charge parameters (such as input current limit) are reset to the default values and charge resumes after a delay of TINT. This function ensures that the charge parameters are reset whenever the battery is replaced.

9.3.3 15-Minute Safety Timer and 32-second Watchdog Timer in Charge Mode

Once a good adapter and good battery are attached, the IC starts the 15-minute saftey timer (t15min) that can be disabled by any write-action performed by host through I2C interface. Once the 15-minute timer is disabled, a 32-second watchdog timer (t32sec) is automatically started. The 32-second timer can be reset by the host using I2C interface. Writing “1” to reset the TMR_RST bit in the control register will reset the 32-second timer and TMR_RST is automatically set to “0” after the 32-second timer is reset. If the 32-second timer expires, the charge is terminated and charge parameters are reset to default values. Then the 15-minute timer starts and the charge resumes in 15-minute mode.

During normal charging process, the IC is usually in 32-second mode with host control and 15-minute mode without host control using I2C interface. The above process repeats until the battery is fully charged. If the 15-minute timer expires, the IC turns off the charge, enunciates FAULT on the STATx bits of status register, and sends the 128μs interrupt pulse. This function prevents battery over charge if the host fails to reset the safety timer. The 15-minute charge, with default parameters, allows time for a discharged battery to charge sufficiently to be able to power the host and start communication. The safety timer flow chart is shown in Figure 17. Fault condition is cleared by POR and fault status bits can only be updated after the status bits are read by the host.

bq24153A bq24156A bq24158 bq24159 tim_flo_lusa27.gif Figure 17. Timer Flow Chart for bq24153A/6A/8/9

9.3.4 USB Friendly Power Up

Prior to POR, if the host continues to write the TMR_RST bit to 1, to stay in 32-second mode, then at POR, the charger enters normal charge mode (using the desired control bits). If not in 32-second mode at POR, the charge will operate with default bit values, in 15 minute mode, until the host updates the control registers.

If the battery voltage is above the VLOWV threshold while in 15 minute mode, the charger will be in the high impedance state.  The default control bits set the charging current and regulation voltage low as a safety feature to avoid violating USB spec and over-charging any of the Li-Ion chemistries, while the host has lost communication.  The input current limiting is described below.

9.3.5 Input Current Limiting at Power Up

The input current sensing circuit and control loop are integrated into the IC. When operating in 15-minute mode, for bq24153A/8, the OTG pin logic level sets the input current limit to 100mA for a logic low and 500mA for a logic high, whereas the bq24156A/9 defaults to 500mA. In 32 second mode, the input current limit is set by the programmed control bits in register 01H.

9.4 Device Functional Modes

9.4.1 Charge Mode Operation

bq24153A bq24156A bq24158 bq24159 opr_flo_lusa27.gif Figure 18. Operational Flow Chart of bq2415x in Charge Mode

9.4.1.1 Charge Profile

Once a good battery with voltage below the recharge threshold has been inserted and a good adapter is attached, the bq2415x enters charge mode. In charge mode, the IC has five control loops to regulate input voltage, input current, charge current, charge voltage and device junction temperature. During the charging process, all five loops are enabled and the one that is dominant takes control. The IC supports a precision Li-ion or Li-polymer charging system for single-cell applications. (a) indicates a typical charge profile without input current regulation loop. It is the traditional CC/CV charge curve, while (b) shows a typical charge profile when input current limiting loop is dominant during the constant current mode. In this case, the charge current is higher than the input current so the charge process is faster than the linear chargers. For bq24153A/6A/8/9, the input voltage threshold for DPM loop, input current limits, the charge current, termination current, and charge voltage are all programmable using I2C interface.

bq24153A bq24156A bq24158 bq24159 typ_chg_pro_lus931.gif Figure 19. Typical Charging Profile of bq24153A/6A/8/9 for
(a) without Input Current Limit, and (b) with Input Current Limit

9.4.2 PWM Controller in Charge Mode

The IC provides an integrated, fixed 3 MHz frequency voltage-mode controller to regulate charge current or voltage. This type of controller is used to improve line transient response, thereby, simplifying the compensation network used for both continuous and discontinuous current conduction operation. The voltage and current loops are internally compensated using a Type-III compensation scheme that provides enough phase margin for stable operation, allowing the use of small ceramic capacitors with a low ESR. The device operates between 0% to 99.5% duty cycles.

The IC has back to back common-drain N-channel FETs at the high side and one N-channel FET at low side. The input N-FET (Q1) prevents battery discharge when VBUS is lower than VCSOUT. The second high-side N-FET (Q2) is the switching control switch. A charge pump circuit is used to provide gate drive for Q1, while a bootstrap circuit with an external bootstrap capacitor is used to supply the gate drive voltage for Q2.

Cycle-by-cycle current limit is sensed through the FETs Q2 and Q3. The threshold for Q2 is set to a nominal 2.4-A peak current. The low-side FET (Q3) also has a current limit that decides if the PWM Controller will operate in synchronous or non-synchronous mode. This threshold is set to 100mA and it turns off the low-side N-channel FET (Q3) before the current reverses, preventing the battery from discharging. Synchronous operation is used when the current of the low-side FET is greater than 100mA to minimize power losses.

9.4.3 Battery Charging Process

At the beginning of precharge, while battery voltage is below the V(SHORT) threshold, the IC applies a short-circuit current, I(SHORT), to the battery. When the battery voltage is above VSHORT and below VOREG, the charge current ramps up to fast charge current, IOCHARGE, or a charge current that corresponds to the input current of IIN_LIMIT. The slew rate for fast charge current is controlled to minimize the current and voltage over-shoot during transient. Both the input current limit, IIN_LIMIT, and fast charge current, IOCHARGE, can be set by the host. Once the battery voltage reaches the regulation voltage, VOREG, the charge current is tapered down as shown in . The voltage regulation feedback occurs by monitoring the battery-pack voltage between the CSOUT and PGND pins. In HOST mode, the regulation voltage is adjustable (3.5V to 4.44V) and is programmed through I2C interface. In 15-minute mode, the regulation voltage is fixed at 3.54V.

The IC monitors the charging current during the voltage regulation phase. If termination is enabled, during the normal charging process with HOST control, once the voltage at the CSOUT pin is above the battery recharge threshold, VOREG - VRCH for the 32-ms (typical) deglitch period, and the termination charge current ITERM is detected, the IC turns off the PWM charge and enables a discharge current, IDETECT, for a period of tDETECT (262-ms typical), then checks the battery voltage. If the battery voltage is still above the recharge threshold after tDETECT, the battery charging is complete. The battery detection routine is used to ensure termination did not occur because the battery was removed. After 40ms (typical) for synchronization purposes of the EOC state and the counter, the status bit and pin are updated to indicate charging has completed. The termination current level is programmable. To disable the charge current termination, the host can set the charge termination bit (I_Term) of charge control register to 0, refer to I2C section for detail.

A new charge cycle is initiated when one of the following conditions is detected:

  • The battery voltage falls below the V(OREG) – V(RCH) threshold.
  • VBUS Power-on reset (POR), if battery voltage is below the V(LOWV) threshold.
  • CE bit toggle or RESET bit is set (Host controlled)

9.4.4 Thermal Regulation and Protection

To prevent overheating of the chip during the charging process, the IC monitors the junction temperature, TJ, of the die and begins to taper down the charge current once TJ reaches the thermal regulation threshold, TCF. The charge current is reduced to zero when the junction temperature increases approximately 10°C above TCF. In any state, if TJ exceeds TSHTDWN, the IC suspends charging. In thermal shutdown mode, PWM is turned off and all timers are frozen. Charging resumes when TJ falls below TSHTDWN by approximately 10°C.

9.4.5 Charge Status Output, STAT Pin

The STAT pin is used to indicate operation conditions for bq24153A/6A/8/9. STAT is pulled low during charging when EN_STAT bit in control register (00H) is set to “1”. Under other conditions, STAT pin behaves as a high impedance (open-drain) output. Under fault conditions, a 128-µs pulse will be sent out to notify the host. The status of STAT pin at different operation conditions is summarized in Table 1. The STAT pin can be used to drive an LED or communicate to the host processor.

Table 1. STAT Pin Summary

CHARGE STATE STAT
Charge in progress and EN_STAT=1 Low
Other normal conditions Open-drain
Charge mode faults: Timer fault, sleep mode, VBUS or battery overvoltage, poor input source, VBUS UVLO, no battery, thermal shutdown 128-μs pulse, then open-drain
Boost mode faults (bq24153A/8 only): Timer fault, over load, VBUS or battery overvoltage, low battery voltage, thermal shutdown 128-μs pulse, then open-drain

9.4.6 Control Bits in Charge Mode

9.4.6.1 CE Bit (Charge Mode)

The CE bit in the control register is used to disable or enable the charge process. A low logic level (0) on this bit enables the charge and a high logic level (1) disables the charge.

9.4.6.2 RESET Bit

The RESET bit in the control register is used to reset all the charge parameters. Writing ‘1” to the RESET bit will reset all the charge parameters to default values except the safety limit register, and RESET bit is automatically cleared to zero once the charge parameters get reset. It is designed for charge parameter reset before charge starts and it is not recommended to set the RESET bit while charging or boosting are in progress.

9.4.6.3 OPA_Mode Bit

OPA_MODE is the operation mode control bit. When OPA_MODE = 0, the IC operates as a charger if HZ_MODE is set to "0", refer to Table 2 for detail. When OPA_MODE=1 and HZ_MODE=0, the IC operates in boost mode.

Table 2. Operation Mode Summary

OPA_MODE HZ_MODE OPERATION MODE
0 0 Charge (no fault)
Charge configure (fault, Vbus > UVLO)
High impedance (Vbus < UVLO)
1(bq24153A/8 only) 0 Boost (no faults)
Any fault go to charge configure mode
X 1 High impedance

9.4.7 Control Pins in Charge Mode

9.4.7.1 CD Pin (Charge Disable)

The CD pin is used to disable the charging process. When the CD pin is low, charge is enabled. When the CD pin is high, charge is disabled and the charger enters high impedance (Hi-Z) mode.

9.4.7.2 SLRST Pin (Safety Limit Register 06H Reset, bq24156A/9 only)

The safety limit registers provide a means to limit both the maximum charge current and maximum battery regulation voltage at POR regardless of subsequent attempts to increase them via I2C. When the SLRST pin is low, bq24156A/9 will reset all the safety limits to default values, regardless of the write actions to safety limits registers (06H). When the SLRST pin is high, the bq24156A/9 can program the safety limit register until any write action to other registers locks the programmed safety limits.

9.4.8 BOOST Mode Operation (bq24153A/8 only)

In 32 second mode, when OTG pin is high (and OTG_EN bit is high thereby enabling OTG functionality) or the operation mode bit (OPA_MODE) is set to 1, bq24153A/8 operates in boost mode and delivers the power to VBUS from the battery. In normal boost mode, bq24153A/8 converts the battery voltage to VBUS-B (about 5.05V) and delivers a current as much as IBO (about 200mA) to support other USB OTG devices connected to the USB connector.

9.4.8.1 PWM Controller in Boost Mode

Similar to charge mode operation, in boost mode, the IC provides an integrated, fixed 3 MHz frequency voltage-mode controller to regulate output voltage at PMID pin (VPMID). The voltage control loop is internally compensated using a Type-III compensation scheme that provides enough phase margin for stable operation with a wide load range and battery voltage range.

In boost mode, the input N-FET (Q1) prevents battery discharge when VBUS pin is over loaded. Cycle-by-cycle current limit is sensed through the internal sense FET for Q3. The cycle-by-cycle current limit threshold for Q3 is set to a nominal 1.0-A peak current. Synchronous operation is used in PWM mode to minimize power losses.

9.4.8.2 Boost Start Up

To prevent the inductor saturation and limit the inrush current, a soft-start control is applied during the boost start up.

9.4.8.3 PFM Mode at Light Load

In boost mode, under light load conditions, the IC operates in pulse skipping mode (PFM mode) to reduce the power loss and improve the converter efficiency. During boosting, the PWM converter is turned off once the inductor current is less than 75mA; and the PWM is turned back on only when the voltage at PMID pin drops to about 99.5% of the rated output voltage. A unique pre-set circuit is used to make the smooth transition between PWM and PFM mode.

9.4.8.4 Safety Timer in Boost Mode

At the beginning of boost operation, the IC starts a 32-second timer that is reset by the host using the I2C interface. Writing “1” to reset bit of TMR_RST in control register will reset the 32-second timer and TMR_RST is automatically set to “0” after the 32-second timer is reset. Once the 32-second timer expires, the IC turns off the boost converter, enunciates the fault pulse from the STAT pin and sets fault status bits in the status register. The fault condition is cleared by POR or host control.

9.4.8.5 Protection in Boost Mode

9.4.8.5.1 Output Overvoltage Protection

The IC provides a built-in over-voltage protection to protect the device and other components against damage if the VBUS voltage goes too high. When an over-voltage condition is detected, the IC turns off the PWM converter, resets OPA_MODE bit to 0, sets fault status bits, and sends out a fault pulse from the STAT pin. Once VBUS drops to the normal level, the boost starts after host sets OPA_MODE to “1” or OTG pin stays in active status.

9.4.8.5.2 Output Overload Protection

The IC provides a built-in over-load protection to prevent the device and battery from damage when VBUS is over loaded. Once the over load condition is detected, Q1 operates in linear mode to limit the output current. If the over load condition lasts for more than 30ms, the over-load fault is detected. When an over-load condition is detected, the IC turns off the PWM converter, resets OPA_MODE bit to 0, sets fault status bits and sends out fault pulse in STAT pin. The boost will not start until the host clears the fault register.

9.4.8.5.3 Battery Overvoltage Protection

During boosting, when the battery voltage is above the battery over voltage threshold, VBATMAX, or below the minimum battery voltage threshold, VBATMIN, the IC turns off the PWM converter, resets OPA_MODE bit to 0, sets fault status bits and sends out fault pulse in STAT pin. Once the battery voltage goes above VBATMIN, the boost will start after the host sets OPA_MODE to “1” or OTG pin stays in active status.

9.4.8.6 STAT Pin in Boost Mode

During normal boosting operation, the STAT pin behaves as a high impedance (open-drain) output. Under fault conditions, a 128-μs pulse is sent out to notify the host.

9.4.9 High Impedance (HI-Z) Mode

In Hi-Z mode, the charger stops charging and enters a low quiescent current state to conserve power. Taking the CD pin high causes the charger to enter Hi-Z mode. When in 15-minute mode and the CD pin is low, the charger automatically enters Hi-Z mode if

  1. VBUS > UVLO and a battery with VBAT > VLOWV is inserted, or
  2. VBUS falls below UVLO.

Taking the CD pin high while in 15-minute mode resets the 15 minute timer.

When in HOST mode and the CD is low, the charger can be placed into Hi-Z mode if the HZ-MODE control bit is set to “1” and OTG pin is not in active status. Once the bq24153A/6A/8/9 enters Hi-Z mode and the CD pin is low, a low power 32-second timer is enabled when the battery voltage is below V(LOWV) to monitor if the host control is available or not. If the low power 32-second timer expires, the IC operates in 15-minute mode and the low power 32 second timer is disabled.

In order to exit Hi-Z mode, the CD pin must be low, VBUS must be higher than UVLO and the HOST must write a "0" to the HZ-MODE control bit.

9.5 Programming

9.5.1 Serial Interface Description

I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device.

The IC works as a slave and is compatible with the following data transfer modes, as defined in the I2C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (up to 3.4 Mbps in write mode). The interface adds flexibility to the battery charge solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents remain intact as long as supply voltage remains above 2.2 V (typical). I2C is asynchronous, which means that it runs off of SCL. The device has no noise or glitch filtering on SCL, so SCL input needs to be clean. Therefore, it is recommended that SDA changes while SCL is LOW.

The data transfer protocol for standard and fast modes is the same; therefore, they are referred to as F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as HS-mode. The bq24153A/6A/8/9 device supports 7-bit addressing only. The device 7-bit address is defined as ‘1101011’ (6BH) for bq24153A, and ‘1101010’ (6AH) for bq24156A/8/9.

9.5.1.1 F/S Mode Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 20. All I2C-compatible devices should recognize a start condition.

bq24153A bq24156A bq24158 bq24159 str_sto_lus824.gif Figure 20. START and STOP Condition

The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 21). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 21) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a slave has been established.

bq24153A bq24156A bq24158 bq24159 srl_inf_lus824.gif Figure 21. Bit Transfer on the Serial Interface

The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 23). This releases the bus and stops the communication link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to prevent the slave I2C logic from getting stuck in a bad state. Attempting to read data from register addresses not listed in this section will result in FFh being read out.

bq24153A bq24156A bq24158 bq24159 i2c_bus_lus824.gif Figure 22. Acknowledge on the I2C Bus™
bq24153A bq24156A bq24158 bq24159 bus_proto_lusa27.gif Figure 23. Bus Protocol

9.5.1.2 H/S Mode Protocol

When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices.

The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX. This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation.

The master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be used to secure the bus in HS-mode. If a transaction is terminated prematurely, the master needs sending a STOP condition to prevent the slave I2C logic from getting stuck in a bad state.

Attempting to read data from register addresses not listed in this section results in FFh being read out.

9.5.1.3 I2C Update Sequence

The IC requires a start condition, a valid I2C address, a register address byte, and a data byte for a single update. After the receipt of each byte, the IC acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I2C address selects the IC. The IC performs an update on the falling edge of the acknowledge signal that follows the LSB byte.

For the first update, the IC requires a start condition, a valid I2C address, a register address byte, a data byte. For all consecutive updates, The IC needs a register address byte, and a data byte. Once a stop condition is received, the IC releases the I2C bus, and awaits a new start conditions.

bq24153A bq24156A bq24158 bq24159 register_lusa27.gif Figure 24. Data Transfer Format in F/S Mode and H/S Mode

9.5.1.4 Slave Address Byte

MSB LSB
X 1 1 0 1 0 1 1

The slave address byte is the first byte received following the START condition from the master device.

9.5.1.5 Register Address Byte

MSB LSB
0 0 0 0 0 D2 D1 D0

Following the successful acknowledgment of the slave address, the bus master will send a byte to the IC, which contains the address of the register to be accessed. The IC contains five 8-bit registers accessible via a bidirectional I2C-bus interface. Among them, four internal registers have read and write access; and one has only read access.

9.6 Register Maps

9.6.1 Status/Control Register [Memory Location: 00, Reset State: x1xx 0xxx]

Table 3. Status/Control Register (Read/Write)
Memory Location: 00, Reset State: x1xx 0xxx

BIT NAME READ/WRITE FUNCTION
B7 (MSB) TMR_RST/OTG Read/Write Write: TMR_RST function, write "1" to reset the safety timer (auto clear)
Read: OTG pin status, (for bq24153A/8 only) 0-OTG pin at Low level, 1-OTG pin at High level
SLRST pin status (for bq2156A/9 only), 0-SLRST pin at LOW level, 1-SLRST pin at HIGH level.
B6 EN_STAT Read/Write 0-Disable STAT pin function, 1-Enable STAT pin function (default 1)
B5 STAT2 Read Only 00-Ready, 01-Charge in progress, 10-Charge done, 11-Fault
B4 STAT1 Read Only
B3 BOOST Read Only 1-Boost mode, 0-Not in boost mode, for bq24153A/8 only;
NA–for bq24156A/9.
B2 FAULT_3 Read Only Charge mode: 000-Normal, 001-VBUS OVP, 010-Sleep mode, 011-Bad Adaptor or VBUS<VUVLO,
100-Output OVP, 101-Thermal shutdown, 110-Timer fault, 111-No battery
Boost mode (for bq24153A/8 only): 000-Normal, 001-VBUS OVP, 010-Over load, 011-Battery voltage is too low, 100-Battery OVP, 101-Thermal shutdown, 110-Timer fault, 111-NA
B1 FAULT_2 Read Only
B0 (LSB) FAULT_1 Read Only

9.6.2 Control Register [Memory Location: 01, Reset State: 0011 0000]

Table 4. Control Register (Read/Write)
Memory Location: 01, Reset State: 0011 0000

BIT NAME READ/WRITE FUNCTION
B7 (MSB) Iin_Limit_2 Read/Write 00-USB host with 100-mA current limit, 01-USB host with 500-mA current limit, 10-USB host/charger with 800-mA current limit, 11-No input current limit (default 00 for bq24153A/8, default 01 for bq24156A/9)
B6 Iin_Limit_1 Read/Write
B5 V(LOWV_2) (1) Read/Write Weak battery voltage threshold: 200mV step (default 1)
B4 V(LOWV_1) (1) Read/Write Weak battery voltage threshold: 100mV step (default 1)
B3 TE Read/Write 1-Enable charge current termination, 0-Disable charge current termination (default 0)
B2 CE Read/Write 1-Charger is disabled, 0-Charger enabled (default 0)
B1 HZ_MODE Read/Write 1-High impedance mode, 0-Not high impedance mode (default 0)
B0 (LSB) OPA_MODE Read/Write 1-Boost mode, 0-Charger mode (default 0), for bq24153A/8 only; NA–for bq24156A/9.
(1) The range of the weak battery voltage threshold (V(LOWV)) is 3.4 V to 3.7 V with an offset of 3.4 V and steps of 100 mV (default 3.7 V, using bits B4-B5).

9.6.3 Control/Battery Voltage Register [Memory Location: 02, Reset State: 0000 1010]

Table 5. Control/Battery Voltage Register (Read/Write)
Memory Location: 02, Reset State: 0000 1010

BIT NAME READ/WRITE FUNCTION
B7 (MSB) VO(REG5) Read/Write Battery Regulation Voltage: 640 mV step (default 0)
B6 VO(REG4) Read/Write Battery Regulation Voltage: 320 mV step (default 0)
B5 VO(REG3) Read/Write Battery Regulation Voltage: 160 mV step (default 0)
B4 VO(REG2) Read/Write Battery Regulation Voltage: 80 mV step (default 0)
B3 VO(REG1) Read/Write Battery Regulation Voltage: 40 mV step (default 1)
B2 VO(REG0) Read/Write Battery Regulation Voltage: 20 mV step (default 0)
B1 OTG_PL Read/Write 1-OTG Boost Enable with High level, 0-OTG Boost Enable with Low level (default 1), for bq24153A/8 only; NA–for bq24156A/9; not applicable to OTG pin control of current limit at POR in 15-minute mode
B0 (LSB) OTG_EN Read/Write 1-Enable OTG Pin in HOST mode, 0-Disable OTG pin in HOST mode (default 0), for bq24153A/8 only; NA–for bq24156A/9; not applicable to OTG pin control of current limit at POR in 15-minute mode

9.6.4 Vender/Part/Revision Register [Memory Location: 03, Reset State: 0101 000x]

  • Charge voltage range is 3.5 V to 4.44 V with the offset of 3.5 V and steps of 20 mV (default 3.54 V), using bits B2-B7.

Table 6. Vender/Part/Revision Register (Read only)
Memory Location: 03, Reset State: 0101 000x

BIT NAME READ/WRITE FUNCTION
B7 (MSB) Vender2 Read Only Vender Code: bit 2 (default 0)
B6 Vender1 Read Only Vender Code: bit 1 (default 1)
B5 Vender0 Read Only Vender Code: bit 0 (default 0)
B4 PN1 Read Only For I2C Address 6BH: 10–bq24153A; 11–NA.
For I2C Address 6AH: 00--bq24156A/9, 01–NA, 10–bq24158, 11–NA.
B3 PN0 Read Only
B2 Revision2 Read Only 011: Revision 1.0;
001: Revision 1.1;
100-111: Future Revisions
B1 Revision1 Read Only
B0 (LSB) Revision0 Read Only

9.6.5 Battery Termination/Fast Charge Current Register [Memory Location: 04, Reset State: 0000 000]

Table 7. Battery Termination/Fast Charge Current Register (Read/Write)
Memory Location: 04, Reset State: 0000 0001

BIT NAME READ/WRITE FUNCTION
B7 (MSB) Reset Read/Write Write: 1-Charger in reset mode, 0-No effect, Read: always get "0"
B6 VI(CHRG3) (1) Read/Write Charge current sense voltage: 27.2 mV step – for bq24153A/8; 54.4mV step – for bq24156A/9 (default 0)
B5 VI(CHRG2) (1) Read/Write Charge current sense voltage: 13.6 mV step – for bq24153A/8; 27.2mV step – for bq24156A/9 (default 0)
B4 VI(CHRG1) (1) Read/Write Charge current sense voltage: 6.8 mV step – for bq24153A/8; 13.6mV step – for bq24156A/9 (default 0)
B3 VI(CHRG0) (1) Read/Write NA – for bq24153A/8; 6.8mV step – for bq24156A/9 (default 0)
B2 VI(TERM2) (2) Read/Write Termination current sense voltage: 13.6 mV step (default 0)
B1 VI(TERM1) (2) Read/Write Termination current sense voltage: 6.8 mV step (default 0)
B0 (LSB) VI(TERM0) (2) Read/Write Termination current sense voltage: 3.4 mV step (default 1)
(1) See Table 13
(2) See Table 12
  • For bq24153A/8, charge current sense voltage offset is 37.4mV and default charge current is 550mA, if 68-mΩ sensing resistor is used and LOW_CHG=0.
  • For bq24156A/9, the maximum charge current is 1.55A. If a higher value is programmed, the 1.55A or maximum safety limit charge current is selected.

9.6.6 Special Charger Voltage/Enable Pin Status Register [Memory location: 05, Reset state: 001X X100]

Table 8. Special Charger Voltage/Enable Pin Status Register
Memory location: 05, Reset state: 001X X100

BIT NAME READ/WRITE FUNCTION
B7 (MSB) NA Read/Write NA
B6 NA Read/Write NA
B5 LOW_CHG Read/Write 0 – Normal charge current sense voltage at 04H,
1 – Low charge current sense voltage of 22.1mV (default 1)
B4 DPM_STATUS Read Only 0 – DPM mode is not active,
1 – DPM mode is active
B3 CD_STATUS Read Only 0 – CD pin at LOW level,
1 – CD pin at HIGH level
B2 VSREG2 Read/Write Special charger voltage: 320mV step (default 1)
B1 VSREG1 Read/Write Special charger voltage: 160mV step (default 0)
B0 (LSB) VSREG0 Read/Write Special charger voltage: 80mV step (default 0)
  • Special charger voltage offset is 4.2V and default special charger voltage is 4.52V.
  • Default charge current will be 325mA, if 68-mΩ sensing resistor is used, since default LOW_CHG=1.

9.6.7 Safety Limit Register [Memory location: 06, Reset state: 01000000]

Table 9. Safety Limit Register (READ/WRITE, Write only once after reset!)
Memory location: 06, Reset state: 01000000

BIT NAME READ/WRITE FUNCTION
B7 (MSB) VMCHRG3 (1) Read/Write Maximum charge current sense voltage: 54.4 mV step (default 0)
B6 VMCHRG2 (1) Read/Write Maximum charge current sense voltage: 27.2 mV step (default 1)
B5 VMCHRG1 (1) Read/Write Maximum charge current sense voltage: 13.6 mV step (default 0)
B4 VMCHRG0 (1) Read/Write Maximum charge current sense voltage: 6.8 mV step (default 0)
B3 VMREG3 Read/Write Maximum battery regulation voltage: 160 mV step (default 0)
B2 VMREG2 Read/Write Maximum battery regulation voltage: 80 mV step (default 0)
B1 VMREG1 Read/Write Maximum battery regulation voltage: 40 mV step (default 0)
B0 (LSB) VMREG0 Read/Write Maximum battery regulation voltage: 20 mV step (default 0)
(1) Refer to Table 13
  • Maximum charge current sense voltage offset is 37.4 mV (550mA), default at 64.6mV (950mA) and the maximum charge current option is 1.55A (105.4mV), if 55-mΩ sensing resistor is used.
  • Maximum battery regulation voltage offset is 4.2V (default at 4.2V) and maximum battery regulation voltage option is 4.44V.
  • Memory location 06H resets only when V(CSOUT) drops below either 1) V(SHORT) threshold (typ. 2.05V) if VBUS > V(UVLO), 2) the digital reset threshold (typ. 2.4V) if VBUS < V(UVLO) or 3) SLRST (pin D4, for bq24156A/9 only) goes to logic ‘0’. After reset, the maximum values for battery regulation voltage and charge current can be programmed until any writing to other register locks the safety limits. Programmed values exclude higher values from memory locations 02 (battery regulation voltage), and from memory location 04 (Fast charge current).
  • If host accesses (write command) to some other register before Safety limit register, the safety default values are used.