SLOS626B December   2009  â€“ November 2015 TPA2011D1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Operating Characteristics
    7. 7.7 Dissipation Ratings
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fully Differential Amplifier
        1. 9.3.1.1 Advantages of Fully Differential Amplifiers
      2. 9.3.2 Eliminating the Output Filter With the TPA2011D1
        1. 9.3.2.1 Effect on Audio
        2. 9.3.2.2 When to Use an Output Filter
      3. 9.3.3 Short Circuit Auto-Recovery
      4. 9.3.4 Integrated Image Reject Filter for DAC Noise Rejection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Summing Input Signals With the TPA2011D1
        1. 9.4.1.1 Summing Two Differential Input Signals
        2. 9.4.1.2 Summing a Differential Input Signal and a Single-Ended Input Signal
        3. 9.4.1.3 Summing Two Single-Ended Input Signals
      2. 9.4.2 Shutdown Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 TPA2011D1 with Differential Input
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Input Resistors (RI)
          2. 10.2.1.2.2 Decoupling Capacitor (CS)
        3. 10.2.1.3 Application Curves
      2. 10.2.2 TPA2011D1 with Differential Input and Input Capacitors
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Input Capacitors (CI)
        3. 10.2.2.3 Application Curves
      3. 10.2.3 TPA2011D1 with Single-Ended Input
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Decoupling Capacitors
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range, TA = 25°C (unless otherwise noted)(1)
MIN MAX UNIT
VDD, PVDD Supply voltage In active mode –0.3 6 V
In shutdown mode –0.3 6 V
VI Input voltage EN, IN+, IN– –0.3 VDD + 0.3 V
RL Minimum load resistance 3.2 Ω
Output continuous total power dissipation See Dissipation Ratings
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature –40 150 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C
Tstg Storage temperature –65 85 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN MAX UNIT
VDD Class-D supply voltage 2.5 5.5 V
VIH High-level input voltage EN 1.3 V
VIL Low-level input voltage EN 0.35 V
RI Input resistor Gain ≤ 20 V/V (26 dB) 15 kΩ
VIC Common mode input voltage range VDD = 2.5V, 5.5V, CMRR ≥ 49 dB 0.75 VDD-1.1 V
TA Operating free-air temperature –40 85 °C

7.4 Thermal Information

THERMAL METRIC(1) TPA2011D1 UNIT
YFF (DSBGA)
9 PINS
RθJA Junction-to-ambient thermal resistance 107 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.9 °C/W
RθJB Junction-to-board thermal resistance 18.1 °C/W
ψJT Junction-to-top characterization parameter 3.8 °C/W
ψJB Junction-to-board characterization parameter 18 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|VOS| Output offset voltage (measured differentially) VI = 0 V, AV = 2 V/V, VDD = 2.5 V to 5.5 V 1 5 mV
|IIH| High-level input current VDD = 5.5 V, VEN = 5.5 V 50 μA
|IIL| Low-level input current VDD = 5.5 V, VEN = 0 V 1 μA
I(Q) Quiescent current VDD = 5.5 V, no load 1.8 2.5 mA
VDD = 3.6 V, no load 1.5 2.3
VDD = 2.5 V, no load 1.3 2.1
I(SD) Shutdown current VEN = 0.35 V, VDD = 2.5 V to 5.5 V 0.1 2 μA
RO, SD Output impedance in shutdown mode VEN = 0.35 V 2 kΩ
f(SW) Switching frequency VDD = 2.5 V to 5.5 V 250 300 350 kHz
AV Gain VDD = 2.5 V to 5.5 V, RI in kΩ 285/RI 300/RI 315/RI V/V
REN Resistance from EN to GND 300 kΩ

7.6 Operating Characteristics

VDD = 3.6 V, TA = 25°C, AV = 2 V/V, RL = 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PO Output power THD + N = 10%, f = 1 kHz, RL = 4 Ω VDD = 5 V 3.24 W
VDD = 3.6 V 1.62
VDD = 2.5 V 0.70
THD + N = 1%, f = 1 kHz, RL = 4 Ω VDD = 5 V 2.57 W
VDD = 3.6 V 1.32
VDD = 2.5 V 0.57
THD + N = 10%, f = 1 kHz, RL = 8 Ω VDD = 5 V 1.80 W
VDD = 3.6 V 0.91
VDD = 2.5 V 0.42
THD + N = 1%, f = 1 kHz, RL = 8 Ω VDD = 5 V 1.46 W
VDD = 3.6 V 0.74
VDD = 2.5 V 0.33
Vn Noise output voltage VDD = 3.6 V, Inputs AC grounded
with CI = 2μF, f = 20 Hz to 20 kHz 		A-weighting 20 μVRMS
No weighting 25
THD+N Total harmonic distortion plus noise VDD = 5.0 V, PO = 1.0 W, f = 1 kHz, RL = 8 Ω 0.11%
VDD = 3.6 V, PO = 0.5 W, f = 1 kHz, RL = 8 Ω 0.05%
VDD = 2.5 V, PO = 0.2 W, f = 1 kHz, RL = 8 Ω 0.05%
VDD = 5.0 V, PO = 2.0 W, f = 1 kHz, RL = 4 Ω 0.23%
VDD = 3.6 V, PO = 1.0 W, f = 1 kHz, RL = 4 Ω 0.07%
VDD = 2.5 V, PO = 0.4 W, f = 1 kHz, RL = 4 Ω 0.06%
PSRR AC power supply rejection ratio VDD = 3.6 V, Inputs AC grounded with CI = 2 μF,
200 mVpp ripple, f = 217 Hz		 86 dB
CMRR Common mode rejection ratio VDD = 3.6 V, VIC = 1 VPP, f = 217 Hz 79 dB
TSU Startup time from shutdown VDD = 3.6 V 4 ms
IOC Overcurrent protection threshold VDD = 3.6 V, VO+ shorted to VDD 2 A
VDD = 3.6 V, VO– shorted to VDD 2
VDD = 3.6 V, VO+ shorted to GND 2
VDD = 3.6 V, VO– shorted to GND 2
VDD = 3.6 V, VO+ shorted to VO– 2
TSD Time for which output is disabled after a short-circuit event, after which auto-recovery trials are continuously made VDD = 2.5 V to 5.5 V 100 ms

7.7 Dissipation Ratings

PACKAGE DERATING FACTOR(1) TA < 25°C TA = 70°C TA = 85°C
YFF (DSBGA) 4.2 mW/°C 525 mW 336 mW 273 mW
(1) Derating factor measure with high K board.

7.8 Typical Characteristics

VDD = 3.6 V, CI = 0.1 μF, CS1 = 0.1 μF, CS2 = 10 μF, TA = 25°C, RL = 8 Ω (unless otherwise noted)
TPA2011D1 Fig01_Efficiency_8ohm.gif Figure 1. Efficiency vs Output Power
TPA2011D1 Fig03_powerDissipation_3p6V.gif Figure 3. Power Dissipation vs Output Power
TPA2011D1 Fig05_IDD_pout_4ohm.gif Figure 5. Supply Current vs Output Power
TPA2011D1 Fig07_supplycurrent_vs_supplyvoltage.gif Figure 7. Supply Current vs Supply Voltage
TPA2011D1 Fig09_RL_Vs_pout_10percentTHD.gif Figure 9. Output Power vs Load Resistance
TPA2011D1 Fig11_pout_vdd.gif Figure 11. Output Power vs Supply Resistance
TPA2011D1 Fig13_THDVsPout_8ohm.png Figure 13. THD + Noise vs Output Power
TPA2011D1 Fig15_THD_VS_Freq_8ohm_3p6V.gif Figure 15. THD + Noise vs Frequency
TPA2011D1 Fig17_THD_VS_Freq_4ohm_5V.gif Figure 17. THD + Noise vs Frequency
TPA2011D1 Fig19_THD_VS_Freq_4ohm_2p5V.gif Figure 19. THD + Noise vs Frequency
TPA2011D1 Fig21_PSRR_VS_Frequency_8ohm.gif Figure 21. Power Supply Rejection Ratio vs Frequency
TPA2011D1 Fig23_PSRR_VS_CommonModeV.gif Figure 23. Power Supply Rejection Ratio vs Common Mode Input Voltage
TPA2011D1 Fig25_CMRR_VS_CommonModeV.gif Figure 25. Common Mode Rejection Ratio vs Common Mode Input Voltage
TPA2011D1 Fig27_GSM_PSRR_Vs_Frequency.gif Figure 27. GSM Power Supply Rejection vs Frequency
TPA2011D1 Fig02_Efficiency_4ohm.gif Figure 2. Efficiency vs Output Power
TPA2011D1 Fig04_powerDissipation_5V.gif Figure 4. Power Dissipation vs Output Power
TPA2011D1 Fig06_IDD_pout_8ohm.gif Figure 6. Supply Current vs Output Power
TPA2011D1 Fig08_supply_currentVs_shutdownVoltage.gif Figure 8. Supply Current vs EN Voltage
TPA2011D1 Fig10_RL_Vs_pout_1percentTHD.gif Figure 10. Output Power vs Load Resistance
TPA2011D1 Fig12_THD_Vs_Pout_4ohm.png Figure 12. THD + Noise vs Output Power
TPA2011D1 Fig14_THD_VS_Freq_8ohm_5V.gif Figure 14. THD + Noise vs Frequency
TPA2011D1 Fig16_THD_VS_Freq_8ohm_2.5V.gif Figure 16. THD + Noise vs Frequency
TPA2011D1 Fig18_THD_VS_Freq_4ohm_3p6V.gif Figure 18. THD + Noise vs Frequency
TPA2011D1 Fig20_THD_VS_CommonModeVoltage.gif Figure 20. THD + Noise vs Common Mode Input Voltage
TPA2011D1 Fig22_PSRR_VS_Frequency_4ohm.gif Figure 22. Power Supply Rejection Ratio vs Frequency
TPA2011D1 Fig24_CMRR_VS_Frequency_8ohm.gif Figure 24. Common Mode Rejection Ratio vs Frequency
TPA2011D1 Fig26_GSM_PSRR_Vs_time.gif Figure 26. GSM Power Supply Rejection vs Time