SLOA248B January 2018 – March 2019 TRF7960A , TRF7962A , TRF7963A
An IRQ status of 0xC0 indicates that both the TX complete and RX start bits have been set. This can be an issue as the TRF79xxA FIFO is supposed to be reset with the direct command 0x0F after a TX operation is finished and before an RX operation begins. Not resetting the FIFO can result in corrupted RX data.
The typical cause for this issue is that the interrupt for the TX complete event (IRQ status = 0x80) is not serviced quickly enough. This can either be an issue with priority of the interrupt or MCU clock speed. Ensure that the IRQ interrupt is serviced correctly and that the FIFO is reset with the direct command 0x0F after receiving the TX complete event. When done correctly, then the interrupt for either the RX complete event (IRQ status = 0x40) or the RX in progress event (IRQ status = 0x60) should be correctly received.
For the TRF79xxA devices with a 12-byte FIFO, another IRQ status that falls into this category is the IRQ status of 0xE0, which indicates that the TX complete bit has been set and that an RX operation is in progress and the FIFO is about to become full. This situation must be handled the same way by servicing the individual interrupts in a timely manner so the device is kept in a good state for each operation.