SLLA652 April   2025 TCAN2410-Q1 , TCAN2411-Q1 , TCAN2450-Q1 , TCAN2451-Q1 , TCAN2845-Q1 , TCAN2847-Q1 , TCAN2855-Q1 , TCAN2857-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2SPI Communication
  6. 3Register Organization
  7. 4EEPROM
  8. 5Suggested Data Structures and Program Flow
  9. 6Example Register Configurations
    1. 6.1 SBC and CAN Transceiver Mode Configuration
    2. 6.2 Partial Networking
    3. 6.3 Watchdog Timer
  10. 7Summary
  11. 8References

4 EEPROM

One of the most important features that is included in the TCAN28xx and TCAN24xx families of devices is the inclusion of an EEPROM which has a dedicated section for designers to use. The EEPROM has two major purposes: contains device trimming configuration that is not accessible to end users and an end user accessible portion that can be used to save select register bits so the device does not have to be reconfigured every time. This section details what information can be saved in the EEPROM and how the EEPROM functions.

The EEPROM can be used to save the following bits for the TCAN28xx line of devices– this is similar to table found in section 8.5.2 of the device’s data sheet.

Table 4-1 TCAN28XX - Register Bits That can be Saved to EEPROM
Register Name Register Address Bits Saved Configuration
SPI_CONFIG 9h 0-3 Byte Count, SDI Polarity, SPI Mode
SBC_CONFIG Ch 0-1,4,6 VEXCC Current Limit, VCC1 Sink Capability, VCC2 Configuration
VREG_CONFIG1 Dh 0-7 VEXCC Configuration, VEXCC Output Selection, VCC1 Sink current control, VCC1 Configuration
SBC_CONFIG1 Eh 0,3-5,7 SW pin Polarity, UVCC1 selection, VCC1 Sleep Mode Action, CAN transceiver Slope Control
WAKE_PIN_CONFIG1 11h 0-4 Min and Max wake pin pulse width configuration
WAKE_PIN_CONFIG2 12h 0-1,5,6 WAKE1 level, WAKE1 Sensing Mode, cyclic wake configuration
WD_CONFIG_1 13h 0-7 Watchdog Mode Select, Watchdog prescaler select, watchdog in sleep mode configuration, watchdog during standby mode configuration, long window time for initial watchdog.
WD_CONFIG_2 14h 0,5-7 Watchdog timer setting, watchdog during standby mode disable
WD_RST_PULSE 16h 4-7 Watchdog Error threshold before device restart.
DEVICE_CONFIG1 1Ah 0,4,7 LIMP during FSM control, LIMP disable control, Cyclic Sensing Wakeup during FSM control.
DEVICE_CONFIG2 1Bh 0 nINT toggle at interrupt generation enable.
SWE_TIMER 1Ch 3-7 SWE Enable Control, SWE Timer Select
nRST_CNTL 29h 5 nRST Pulse Width length when device restarts due to watchdog failure
WAKE_PIN_CONFIG4 2Bh 0-1,3,4-5,7 WAKE3 Threshold, WAKE3 static or cyclic control, WAKE2 Threshold, WAKE2 static or cyclic control.
WD_QA_CONFIG 2Dh 0-7 Watchdog answer generation configuration, watchdog Q&A polynomial configuration, Watchdog Q&A polynomial seed value
HSS_CNTL3 4Fh 0,4 Restart Timer Selection, Cyclic wake in sleep mode enable

While similar action – the bits able to be saved for the TCAN24xx are slightly different.

Table 4-2 TCAN24XX - Register Bits That can be Saved to EEPROM
Register NameRegister AddressBits SavedConfiguration
SBC_CONFIGCh0-1,4,7OVCC1 threshold select, VCC1 Sink Capability, VCC2 Configuration
VREG_CONFIG1Dh3,5,6-7FPWM during OVSUP control, VCC1 Sink current control, VCC1 Configuration
SBC_CONFIG1Eh0,3-5SW pin Polarity, UVCC1 selection, VCC1 Sleep Mode Action
WAKE_PIN_CONFIG111h0-3Min and Max wake pin pulse width configuration
WAKE_PIN_CONFIG212h0-1,5-7WAKE1 level, WAKE1 Sensing Mode, cyclic wake configuration, wake pulse configuration
WD_CONFIG_113h0-7Watchdog Mode Select, Watchdog prescaler select, watchdog in sleep mode configuration, watchdog during standby mode configuration, long window time for initial watchdog.
WD_CONFIG_214h0,5-7Watchdog timer setting, watchdog during standby mode disable
WD_RST_PULSE16h4-7Watchdog Error threshold before device restart.
DEVICE_CONFIG21Bh2UVLO on VSUP that disables BUCK
SWE_TIMER1Ch3-7SWE Enable Control, SWE Timer Select
nRST_CNTL29h4,5nRST Pulse Width length when device restarts due to watchdog failure, GFO polarity select
WAKE_PIN_CONFIG32Ah4-7WAKE1-WAKE4 enable bits
WAKE_PIN_CONFIG42Bh0-1,3,4-5,7WAKE3 Threshold, WAKE3 static or cyclic control, WAKE2 Threshold, WAKE2 static or cyclic control.
HSS_CNTL34Fh0,4Restart Timer Selection, Cyclic wake in sleep mode enable
SMPS_CONFIG165h0-7Spread spectrum modulation frequency spread, buck regulator switching frequency, PFM/PWM mode configuration in normal mode, PFM/PWM in standby/sleep mode, VCC1 current limit select
WAKE_ID_PIN_CONFIG179h1-3,5-7ID1 and ID2 enable bits and bias resistor selection
WAKE_ID_PIN_CONFIG27Ah1-3,5-7ID3 and ID4 enable bits and bias resistor selection
WAKE_PIN_CONFIG57Bh4-5,7WAKE4 level and cyclic or static control bit.

For the EEPROM configuration to be saved SPI with CRC check must be configured at the very minimum. To save the register bits as stated beforehand the processor must write 0b1 to register address 4E at bit position 7 as well as writing the default code Ah to register address 4Eh in the least significant nibble of register (bit field 3-0) followed by the CRC byte. Register 4Eh’s least significant nibble can read back 0x0 and once the configuration bits have been saved register 4Eh’s bit position 7 can read back 0b0. In applications where the host processor doesn’t support CRC or CRC is not needed for anything else but the EEPROM save there is a work-around. First, the device is configured as this normally can be. Then set the CRC polynomial at bit position 0 of register at address Bh where 0b0 is AutoSar and 0b1 is SAE J11850. Next, the SPI CRC must be enabled by writing 0x1 to bit position 0 in register Ah. Then, the EEPROM configuration can be saved as previously described. Finally disable the SPI CRC if processor does not support this or is unwanted for rest of the application. As a final note, the EEPROM can only be reprogrammed up to 500 times.

To understand how the EEPROM functions under different events – there are five main ones to be aware of.

  1. UVSUP event; no action is taken w.r.t. EEPROM because register configuration is not lost.
  2. Power on Reset (POR) event; EEPROM is read and registers are restored in Init Mode when VSUP > UVSUP_33R
  3. Soft Reset; EEPROM is read, registers are restored, and device transitions to Standby mode
  4. Hard Reset; EEPROM is read, registers are restored, and device transitions to Init mode

nRST input; EEPROM is read, registers are restored, and device transitions to Restart mode