SLAZ771 February   2026 MSPM0G1218 , MSPM0G3218-Q1

 

  1.   1
  2.   Abstract
  3. 1Functional Advisories
  4. 2Preprogrammed Software Advisories
  5. 3Debug Only Advisories
  6. 4Fixed by Compiler Advisories
  7. 5Device Nomenclature
  8. 6Advisory Descriptions
    1. 6.1  AES_ERR_01
    2. 6.2  CPU_ERR_02
    3. 6.3  CPU_ERR_03
    4. 6.4  FLASH_ERR_03
    5. 6.5  FLASH_ERR_04
    6. 6.6  FLASH_ERR_05
    7. 6.7  FLASH_ERR_08
    8. 6.8  GPIO_ERR_05
    9. 6.9  GPIO_ERR_06
    10. 6.10 KEYSTORE_ERR_01
    11. 6.11 MATHACL_ERR_01
    12. 6.12 PMCU_ERR_13
    13. 6.13 RST_ERR_01
    14. 6.14 SYSCTL_ERR_01
    15. 6.15 SYSCTL_ERR_02
    16. 6.16 SYSCTL_ERR_03
    17. 6.17 SYSCTL_ERR_04
    18. 6.18 SYSCTL_ERR_05
    19. 6.19 SYSCTL_ERR_06
    20. 6.20 SYSOSC_ERR_01
    21. 6.21 SYSOSC_ERR_02
    22. 6.22 SYSOSC_ERR_04
    23. 6.23 SYSPLL_ERR_01
    24. 6.24 TIMER_ERR_04
    25. 6.25 TIMER_ERR_06
    26. 6.26 TIMER_ERR_07
    27. 6.27 UNICOMMI2CC_ERR_01
    28. 6.28 UNICOMMUART_ERR_06
    29. 6.29 UNICOMMUART_ERR_07
    30. 6.30 UNICOMMUART_ERR_09
    31. 6.31 UNICOMMUART_ERR_10
    32. 6.32 VREF_ERR_05
  9. 7Revision History

6.24 TIMER_ERR_04

TIMER Module

Category

Functional

Function

TIMER re-enable may be missed if done close to zero event

Description

When using a TIMER in one shot mode, TIMER re-enable may be missed if done close to zero event. The HW update to the timer enable bit will take a single functional clock cycle, if you use 32.768kHz and divider of 3, then it will take ~100us to have the enable bit set to 0 properly.

Workaround

Wait 1 functional clock cycle before re-enabling the timer OR the timer can be disabled first before re-enabling. Disable the counter with CTRCTL.EN = 0, then reenable with CTRCTL.EN = 1