SLAZ771 February 2026 MSPM0G1218 , MSPM0G3218-Q1
TIMG Module
Functional
Writing 0 to CLKEN bit does not disable counter
Writing 0 to the Counter Clock Control Register(CCLKCTL) Clock Enable bit(CLKEN) does not stop the timer.
Stop the timer by writing 0 to the Counter Control(CTRCTL) Enable(EN) bit.