SLAZ648S February   2015  – May 2021 MSP430F6734A

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      PZ100
      2.      PN80
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC39
    2. 6.2  ADC42
    3. 6.3  ADC69
    4. 6.4  AUXPMM2
    5. 6.5  BSL7
    6. 6.6  BSL14
    7. 6.7  CPU21
    8. 6.8  CPU22
    9. 6.9  CPU36
    10. 6.10 CPU40
    11. 6.11 CPU46
    12. 6.12 CPU47
    13. 6.13 DMA4
    14. 6.14 DMA7
    15. 6.15 DMA9
    16. 6.16 DMA10
    17. 6.17 EEM8
    18. 6.18 EEM17
    19. 6.19 EEM19
    20. 6.20 EEM23
    21. 6.21 JTAG26
    22. 6.22 JTAG27
    23. 6.23 LCDB5
    24. 6.24 LCDB6
    25. 6.25 PMM7
    26. 6.26 PMM11
    27. 6.27 PMM12
    28. 6.28 PMM14
    29. 6.29 PMM15
    30. 6.30 PMM18
    31. 6.31 PMM20
    32. 6.32 PMM26
    33. 6.33 PORT15
    34. 6.34 PORT19
    35. 6.35 SD3
    36. 6.36 UCS11
    37. 6.37 USCI36
    38. 6.38 USCI37
    39. 6.39 USCI41
    40. 6.40 USCI42
    41. 6.41 USCI47
    42. 6.42 USCI50
  7. 7Revision History

6.4 AUXPMM2

AUXPMM Module

Category

Functional

Function

Latch-up in AUXPMM

Description

Latch-up current can appear at the AUXPMM module supply pins in the following two scenarios:

Scenario 1: When the AUXPMM is configured for hardware- or software-controlled switching and the module switches from DVCC to AUXVCC2, latch-up current can appear at AUXVCC2 at the switching point defined by SVSMHCTL.SVSMHRRL (or AUXCTL2.AUX0LVLx). The probability for this event to occur depends on:
a) Operating temperature (higher temperatures increase probability)
b) External AUXVCC2 voltage level (higher voltages increase probability)
c) SVSMHRRL level (lower levels increase probability) defining the switching level in hardware-controlled mode
d) AUX0LVLx level (lower levels increase probability) defining the switching level in software-controlled mode (applicable to DVCC only)

Scenario 2: When a battery is connected to DVCC, AUXVCC1 or AUXVCC2 as the first voltage supply, due to the low internal resistance of the battery a very fast rise time is seen by the AUXPMM and latch-up current can appear at the connected supply if:
a) Rise times are in the range of 140 kV/s (faster rise times increase probability)
b) Device operates at temperatures of 75 deg C and above (higher temperatures increase probability)

The latch-up current disappears after complete power cycles of all supply sources.

Workaround

For scenario 1:
- Increase SVSMRRL to a level above maximum external voltage expected on AUXVCC2. SVSMRRL = 6 or 7 (requires VCORE level of 3) is applicable for AUXVCC2 of up to maximum voltage, 3.58V, while a lower SVSMRRL setting can be selected if a lower voltage (e.g. 3.3V) is expected on AUXVCC2.

Or

- Connect all 3 supplies via 3 external diodes to DVCC and realize the switching externally without using the internal AUXPMM switches. See application report "Implementation of a Three-Phase Electronic Watt-Hour Meter Using the MSP430F471xx" for details.

Or

- Use AUXVCC1 instead of AUXVCC2 for backup supply

For scenario 2:
Limit the supply voltage ramp up time through a series resistor (e.g. 10 Ohm) in the critical supply path. Side effects such as voltage dips due to high current consumption of the device need to be considered.