SLAZ304AC October   2012  – May 2021 MSP430F5515

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      PN80
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  BSL6
    2. 6.2  BSL7
    3. 6.3  COMP10
    4. 6.4  CPU21
    5. 6.5  CPU22
    6. 6.6  CPU23
    7. 6.7  CPU26
    8. 6.8  CPU27
    9. 6.9  CPU28
    10. 6.10 CPU29
    11. 6.11 CPU30
    12. 6.12 CPU31
    13. 6.13 CPU32
    14. 6.14 CPU33
    15. 6.15 CPU34
    16. 6.16 CPU35
    17. 6.17 CPU37
    18. 6.18 CPU39
    19. 6.19 CPU40
    20. 6.20 CPU47
    21. 6.21 DMA4
    22. 6.22 DMA7
    23. 6.23 DMA8
    24. 6.24 DMA10
    25. 6.25 EEM9
    26. 6.26 EEM11
    27. 6.27 EEM13
    28. 6.28 EEM14
    29. 6.29 EEM15
    30. 6.30 EEM16
    31. 6.31 EEM17
    32. 6.32 EEM19
    33. 6.33 EEM21
    34. 6.34 EEM23
    35. 6.35 FLASH33
    36. 6.36 FLASH34
    37. 6.37 FLASH35
    38. 6.38 FLASH37
    39. 6.39 JTAG20
    40. 6.40 JTAG26
    41. 6.41 JTAG27
    42. 6.42 MPY1
    43. 6.43 PMAP1
    44. 6.44 PMM9
    45. 6.45 PMM10
    46. 6.46 PMM11
    47. 6.47 PMM12
    48. 6.48 PMM14
    49. 6.49 PMM15
    50. 6.50 PMM17
    51. 6.51 PMM18
    52. 6.52 PMM20
    53. 6.53 PORT15
    54. 6.54 PORT16
    55. 6.55 PORT19
    56. 6.56 PORT24
    57. 6.57 RTC3
    58. 6.58 RTC6
    59. 6.59 SYS10
    60. 6.60 SYS12
    61. 6.61 SYS14
    62. 6.62 SYS16
    63. 6.63 SYS18
    64. 6.64 TAB23
    65. 6.65 USB4
    66. 6.66 USB6
    67. 6.67 USB8
    68. 6.68 USB9
    69. 6.69 USB10
    70. 6.70 USB11
    71. 6.71 USB12
    72. 6.72 USB13
    73. 6.73 USCI26
    74. 6.74 USCI30
    75. 6.75 USCI31
    76. 6.76 USCI34
    77. 6.77 USCI35
    78. 6.78 USCI39
    79. 6.79 USCI40
    80. 6.80 WDG4
  7. 7Revision History

USCI30

USCI Module

Category

Functional

Function

I2C mode master receiver / slave receiver

Description

When the USCI I2C module is configured as a receiver (master or slave), it performs a double-buffered receive operation. In a transaction of two bytes, once the first byte is moved from the receive shift register to the receive buffer the byte is acknowledged and the state machine allows the reception of the next byte.

If the receive buffer has not been cleared of its contents by reading the UCBxRXBUF register while the 7th bit of the following data byte is being received, an error condition may occur on the I2C bus. Depending on the USCI configuration the following may occur:

1) If the USCI is configured as an I2C master receiver, an unintentional repeated start condition can be triggered or the master switches into an idle state (I2C communication aborted). The reception of the current data byte is not successful in this case.
2) If the USCI is configured as I2C slave receiver, the slave can switch to an idle state stalling I2C communication. The reception of the current data byte is not successful in this case. The USCI I2C state machine will notify the master of the aborted reception with a NACK.

Note that the error condition described above occurs only within a limited window of the 7th bit of the current byte being received. If the receive buffer is read outside of this window (before or after), then the error condition will not occur.

Workaround

a) The error condition can be avoided altogether by servicing the UCBxRXIFG in a timely manner. This can be done by (a) servicing the interrupt and ensuring UCBxRXBUF is read promptly or (b) Using the DMA to automatically read bytes from receive buffer upon UCBxRXIFG being set.

OR

b) In case the receive buffer cannot be read out in time, test the I2C clock line before the UCBxRXBUF is read out to ensure that the critical window has elapsed. This is done by checking if the clock line low status indicator bit UCSCLLOW is set for atleast three USCI bit clock cycles i.e. 3 X t(BitClock).

Note that the last byte of the transaction must be read directly from UCBxRXBUF. For all other bytes follow the workaround:

Code flow for workaround

(1) Enter RX ISR for reading receiving bytes
(2) Check if UCSCLLOW.UCBxSTAT == 1
(3) If no, repeat step 2 until set
(4) If yes, repeat step 2 for a time period > 3 x t (BitClock) where t (BitClock) = 1/ f (BitClock)
(5) If window of 3 x t(BitClock) cycles has elapsed, it is safe to read UCBxRXBUF