SLAZ283AA October   2012  – May 2021 MSP430F5435

 

  1.   1
  2.   2
  3.   3
  4.   4
  5.   5
    1.     6
    2.     7
      1.      8
    3.     9
  6.   10
    1.     11
    2.     12
    3.     13
    4.     14
    5.     15
    6.     16
    7.     17
    8.     18
    9.     19
    10.     20
    11.     21
    12.     22
    13.     23
    14.     24
    15.     25
    16.     26
    17.     27
    18.     28
    19.     29
    20.     30
    21.     31
    22.     32
    23.     33
    24.     34
    25.     35
    26.     36
    27.     37
    28.     38
    29.     39
    30.     40
    31.     41
    32.     42
    33.     43
    34.     44
    35.     45
    36.     46
    37.     47
    38.     48
    39.     49
    40.     50
    41.     51
    42.     52
    43.     53
    44.     54
    45.     55
    46.     56
    47.     57
    48.     58
    49.     59
    50.     60
    51.     61
    52.     62
    53.     63
    54.     64
    55.     65
    56.     66
    57.     67
    58.     68
    59.     69
    60.     70
    61.     71
    62.     72
    63.     73
    64.     74
    65.     75
    66.     76
    67.     77
    68.     78
    69.     79
    70.     80
    71.     81
    72.     82
    73.     83
    74.     84
    75.     85
    76.     86
    77.     87
    78.     88
    79.     89
    80.     90
    81.     91
    82.     92
    83.     93
    84.     94
    85.     95
    86.     96
    87.     97
    88.     98
    89.     99
    90.     100
    91.     101
    92.     102
    93.     103
    94.     104
    95.     105
    96.     106
    97.     107
    98.     108
    99.     109
    100.     110
    101.     111
    102.     112
    103.     113
    104.     114
    105.     115
    106.     116
    107.     117
    108.     118
    109.     119
    110.     120
    111.     121
    112.     122
    113.     123
    114.     124
    115.     125
    116.     126
    117.     127
    118.     128
  7.   129

6.91 SYS7

SYS Module

Category

Functional

Function

Timing of USCI interrupts may cause PC corruption due to automatic clear of an IFG

Description

When certain USCI I2C interrupt flags (IFG) are set and an automatic flag-clearing event on the I2C bus occurs, the address bus will default to FFFEh (Reset Vector) and the data bus to the opcode for the RETI instruction. This means the program counter defaults to FFFEh (Reset Vector) during this period of time. This will only happen when the IFG is cleared within a critical time window (~6 CPU clock cycles) after a USCI interrupt request occurs and before the interrupt servicing is initiated. The affected interrupts are UCBxTXIFG, UCSTPIFG, UCSTTIFG and UCNACKIFG.

The automatic flag-clearing scenarios are described in the following situations:
- A pending UCBxTXIFG interrupt request is cleared on the falling SCL clock edge following a NACK.
- A pending UCSTPIFG, UCSTTIFG, or UCNACKIFG interrupt request is cleared by a following Start condition.

If an NMI request occurs during the time that the PC holds the default value FFFEh before the default RETI instruction is executed, the PC will be corrupted on return from the NMI ISR. This is because the previous PC contents of FFFEh were stored onto the stack as the address of the next instruction to be executed. The CPU consequently interprets the address in FFFEh as an instruction (errant behavior) and because the default RETI was never executed, the stack pointer remains decreased by four (errant behavior).

Workaround

Prevent the flag-clearing event from interrupting the servicing of the affected USCI IFG's.
- Poll the affected USCI flags instead of enabling the interrupts.
or
- Ensure the above mentioned flag-clearing events occur after a time delay of 6 CPU clock cycles after the interrupt requests occur and are accepted.