SLAZ263AB October   2012  – August 2021 MSP430F5229

 

  1.   1
  2.   2
  3.   3
  4.   4
  5.   5
    1.     6
    2.     7
      1.      8
      2.      9
      3.      10
    3.     11
  6.   12
    1.     13
    2.     14
    3.     15
    4.     16
    5.     17
    6.     18
    7.     19
    8.     20
    9.     21
    10.     22
    11.     23
    12.     24
    13.     25
    14.     26
    15.     27
    16.     28
    17.     29
    18.     30
    19.     31
    20.     32
    21.     33
    22.     34
    23.     35
    24.     36
    25.     37
    26.     38
    27.     39
    28.     40
    29.     41
    30.     42
    31.     43
    32.     44
    33.     45
    34.     46
    35.     47
    36.     48
    37.     49
    38.     50
    39.     51
    40.     52
    41.     53
    42.     54
    43.     55
  7.   56

USCI35

USCI Module

Category

Functional

Function

Violation of setup and hold times for (repeated) start in I2C master mode

Description

In I2C master mode, the setup and hold times for a (repeated) START, tSU,STA and tHD,STA respectively, can be violated if SCL clock frequency is greater than 50kHz in standard mode (100kbps). As a result, a slave can receive incorrect data or the I2C bus can be stalled due to clock stretching by the slave.

Workaround

If using repeated start, ensure SCL clock frequencies is < 50kHz in I2C standard mode (100 kbps).