SLAZ249Z October   2012  – May 2021 MSP430F5152

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      DA38
      2.      RSB40
      3.      YFF40
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC39
    2. 6.2  ADC42
    3. 6.3  ADC69
    4. 6.4  BSL7
    5. 6.5  COMP10
    6. 6.6  CPU21
    7. 6.7  CPU22
    8. 6.8  CPU40
    9. 6.9  CPU46
    10. 6.10 CPU47
    11. 6.11 DMA4
    12. 6.12 DMA7
    13. 6.13 DMA10
    14. 6.14 EEM11
    15. 6.15 EEM17
    16. 6.16 EEM19
    17. 6.17 EEM21
    18. 6.18 EEM23
    19. 6.19 JTAG26
    20. 6.20 JTAG27
    21. 6.21 PMAP1
    22. 6.22 PMM14
    23. 6.23 PMM15
    24. 6.24 PMM18
    25. 6.25 PMM20
    26. 6.26 PMM26
    27. 6.27 PORT15
    28. 6.28 PORT19
    29. 6.29 PORT21
    30. 6.30 SYS12
    31. 6.31 SYS16
    32. 6.32 TD1
    33. 6.33 TD2
    34. 6.34 UCS9
    35. 6.35 UCS11
    36. 6.36 USCI26
    37. 6.37 USCI31
    38. 6.38 USCI34
    39. 6.39 USCI35
    40. 6.40 USCI39
    41. 6.41 USCI40
  7. 7Revision History

6.32 TD1

TD Module

Category

Functional

Function

Timer halt on EXTCLR event

Description

When the TEC module is configured to enable external asynchronous signals on the TECxCLR (TEC external clear) pin to clear the timer counter on the selected edge and the timer is halted after an external clear event but before next positive edge of the timer clock, then due to the erratum, it is not possible to write to the timer counter (TDxR) until the next positive timer clock edge occurrence. Halting of the timer right after an external clear event is possible if the system clock (MCLK) much greater than the Timer_D clock and the application halts the timer in the external clear interrupt service routine or if the application is doing random timer halts. This erratum does not cause any dead-lock conditions and the timer counter can be written into when the next positive timer clock edge is available.

Workaround

If required to halt the timer and change the timer counter value on an external clear event, wait until one timer clock period has elapsed to change the timer counter value.