SLAZ242O October   2012  – May 2021 MSP430F4784

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      PZ100
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  COMP3
    2. 6.2  CPU19
    3. 6.3  CPU44
    4. 6.4  EEM20
    5. 6.5  FLASH19
    6. 6.6  FLASH24
    7. 6.7  FLASH25
    8. 6.8  FLASH27
    9. 6.9  FLASH36
    10. 6.10 FLL4
    11. 6.11 FLL5
    12. 6.12 FLL6
    13. 6.13 FLL7
    14. 6.14 JTAG23
    15. 6.15 LCDA5
    16. 6.16 LCDA7
    17. 6.17 SDA4
    18. 6.18 TA12
    19. 6.19 TA16
    20. 6.20 TA21
    21. 6.21 TAB22
    22. 6.22 TB2
    23. 6.23 TB16
    24. 6.24 TB24
    25. 6.25 USCI15
    26. 6.26 USCI19
    27. 6.27 USCI20
    28. 6.28 USCI21
    29. 6.29 USCI22
    30. 6.30 USCI23
    31. 6.31 USCI24
    32. 6.32 USCI25
    33. 6.33 USCI26
    34. 6.34 USCI28
    35. 6.35 USCI30
    36. 6.36 USCI34
    37. 6.37 USCI35
    38. 6.38 USCI40
    39. 6.39 XOSC5
    40. 6.40 XOSC8
    41. 6.41 XOSC9
  7. 7Revision History

6.17 SDA4

SDA Module

Category

Functional

Function

Reduced SINAD performance at certain input voltage levels

Description

The performance of the SD16_A maybe degraded due to reduced SINAD when the level of the analog input is between 20mV and 120mV. This can occur on any channel, irrespective of their PGA settings.

Workaround

1. Avoid the use of any PGA settings less than 16 with the common-mode voltage of zero, which most likely accommodates input signal levels that fall under this range.
or
2. Introduce a common-mode voltage, such as internal reference voltage of 1.2 V, to ensure that the input signal level is outside the range of 20 mV to 120 mV.

The following table shows the SD16_A performance with common mode voltage of zero:


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