SLAZ222P October   2012  – May 2021 MSP430F46181

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      ZQW113
      2.      PZ100
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  CPU8
    2. 6.2  CPU16
    3. 6.3  CPU19
    4. 6.4  DMA3
    5. 6.5  DMA4
    6. 6.6  FLL3
    7. 6.7  FLL6
    8. 6.8  LCDA5
    9. 6.9  LCDA7
    10. 6.10 RTC1
    11. 6.11 TA12
    12. 6.12 TA16
    13. 6.13 TA18
    14. 6.14 TA21
    15. 6.15 TAB22
    16. 6.16 TB2
    17. 6.17 TB16
    18. 6.18 TB18
    19. 6.19 TB24
    20. 6.20 USCI16
    21. 6.21 USCI19
    22. 6.22 USCI20
    23. 6.23 USCI21
    24. 6.24 USCI22
    25. 6.25 USCI23
    26. 6.26 USCI24
    27. 6.27 USCI25
    28. 6.28 USCI26
    29. 6.29 USCI27
    30. 6.30 USCI30
    31. 6.31 USCI34
    32. 6.32 USCI35
    33. 6.33 USCI40
    34. 6.34 WDG2
    35. 6.35 XOSC5
    36. 6.36 XOSC8
    37. 6.37 XOSC9
  7. 7Revision History

6.3 CPU19

CPU Module

Category

Compiler-Fixed

Function

CPUOFF modification may result in unintentional register read

Description

If an instruction that modifies the CPUOFF bit in the Status Register is followed by an instruction with an indirect addressed operand (e.g. MOV @R8, R9, RET, POP, POPM), an unintentional register read operation can occur during the wakeup of the CPU. If the unintentional read occurs to a read sensitive register (e.g. UCB0RXBUF, TAIV), which changes its value or the value of other registers (IFG's), the bug leads to lost interrupts or wrong register read values.

Workaround

Insert a NOP instruction after each CPUOFF instruction.

OR

Refer to the table below for compiler-specific fix implementation information.
Note that compilers implementing the fix may lead to double stack usage when RET/RETA follows the compiler-inserted NOP.

IDE/Compiler Version Number Notes
IAR Embedded Workbench IAR EW430 v6.20.1 until v6.40 User is required to add the compiler or assembler flag option below. --hw_workaround=nop_after_lpm
IAR Embedded Workbench IAR EW430 v6.40 or later Workaround is automatically enabled
TI MSP430 Compiler Tools (Code Composer Studio) 15.12.0.LTS User is required to add the compiler or assembler flag option below. --silicon_errata=CPU19
MSP430 GNU Compiler (MSP430-GCC) MSP430-GCC 4.9 build 389 or later User is required to add the compiler or assembler flag option below. -msilicon-errata=cpu19 -msilicon-errata-warn=cpu19 generates a warning in addition
MSP430 GNU Compiler (MSP430-GCC) MSP430-GCC 5.x build 14 or later User is required to add the compiler or assembler flag option below. -msilicon-errata=cpu19 -msilicon-errata-warn=cpu19 generates a warning in addition