SLAZ194L October   2012  – May 2021 MSP430F4152

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      RGZ48
      2.      PM64
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  CPU4
    2. 6.2  CPU19
    3. 6.3  EEM20
    4. 6.4  FLASH19
    5. 6.5  FLASH24
    6. 6.6  FLASH27
    7. 6.7  FLL3
    8. 6.8  LCDA3
    9. 6.9  LCDA5
    10. 6.10 LCDA7
    11. 6.11 TA12
    12. 6.12 TA16
    13. 6.13 TA18
    14. 6.14 TA21
    15. 6.15 TAB22
    16. 6.16 USCI20
    17. 6.17 USCI22
    18. 6.18 USCI23
    19. 6.19 USCI24
    20. 6.20 USCI25
    21. 6.21 USCI26
    22. 6.22 USCI28
    23. 6.23 USCI30
    24. 6.24 USCI34
    25. 6.25 USCI35
    26. 6.26 USCI40
    27. 6.27 XOSC5
    28. 6.28 XOSC8
    29. 6.29 XOSC9
  7. 7Revision History

6.25 USCI35

USCI Module

Category

Functional

Function

Violation of setup and hold times for (repeated) start in I2C master mode

Description

In I2C master mode, the setup and hold times for a (repeated) START, tSU,STA and tHD,STA respectively, can be violated if SCL clock frequency is greater than 50kHz in standard mode (100kbps). As a result, a slave can receive incorrect data or the I2C bus can be stalled due to clock stretching by the slave.

Workaround

If using repeated start, ensure SCL clock frequencies is < 50kHz in I2C standard mode (100 kbps).