SLAZ187T October   2012  – May 2021 MSP430F2617

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      ZQW113
      2.      PM64
      3.      PN80
      4.      ZCA113
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC25
    2. 6.2  BCL12
    3. 6.3  BCL13
    4. 6.4  BCL15
    5. 6.5  CPU8
    6. 6.6  CPU16
    7. 6.7  CPU19
    8. 6.8  DAC4
    9. 6.9  DMA3
    10. 6.10 DMA4
    11. 6.11 DMA13
    12. 6.12 FLASH19
    13. 6.13 FLASH24
    14. 6.14 FLASH25
    15. 6.15 FLASH27
    16. 6.16 FLASH36
    17. 6.17 JTAG23
    18. 6.18 PORT10
    19. 6.19 PORT12
    20. 6.20 TA12
    21. 6.21 TA16
    22. 6.22 TA21
    23. 6.23 TAB22
    24. 6.24 TB2
    25. 6.25 TB16
    26. 6.26 TB24
    27. 6.27 USCI20
    28. 6.28 USCI21
    29. 6.29 USCI22
    30. 6.30 USCI23
    31. 6.31 USCI24
    32. 6.32 USCI25
    33. 6.33 USCI26
    34. 6.34 USCI27
    35. 6.35 USCI30
    36. 6.36 USCI34
    37. 6.37 USCI35
    38. 6.38 USCI40
    39. 6.39 XOSC5
    40. 6.40 XOSC8
  7. 7Revision History

6.7 CPU19

CPU Module

Category

Compiler-Fixed

Function

CPUOFF modification may result in unintentional register read

Description

If an instruction that modifies the CPUOFF bit in the Status Register is followed by an instruction with an indirect addressed operand (e.g. MOV @R8, R9, RET, POP, POPM), an unintentional register read operation can occur during the wakeup of the CPU. If the unintentional read occurs to a read sensitive register (e.g. UCB0RXBUF, TAIV), which changes its value or the value of other registers (IFG's), the bug leads to lost interrupts or wrong register read values.

Workaround

Insert a NOP instruction after each CPUOFF instruction.

OR

Refer to the table below for compiler-specific fix implementation information.
Note that compilers implementing the fix may lead to double stack usage when RET/RETA follows the compiler-inserted NOP.

IDE/Compiler Version Number Notes
IAR Embedded Workbench IAR EW430 v6.20.1 until v6.40 User is required to add the compiler or assembler flag option below. --hw_workaround=nop_after_lpm
IAR Embedded Workbench IAR EW430 v6.40 or later Workaround is automatically enabled
TI MSP430 Compiler Tools (Code Composer Studio) 15.12.0.LTS User is required to add the compiler or assembler flag option below. --silicon_errata=CPU19
MSP430 GNU Compiler (MSP430-GCC) MSP430-GCC 4.9 build 389 or later User is required to add the compiler or assembler flag option below. -msilicon-errata=cpu19 -msilicon-errata-warn=cpu19 generates a warning in addition
MSP430 GNU Compiler (MSP430-GCC) MSP430-GCC 5.x build 14 or later User is required to add the compiler or assembler flag option below. -msilicon-errata=cpu19 -msilicon-errata-warn=cpu19 generates a warning in addition